Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519516
R. Makki, K. Daneshvar, F. Tranjan, Richard Greene
We present a new Manufacturing-For-Test technology based on new physical methods of testing digital VLSIIULSI circuits for faults, which has the potential for much greater testing efjciency than possible by conventional electrical addressing through external pins alone. The method uses variants of the pulsed laser probing of microelectronic devices, and various holographic techniques of formation of virtual (transient) interconnects, together with electrical pulse testing, to greatly increase test coverage. Combined with a Design-for-Test scheme, the new technology can significantly improve fault coverage by allowing direct access to internal nodes. The new Manufacturing-For-Test method utilizes standard fabrication technologies and introduces only a small area overhead, and circuit loading; it has the promise of low cost in manufacture and test, and requires no significant increase in the number of physical chip connections.
{"title":"ON THE INTEGRATION OF DESIGN AND MANUFACTURING FOR IMPROVED TESTABILITY","authors":"R. Makki, K. Daneshvar, F. Tranjan, Richard Greene","doi":"10.1109/TEST.1991.519516","DOIUrl":"https://doi.org/10.1109/TEST.1991.519516","url":null,"abstract":"We present a new Manufacturing-For-Test technology based on new physical methods of testing digital VLSIIULSI circuits for faults, which has the potential for much greater testing efjciency than possible by conventional electrical addressing through external pins alone. The method uses variants of the pulsed laser probing of microelectronic devices, and various holographic techniques of formation of virtual (transient) interconnects, together with electrical pulse testing, to greatly increase test coverage. Combined with a Design-for-Test scheme, the new technology can significantly improve fault coverage by allowing direct access to internal nodes. The new Manufacturing-For-Test method utilizes standard fabrication technologies and introduces only a small area overhead, and circuit loading; it has the promise of low cost in manufacture and test, and requires no significant increase in the number of physical chip connections.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519723
S. Bollinger, S. Midkiff
This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.
{"title":"ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS","authors":"S. Bollinger, S. Midkiff","doi":"10.1109/TEST.1991.519723","DOIUrl":"https://doi.org/10.1109/TEST.1991.519723","url":null,"abstract":"This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519767
D. Organ
In device-oriented testing, the test program is created in terms of the device's data sheet. Timing diagrams are utilized. This paper examines some ambiguities and redundancies in timing diagrams found in data sheets with regard to automatic test generation. Their resolution is described in a partices is obvious. There are two cases where it becomes more difficult. First, some timing parameters may have both a minimum and a maximum value specified. The question is when to use which? Normally the solution is to use two-pass testing. The second situation is more difficult. There may be edges which must Conform to Several timing relaular device-oriented visual programming language.
{"title":"The enVision Timing Resolver","authors":"D. Organ","doi":"10.1109/TEST.1991.519767","DOIUrl":"https://doi.org/10.1109/TEST.1991.519767","url":null,"abstract":"In device-oriented testing, the test program is created in terms of the device's data sheet. Timing diagrams are utilized. This paper examines some ambiguities and redundancies in timing diagrams found in data sheets with regard to automatic test generation. Their resolution is described in a partices is obvious. There are two cases where it becomes more difficult. First, some timing parameters may have both a minimum and a maximum value specified. The question is when to use which? Normally the solution is to use two-pass testing. The second situation is more difficult. There may be edges which must Conform to Several timing relaular device-oriented visual programming language.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519511
G. Tromp
Generating minimal test sets for combinational circuits is a NP-hard problem. In this paper it will be shown that for a class of circuits with a high fnult compatibility well-known test set compaction methods such as dynamic compaction and reverse order fault simulation do not effectively minimize the test set. Furthermore it will be shown for a number of benchmark circuits that it is possible to generate test sets that are significantly smaller than test sets generated by conventional test set compaction methods. This paper will also present an algorithm based on finding a maximal clique in a graph to estimate the size of a minimum test set.
{"title":"Minimal Test Sets for Combinational Circuits","authors":"G. Tromp","doi":"10.1109/TEST.1991.519511","DOIUrl":"https://doi.org/10.1109/TEST.1991.519511","url":null,"abstract":"Generating minimal test sets for combinational circuits is a NP-hard problem. In this paper it will be shown that for a class of circuits with a high fnult compatibility well-known test set compaction methods such as dynamic compaction and reverse order fault simulation do not effectively minimize the test set. Furthermore it will be shown for a number of benchmark circuits that it is possible to generate test sets that are significantly smaller than test sets generated by conventional test set compaction methods. This paper will also present an algorithm based on finding a maximal clique in a graph to estimate the size of a minimum test set.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127248958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519705
Sally Wilk
This paper describes a Statistical Process Control (SPC) application to a WSI testec The application reviewed provides an accurate monitor of tester reliability as reported through stability, repeatability, and accuracy metrics using a calibrated external instrument. This SPC process conforms to MIL-M-38510 requirements.
{"title":"EFFECTIVE IMPLEMENTATION OF STATISTICAL PROCESS CONTROL IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT","authors":"Sally Wilk","doi":"10.1109/TEST.1991.519705","DOIUrl":"https://doi.org/10.1109/TEST.1991.519705","url":null,"abstract":"This paper describes a Statistical Process Control (SPC) application to a WSI testec The application reviewed provides an accurate monitor of tester reliability as reported through stability, repeatability, and accuracy metrics using a calibrated external instrument. This SPC process conforms to MIL-M-38510 requirements.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123885178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519720
G. Stenbakken, T., Michael Souders
Techniquesare presented for developinglinear error models for analog and mixed-signal devices. Methods for choosingparameters and assuring the models are complete and wellconditioned, are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices.
{"title":"LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES","authors":"G. Stenbakken, T., Michael Souders","doi":"10.1109/TEST.1991.519720","DOIUrl":"https://doi.org/10.1109/TEST.1991.519720","url":null,"abstract":"Techniquesare presented for developinglinear error models for analog and mixed-signal devices. Methods for choosingparameters and assuring the models are complete and wellconditioned, are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519721
A. Chatterjee
In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.
{"title":"CONCURRENT ERROR DETECTION IN LINEAR ANALOG AND SWITCHED-CAPACITOR STATE VARIABLE SYSTEMS USING CONT","authors":"A. Chatterjee","doi":"10.1109/TEST.1991.519721","DOIUrl":"https://doi.org/10.1109/TEST.1991.519721","url":null,"abstract":"In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519718
Y. Morooka, S. Mori, H. Miyamoto, M. Yamada
This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.
{"title":"AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS","authors":"Y. Morooka, S. Mori, H. Miyamoto, M. Yamada","doi":"10.1109/TEST.1991.519718","DOIUrl":"https://doi.org/10.1109/TEST.1991.519718","url":null,"abstract":"This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519740
B. Murray, J. Hayes
Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.
{"title":"Test Propagation Through Modules and Circuits","authors":"B. Murray, J. Hayes","doi":"10.1109/TEST.1991.519740","DOIUrl":"https://doi.org/10.1109/TEST.1991.519740","url":null,"abstract":"Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519703
Gary J. Lesmeister
+zero Time Mux - tap path CMOS, when applied with a closed-loop, fast path design methodology, is a viable choice as the core technology for a densely integrated high performance integrated circuit tester.
{"title":"A DENSELY INTEGRATED HIGH PERFORMANCE CMOS TESTER","authors":"Gary J. Lesmeister","doi":"10.1109/TEST.1991.519703","DOIUrl":"https://doi.org/10.1109/TEST.1991.519703","url":null,"abstract":"+zero Time Mux - tap path CMOS, when applied with a closed-loop, fast path design methodology, is a viable choice as the core technology for a densely integrated high performance integrated circuit tester.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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