Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519516
R. Makki, K. Daneshvar, F. Tranjan, Richard Greene
We present a new Manufacturing-For-Test technology based on new physical methods of testing digital VLSIIULSI circuits for faults, which has the potential for much greater testing efjciency than possible by conventional electrical addressing through external pins alone. The method uses variants of the pulsed laser probing of microelectronic devices, and various holographic techniques of formation of virtual (transient) interconnects, together with electrical pulse testing, to greatly increase test coverage. Combined with a Design-for-Test scheme, the new technology can significantly improve fault coverage by allowing direct access to internal nodes. The new Manufacturing-For-Test method utilizes standard fabrication technologies and introduces only a small area overhead, and circuit loading; it has the promise of low cost in manufacture and test, and requires no significant increase in the number of physical chip connections.
{"title":"ON THE INTEGRATION OF DESIGN AND MANUFACTURING FOR IMPROVED TESTABILITY","authors":"R. Makki, K. Daneshvar, F. Tranjan, Richard Greene","doi":"10.1109/TEST.1991.519516","DOIUrl":"https://doi.org/10.1109/TEST.1991.519516","url":null,"abstract":"We present a new Manufacturing-For-Test technology based on new physical methods of testing digital VLSIIULSI circuits for faults, which has the potential for much greater testing efjciency than possible by conventional electrical addressing through external pins alone. The method uses variants of the pulsed laser probing of microelectronic devices, and various holographic techniques of formation of virtual (transient) interconnects, together with electrical pulse testing, to greatly increase test coverage. Combined with a Design-for-Test scheme, the new technology can significantly improve fault coverage by allowing direct access to internal nodes. The new Manufacturing-For-Test method utilizes standard fabrication technologies and introduces only a small area overhead, and circuit loading; it has the promise of low cost in manufacture and test, and requires no significant increase in the number of physical chip connections.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519723
S. Bollinger, S. Midkiff
This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.
{"title":"ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS","authors":"S. Bollinger, S. Midkiff","doi":"10.1109/TEST.1991.519723","DOIUrl":"https://doi.org/10.1109/TEST.1991.519723","url":null,"abstract":"This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519767
D. Organ
In device-oriented testing, the test program is created in terms of the device's data sheet. Timing diagrams are utilized. This paper examines some ambiguities and redundancies in timing diagrams found in data sheets with regard to automatic test generation. Their resolution is described in a partices is obvious. There are two cases where it becomes more difficult. First, some timing parameters may have both a minimum and a maximum value specified. The question is when to use which? Normally the solution is to use two-pass testing. The second situation is more difficult. There may be edges which must Conform to Several timing relaular device-oriented visual programming language.
{"title":"The enVision Timing Resolver","authors":"D. Organ","doi":"10.1109/TEST.1991.519767","DOIUrl":"https://doi.org/10.1109/TEST.1991.519767","url":null,"abstract":"In device-oriented testing, the test program is created in terms of the device's data sheet. Timing diagrams are utilized. This paper examines some ambiguities and redundancies in timing diagrams found in data sheets with regard to automatic test generation. Their resolution is described in a partices is obvious. There are two cases where it becomes more difficult. First, some timing parameters may have both a minimum and a maximum value specified. The question is when to use which? Normally the solution is to use two-pass testing. The second situation is more difficult. There may be edges which must Conform to Several timing relaular device-oriented visual programming language.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519713
R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio
Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.
{"title":"CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS","authors":"R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio","doi":"10.1109/TEST.1991.519713","DOIUrl":"https://doi.org/10.1109/TEST.1991.519713","url":null,"abstract":"Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114582005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519522
C. Henderson, J. Soden, C. Hawkins
The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.
{"title":"THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS","authors":"C. Henderson, J. Soden, C. Hawkins","doi":"10.1109/TEST.1991.519522","DOIUrl":"https://doi.org/10.1109/TEST.1991.519522","url":null,"abstract":"The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128531072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519489
S. Sarma
The intent of this paper is to describe the built-in-self-test (BIST) design and verification methodology followed for thermal conduction modules (TCMs) in the aircooled IBM Enterprise System/9000 Type 9121 processors. The ES/9121 processor utilizes a mixture of bipolar and CMOS circuitry. Each ES/9121 processor TCM can accommodate a maximum of 121 logic and memory chips. There are five distinct TCMs in the uniprocessor configuration and the testability results achieved using BIST will be presented in this paper. The resources required to support the BIST process will also be presented. Finally, improvements to the BIST methodology will be discussed.
{"title":"Built-in-self-test considerations in a high-performance, general-purpose processor","authors":"S. Sarma","doi":"10.1109/TEST.1991.519489","DOIUrl":"https://doi.org/10.1109/TEST.1991.519489","url":null,"abstract":"The intent of this paper is to describe the built-in-self-test (BIST) design and verification methodology followed for thermal conduction modules (TCMs) in the aircooled IBM Enterprise System/9000 Type 9121 processors. The ES/9121 processor utilizes a mixture of bipolar and CMOS circuitry. Each ES/9121 processor TCM can accommodate a maximum of 121 logic and memory chips. There are five distinct TCMs in the uniprocessor configuration and the testability results achieved using BIST will be presented in this paper. The resources required to support the BIST process will also be presented. Finally, improvements to the BIST methodology will be discussed.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519703
Gary J. Lesmeister
+zero Time Mux - tap path CMOS, when applied with a closed-loop, fast path design methodology, is a viable choice as the core technology for a densely integrated high performance integrated circuit tester.
{"title":"A DENSELY INTEGRATED HIGH PERFORMANCE CMOS TESTER","authors":"Gary J. Lesmeister","doi":"10.1109/TEST.1991.519703","DOIUrl":"https://doi.org/10.1109/TEST.1991.519703","url":null,"abstract":"+zero Time Mux - tap path CMOS, when applied with a closed-loop, fast path design methodology, is a viable choice as the core technology for a densely integrated high performance integrated circuit tester.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519695
P. Maxwell, R. Aitken, V. Johansen, I. Chiang
This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.
{"title":"THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%?","authors":"P. Maxwell, R. Aitken, V. Johansen, I. Chiang","doi":"10.1109/TEST.1991.519695","DOIUrl":"https://doi.org/10.1109/TEST.1991.519695","url":null,"abstract":"This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519741
M. Hâncu, K. Iwasaki, Yuji Sato, M. Sugie
New principles for the on-line system-level test of multiprocessors are proposed, based on signaturing and monitoring data dependences together with control dependences. I n order to help in this process, each data routing message contains both source and destination addresses. At each message source, the destination addresses of the outgoing messages are compressed. At the same time, at each destination, the source addresses of all incoming messages are compressed. Concurrent compression of the instructions executed by the PES is also possible. The resulting signatures are compared at the end of each computational block with reference signatures created at compilation time. An analytical model and an analysis for the address compression process used for the monitoring the data routing process are provided. The aliasing probability for the error detection process is studied, obtaining closedform expressions in the single error case and upper bounds in the multiple error case.
{"title":"A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR DETECTION CAPABILITY","authors":"M. Hâncu, K. Iwasaki, Yuji Sato, M. Sugie","doi":"10.1109/TEST.1991.519741","DOIUrl":"https://doi.org/10.1109/TEST.1991.519741","url":null,"abstract":"New principles for the on-line system-level test of multiprocessors are proposed, based on signaturing and monitoring data dependences together with control dependences. I n order to help in this process, each data routing message contains both source and destination addresses. At each message source, the destination addresses of the outgoing messages are compressed. At the same time, at each destination, the source addresses of all incoming messages are compressed. Concurrent compression of the instructions executed by the PES is also possible. The resulting signatures are compared at the end of each computational block with reference signatures created at compilation time. An analytical model and an analysis for the address compression process used for the monitoring the data routing process are provided. The aliasing probability for the error detection process is studied, obtaining closedform expressions in the single error case and upper bounds in the multiple error case.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115067618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519718
Y. Morooka, S. Mori, H. Miyamoto, M. Yamada
This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.
{"title":"AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS","authors":"Y. Morooka, S. Mori, H. Miyamoto, M. Yamada","doi":"10.1109/TEST.1991.519718","DOIUrl":"https://doi.org/10.1109/TEST.1991.519718","url":null,"abstract":"This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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