Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519785
Paul D. Roddy
Software testing is any activity aimed at evaluating an attribute or capability of a program or system and determining that it meets its required results. [Hetzel88] Although crucial to software quality and widely deployed by programmers and testers, software testing still remains an art, due to limited understanding of the principles of software. The difficulty in software testing stems from the complexity of software: we can not completely test a program with moderate complexity. Testing is more than just debugging. The purpose of testing can be quality assurance, verification and validation, or reliability estimation. Testing can be used as a generic metric as well. Correctness testing and reliability testing are two major areas of testing. Software testing is a trade-off between budget, time and quality.
{"title":"SOFTWARE TESTING","authors":"Paul D. Roddy","doi":"10.1109/TEST.1991.519785","DOIUrl":"https://doi.org/10.1109/TEST.1991.519785","url":null,"abstract":"Software testing is any activity aimed at evaluating an attribute or capability of a program or system and determining that it meets its required results. [Hetzel88] Although crucial to software quality and widely deployed by programmers and testers, software testing still remains an art, due to limited understanding of the principles of software. The difficulty in software testing stems from the complexity of software: we can not completely test a program with moderate complexity. Testing is more than just debugging. The purpose of testing can be quality assurance, verification and validation, or reliability estimation. Testing can be used as a generic metric as well. Correctness testing and reliability testing are two major areas of testing. Software testing is a trade-off between budget, time and quality.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519508
M. Abadir, Joe Newman, D. D'Souza, Steve Spencer
This paper describes the partitioning subsystem of MCC's Testability Insertion Guidance ExpeRt system (TIGER) [2]. TIGER addresses Design for Testability issues by employing a divide and conquer strategy which permits auser to analyze testability problems early in a design cycle, and make intelligent decisions about the applicability of various test methods to circuit partitions. This paper describes the methodology used in Tiger to partition hierarchical designs for test purposes.
{"title":"PARTITIONING HIERARCHICAL DESIGNS FOR TESTABILITY","authors":"M. Abadir, Joe Newman, D. D'Souza, Steve Spencer","doi":"10.1109/TEST.1991.519508","DOIUrl":"https://doi.org/10.1109/TEST.1991.519508","url":null,"abstract":"This paper describes the partitioning subsystem of MCC's Testability Insertion Guidance ExpeRt system (TIGER) [2]. TIGER addresses Design for Testability issues by employing a divide and conquer strategy which permits auser to analyze testability problems early in a design cycle, and make intelligent decisions about the applicability of various test methods to circuit partitions. This paper describes the methodology used in Tiger to partition hierarchical designs for test purposes.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129399964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519698
Sean P. Morley, R. Marlett
Partial scan is an increasingly popular testability solution, but the test program length it requires is a growing concern. This paper proposes a selectable length sican implementation that can dramatically reduce the shifting requirements. Equations are developed, based on a statistical approach, to predict the reduction. A practical methodology to implement the technique is presented. 'The easily calculated estimate is shown to be in excellent agreement with actual results. This technique uses the sizme number of test pins as other scan methods, compliles with industry standards, is broadly applicable, and has provided greater than 70% test program length reduction on .a variety of commercially designed circuits.
{"title":"Selectable Length Partial Scan: A Method to Reduce Vector Length","authors":"Sean P. Morley, R. Marlett","doi":"10.1109/TEST.1991.519698","DOIUrl":"https://doi.org/10.1109/TEST.1991.519698","url":null,"abstract":"Partial scan is an increasingly popular testability solution, but the test program length it requires is a growing concern. This paper proposes a selectable length sican implementation that can dramatically reduce the shifting requirements. Equations are developed, based on a statistical approach, to predict the reduction. A practical methodology to implement the technique is presented. 'The easily calculated estimate is shown to be in excellent agreement with actual results. This technique uses the sizme number of test pins as other scan methods, compliles with industry standards, is broadly applicable, and has provided greater than 70% test program length reduction on .a variety of commercially designed circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519497
Tsu-Wei Ku, Wei-Kong Chia
This paper combines the advantages of forward and reverse time approaches to generate the test vectors for a sequential circuit. The algorithm uses PODEM and nine-value logic model. Two new classes of faults called 0-step and 1-step testable faults are defined. The tests for these faults are generated based on known states. These faults are regarded as easy-to-test because the justification and propagation sequences are already known. The percentages of such faults are experimented for MCNC benchmark circuits. Fault simulation of the vectors for such faults is fast because fault simulation of justification sequences is not needed. Fewer test vectors is needed when a fault is identified as 0-step and 1-step testable because the justification sequence of the fault can be shared with other faults. The tests €or the faults other than 0-step and 1-step testable faults are obtained using partial state enumeration, fault free justification and propagation method. The program is written on top of STEED which is a UC Berkley sequential test generator. The CPU time improvement can be up to 150% faster SEED and the number of test vectors can be 38% less than the set generated by STEED.
{"title":"A Sequential Test Generator with Explicit Elimination of Easy-To-Test Faults","authors":"Tsu-Wei Ku, Wei-Kong Chia","doi":"10.1109/TEST.1991.519497","DOIUrl":"https://doi.org/10.1109/TEST.1991.519497","url":null,"abstract":"This paper combines the advantages of forward and reverse time approaches to generate the test vectors for a sequential circuit. The algorithm uses PODEM and nine-value logic model. Two new classes of faults called 0-step and 1-step testable faults are defined. The tests for these faults are generated based on known states. These faults are regarded as easy-to-test because the justification and propagation sequences are already known. The percentages of such faults are experimented for MCNC benchmark circuits. Fault simulation of the vectors for such faults is fast because fault simulation of justification sequences is not needed. Fewer test vectors is needed when a fault is identified as 0-step and 1-step testable because the justification sequence of the fault can be shared with other faults. The tests €or the faults other than 0-step and 1-step testable faults are obtained using partial state enumeration, fault free justification and propagation method. The program is written on top of STEED which is a UC Berkley sequential test generator. The CPU time improvement can be up to 150% faster SEED and the number of test vectors can be 38% less than the set generated by STEED.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519749
V. Iyengar, G. Vijayan
The increasing emphasis on AC testing of integrated circuits is driven by the combination of tighter quality requirements and sensitivity of high performance circuits to delay defects. The areas of fault modeling, fault simulation and test generation as applied to AC testing have received most of the attention so far. The relatively unexplored side of AC test is the determination of the test application timing. Tight timings during test application are crucial to the success of the AC test. This paper formulates the problem of generating tight test application timings and presents some sample results using a heuristic algorithm.
{"title":"Test Application Timing: The Unexplored Issue in AC Test","authors":"V. Iyengar, G. Vijayan","doi":"10.1109/TEST.1991.519749","DOIUrl":"https://doi.org/10.1109/TEST.1991.519749","url":null,"abstract":"The increasing emphasis on AC testing of integrated circuits is driven by the combination of tighter quality requirements and sensitivity of high performance circuits to delay defects. The areas of fault modeling, fault simulation and test generation as applied to AC testing have received most of the attention so far. The relatively unexplored side of AC test is the determination of the test application timing. Tight timings during test application are crucial to the success of the AC test. This paper formulates the problem of generating tight test application timings and presents some sample results using a heuristic algorithm.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127722399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519742
D. Bhavsar
Tbts paper presents an arclcecrute for niakms the EEE Standard 1139.1 lest acces port did dl it? major provisions available on a system b~ckplaae It proposes a powerful. low-cost alternabve for system-wide comnim~ication for test and mamtenance purposes. using one chip-to-system test access protocol The bus interconnectton method employed in the xchtecture inherently accommcdates enipty slots in arbitrary posinom in the system back-plane without Qsrupnng the test bus connecavity or the test conimumcatlons
{"title":"An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes","authors":"D. Bhavsar","doi":"10.1109/TEST.1991.519742","DOIUrl":"https://doi.org/10.1109/TEST.1991.519742","url":null,"abstract":"Tbts paper presents an arclcecrute for niakms the EEE Standard 1139.1 lest acces port did dl it? major provisions available on a system b~ckplaae It proposes a powerful. low-cost alternabve for system-wide comnim~ication for test and mamtenance purposes. using one chip-to-system test access protocol The bus interconnectton method employed in the xchtecture inherently accommcdates enipty slots in arbitrary posinom in the system back-plane without Qsrupnng the test bus connecavity or the test conimumcatlons","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128003476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519739
M. Karam, R. Leveugle, G. Saucier
A hierarchical test generation method is presented which is based on a functional approach to guide backward and forward propagations. The proposed algorithm permits solving most propagation conflicts by taking advantage of the functionality of the implemented block and avoids costly unnecessary design modifications. It has been implemented and its effectiveness has been proved on a set of datapaths. The formalism and the algorithms are general enough to handle any type of synchronous digital circuit.
{"title":"Hierarchical Test Generation Based on Delayed Propagation","authors":"M. Karam, R. Leveugle, G. Saucier","doi":"10.1109/TEST.1991.519739","DOIUrl":"https://doi.org/10.1109/TEST.1991.519739","url":null,"abstract":"A hierarchical test generation method is presented which is based on a functional approach to guide backward and forward propagations. The proposed algorithm permits solving most propagation conflicts by taking advantage of the functionality of the implemented block and avoids costly unnecessary design modifications. It has been implemented and its effectiveness has been proved on a set of datapaths. The formalism and the algorithms are general enough to handle any type of synchronous digital circuit.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"96 7-12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121028583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519724
E. Vandris, G. Sobelman
A mixed functional/IDDQ testing methodology is presented for detecting transistor faults in CMOS VLSI circuits. A fault preprocessor and a fast switch-level fault simulator have been developed for implementing this testing methodology. The fault preprocessor performs fault generation and collapsing of CMOS transistor faults and identifies those transistor faults that are undetectable by functional testing. Faults that are detectable by functional testing are simulated by the switch-level fault simulator using logic monitoring of the circuit outputs. Faults that are deterministically undetectable by functional testing are considered for detection by monitoring the IDDQ current. These faults are detected if they create conducting transistor paths between VDD and GND, thus elevating IDDQ. By using accurate electrical evaluation techniques of the switch-level circuit state the number of faults that are determined to be detectable by functional testing is increased and the corresponding number of faults requiring IDDQ testing is decreased. This decreases the number of test vectors where IDDQ testing is required and therefore minimizes the total test time.
{"title":"A MIXED FUNCTIONAL/IDDQ TESTING METHODOLOGY FOR CMOS TRANSISTOR FAULTS","authors":"E. Vandris, G. Sobelman","doi":"10.1109/TEST.1991.519724","DOIUrl":"https://doi.org/10.1109/TEST.1991.519724","url":null,"abstract":"A mixed functional/IDDQ testing methodology is presented for detecting transistor faults in CMOS VLSI circuits. A fault preprocessor and a fast switch-level fault simulator have been developed for implementing this testing methodology. The fault preprocessor performs fault generation and collapsing of CMOS transistor faults and identifies those transistor faults that are undetectable by functional testing. Faults that are detectable by functional testing are simulated by the switch-level fault simulator using logic monitoring of the circuit outputs. Faults that are deterministically undetectable by functional testing are considered for detection by monitoring the IDDQ current. These faults are detected if they create conducting transistor paths between VDD and GND, thus elevating IDDQ. By using accurate electrical evaluation techniques of the switch-level circuit state the number of faults that are determined to be detectable by functional testing is increased and the corresponding number of faults requiring IDDQ testing is decreased. This decreases the number of test vectors where IDDQ testing is required and therefore minimizes the total test time.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"184 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121127289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519525
V. Pitchumani, Pankaj Mayor, N. Radia
This paper describes algorithms for fault diagnosis of computer hardware modeled in VHDL [1,2,3,4]. Given a VHDL description, the compiler creates an internal representation. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.
{"title":"Fault Diagnosis using Functional Fault Models for VHDL descriptions","authors":"V. Pitchumani, Pankaj Mayor, N. Radia","doi":"10.1109/TEST.1991.519525","DOIUrl":"https://doi.org/10.1109/TEST.1991.519525","url":null,"abstract":"This paper describes algorithms for fault diagnosis of computer hardware modeled in VHDL [1,2,3,4]. Given a VHDL description, the compiler creates an internal representation. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122990282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519774
K. Karube, Y. Bessho, T. Takakura, K. Gunji
Koji Karube, Yoshiyuki Bessho, Tokuo Takakura, and Keita Gunji Yokogawa Hewlett-Packard 9-1, Takakura-cho, Hachioji, Tokyo JAPAN 192 W? developed a new arclzitechire tester iit which each resource has a local real-time digital signal processor (DSP) that enables the tester to peifonn wious applications. Previous&, this was difficult to do becaiue it required a yea t deal of nienioiy. Die tester calif also p e ~ o n i z real-tiine data processiiig, tlziis eliiiiiiiatiig the specialized hardware that is required for complicated nttixed-sigrzal device tests. Dzis paper not on@ show tlze liijuitatioizs related to previous arclzitectures, but also shows how ta use the tester to yerfoini ISDN tests mid the izewly developed ADC test.
{"title":"ADVANCED MIXED SIGNAL TESTING BY DSP LOCALIZED TESTER","authors":"K. Karube, Y. Bessho, T. Takakura, K. Gunji","doi":"10.1109/TEST.1991.519774","DOIUrl":"https://doi.org/10.1109/TEST.1991.519774","url":null,"abstract":"Koji Karube, Yoshiyuki Bessho, Tokuo Takakura, and Keita Gunji Yokogawa Hewlett-Packard 9-1, Takakura-cho, Hachioji, Tokyo JAPAN 192 W? developed a new arclzitechire tester iit which each resource has a local real-time digital signal processor (DSP) that enables the tester to peifonn wious applications. Previous&, this was difficult to do becaiue it required a yea t deal of nienioiy. Die tester calif also p e ~ o n i z real-tiine data processiiig, tlziis eliiiiiiiatiig the specialized hardware that is required for complicated nttixed-sigrzal device tests. Dzis paper not on@ show tlze liijuitatioizs related to previous arclzitectures, but also shows how ta use the tester to yerfoini ISDN tests mid the izewly developed ADC test.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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