Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519520
R. Parekhji, G. Venkatesh, S. Sherlekar
This papcl . presents a formal framework for designing self-checking sequen,tial circuits implemented using the monitoriry machine approach. The two main contributions of this paper are: (1) the formulation of the problcm of &;signing an optimal monitoring machine for arbitrcwy fault m,odcls as the problem of minimizi n g an incompletely specified sequential machine, and (2) rlc?iclopin,g a methodology for performing state assignment which results in the monitoring machine hauiruj (L fized number of states for specific fault models. Thx method allows the designer to ezplorc the tradeofl8 between the cost of implementing the main machine and the mon,itoring machine.
{"title":"A Methodology for Designing Optimal Self-Checking Sequential Circuits","authors":"R. Parekhji, G. Venkatesh, S. Sherlekar","doi":"10.1109/TEST.1991.519520","DOIUrl":"https://doi.org/10.1109/TEST.1991.519520","url":null,"abstract":"This papcl . presents a formal framework for designing self-checking sequen,tial circuits implemented using the monitoriry machine approach. The two main contributions of this paper are: (1) the formulation of the problcm of &;signing an optimal monitoring machine for arbitrcwy fault m,odcls as the problem of minimizi n g an incompletely specified sequential machine, and (2) rlc?iclopin,g a methodology for performing state assignment which results in the monitoring machine hauiruj (L fized number of states for specific fault models. Thx method allows the designer to ezplorc the tradeofl8 between the cost of implementing the main machine and the mon,itoring machine.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"80 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519786
T. Gheewala
Test automation refers to the automatic development of test and diagnostics programs for ICs, printed circuit boards and systems. For all practical purposes, it requires the addition of test circuits on the IC to provide controllability and/or observability of signals. Internal scan, Crosscheck and boundary scan are examples of on-chip test structures that permit automatic test program dwelopment.
{"title":"For Test Automation, Silicon is Free","authors":"T. Gheewala","doi":"10.1109/TEST.1991.519786","DOIUrl":"https://doi.org/10.1109/TEST.1991.519786","url":null,"abstract":"Test automation refers to the automatic development of test and diagnostics programs for ICs, printed circuit boards and systems. For all practical purposes, it requires the addition of test circuits on the IC to provide controllability and/or observability of signals. Internal scan, Crosscheck and boundary scan are examples of on-chip test structures that permit automatic test program dwelopment.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124170038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519781
C. Pyron
The EDIF Test View is a proposed extenslion to the existing EIA/ANSI standard, EDIF 2 0 0. The current EDIF version supports neutral data interchange formats for electronic data such as schematics, netlists, and mask layouts. The addition of the EDIF Test View will provide an industry standard for the interchange of test data. EDIF Test supports the exchange of information such as test vectors between Computer-Aided Engineering (CAE) and Automatic Test Equipment (ATE) systems. The data model of the EDIF Test View proposal is currently available as the EDIF Version 2 0 3 1 [I].
EDIF测试视图是对现有EIA/ANSI标准EDIF 2.0的建议扩展。当前的EDIF版本支持电子数据的中立数据交换格式，如原理图、网络列表和掩码布局。EDIF测试视图的添加将为测试数据的交换提供一个行业标准。EDIF Test支持在计算机辅助工程(CAE)和自动测试设备(ATE)系统之间交换诸如测试向量之类的信息。EDIF测试视图建议的数据模型目前作为EDIF Version 2 0 31 [I]可用。
{"title":"Representing Boundary Scan Tests with the EDIF Test View","authors":"C. Pyron","doi":"10.1109/TEST.1991.519781","DOIUrl":"https://doi.org/10.1109/TEST.1991.519781","url":null,"abstract":"The EDIF Test View is a proposed extenslion to the existing EIA/ANSI standard, EDIF 2 0 0. The current EDIF version supports neutral data interchange formats for electronic data such as schematics, netlists, and mask layouts. The addition of the EDIF Test View will provide an industry standard for the interchange of test data. EDIF Test supports the exchange of information such as test vectors between Computer-Aided Engineering (CAE) and Automatic Test Equipment (ATE) systems. The data model of the EDIF Test View proposal is currently available as the EDIF Version 2 0 3 1 [I].","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116911209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519770
S. Bandyopadhyay, B. Bhattacharya
This paper presents a new testable design scheme appli- cable to any arbitrary 1-dimensional bilateral systolic array. The hardware overhead is a global control he and a small amount of additional logic per cell . The proposed design ensures that all cells in the array can simultaneously be set to any state in constant steps after initialization, regardless of the size of the array. The design also supports propaga- tion of test outcomes to observable exiremitles so that the where IVI is the number of states per cell and N is the number
{"title":"ON THE TESTABLE DESIGN OF BILATERAL BIT-LEVEL SYSTOLIC ARRAYS","authors":"S. Bandyopadhyay, B. Bhattacharya","doi":"10.1109/TEST.1991.519770","DOIUrl":"https://doi.org/10.1109/TEST.1991.519770","url":null,"abstract":"This paper presents a new testable design scheme appli- cable to any arbitrary 1-dimensional bilateral systolic array. The hardware overhead is a global control he and a small amount of additional logic per cell . The proposed design ensures that all cells in the array can simultaneously be set to any state in constant steps after initialization, regardless of the size of the array. The design also supports propaga- tion of test outcomes to observable exiremitles so that the where IVI is the number of states per cell and N is the number","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125855653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519748
M. Karpovsky, S. Gupta, D. Pradhan
A number of methods have been proposed to study aliasing in MISR compression. However, most of the methods can compute aliasing probability only for specific test lengths and/or specific error models. Recently, a GLFSR structure [15] was introduced which admits coding theory formulation. The conventional signature analyzers such as LFSR and MISR form special cases of this GLFSR structure. Using this formulation, a general result is now presented which computes the exact aliasing probability for MISRs with primitive feedback polynomials, for any test length and for any error model. The framework is then extended to study the probability of correct diagnosis when faulty signature is used to identify the faulty CUT in the STUMPS environment. Specifically, the results in [7, 15, 161 are extended by proposing two new error models, a general error model which subsumes all the commonly used models, and a fixed magnitude error model which is shown to be useful for fault diagnosis. It is shown how statistical simulation can be used to determine the general error model, for a given CUT. Aliasing for some benchmark circuits, for various error models and test lengths is studied.
{"title":"Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model","authors":"M. Karpovsky, S. Gupta, D. Pradhan","doi":"10.1109/TEST.1991.519748","DOIUrl":"https://doi.org/10.1109/TEST.1991.519748","url":null,"abstract":"A number of methods have been proposed to study aliasing in MISR compression. However, most of the methods can compute aliasing probability only for specific test lengths and/or specific error models. Recently, a GLFSR structure [15] was introduced which admits coding theory formulation. The conventional signature analyzers such as LFSR and MISR form special cases of this GLFSR structure. Using this formulation, a general result is now presented which computes the exact aliasing probability for MISRs with primitive feedback polynomials, for any test length and for any error model. The framework is then extended to study the probability of correct diagnosis when faulty signature is used to identify the faulty CUT in the STUMPS environment. Specifically, the results in [7, 15, 161 are extended by proposing two new error models, a general error model which subsumes all the commonly used models, and a fixed magnitude error model which is shown to be useful for fault diagnosis. It is shown how statistical simulation can be used to determine the general error model, for a given CUT. Aliasing for some benchmark circuits, for various error models and test lengths is studied.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519756
E. Park, Bill Underwood, T. Williams, M. R. Mercer
As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.
{"title":"Delay Testing Quality in Timing-Optimized Designs","authors":"E. Park, Bill Underwood, T. Williams, M. R. Mercer","doi":"10.1109/TEST.1991.519756","DOIUrl":"https://doi.org/10.1109/TEST.1991.519756","url":null,"abstract":"As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519715
R.W. Bassett, P. S. Gillis, John J. Shushereba
Muhichip-module ( M C M ) packages have been developed for use with high-density, high-performance CMOS chip technologies. The combination of CMOS and multichip packaging poses, new test-related challenges arising from the resulting v e 9 large circuit and signal inputloutput counts, and from CMOS-related reliability requirements. This paper discusses current practice and indicates jidture directions for MCM assembly, testing, and diagnosis.
{"title":"HIGH-DENSITY CMOS MULTICHIP-MODULE TESTING AND DIAGNOSIS","authors":"R.W. Bassett, P. S. Gillis, John J. Shushereba","doi":"10.1109/TEST.1991.519715","DOIUrl":"https://doi.org/10.1109/TEST.1991.519715","url":null,"abstract":"Muhichip-module ( M C M ) packages have been developed for use with high-density, high-performance CMOS chip technologies. The combination of CMOS and multichip packaging poses, new test-related challenges arising from the resulting v e 9 large circuit and signal inputloutput counts, and from CMOS-related reliability requirements. This paper discusses current practice and indicates jidture directions for MCM assembly, testing, and diagnosis.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126279432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519782
Ted W. Gary
Practices for software testing vary greatly. In most companies, software testing is performed by the developers who test informally aspart of their debugging activity. Some companies have formal test requirements. In such cases, dedicated software testing tools are often used, and testing is a separate activity performed near the end of the software development cycle. A few companies have a formally defined sofiware development process which utilizes testing and metrics throughout the development process. All companies recognize the need to improve software quality and are seeking additional tools and processes to assist them.
{"title":"Software Testing, the State of the Practice","authors":"Ted W. Gary","doi":"10.1109/TEST.1991.519782","DOIUrl":"https://doi.org/10.1109/TEST.1991.519782","url":null,"abstract":"Practices for software testing vary greatly. In most companies, software testing is performed by the developers who test informally aspart of their debugging activity. Some companies have formal test requirements. In such cases, dedicated software testing tools are often used, and testing is a separate activity performed near the end of the software development cycle. A few companies have a formally defined sofiware development process which utilizes testing and metrics throughout the development process. All companies recognize the need to improve software quality and are seeking additional tools and processes to assist them.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519753
L. Whetsel
This paper describes an IEEE 1149.1 based test IC that emulates the functions of logic and signature analysis test instruments. These ICs can be used at the board or multi-chip module level t o provide an embedded method of monitoring circuits at-speed. This a er assumes the reader has a basic understanding o t t f e IEEE 1149.1 ~ t a n d a r d c ~ , ~ ~ . INTRODUCTION Test instruments, such as logic analyzers, have traditionally been used t o test the at-speed interaction of functioning ICs on board designs. These tes t instruments gain access t o the circuit under test by physically contacting the circuit using a probing mechanism. The use of these test instruments t o test functioning circuitry can reveal timing sensitive and/or intermittent failures that would otherwise not be detectable in a nonfunctional test environment. The abilit of these test instruments t o s nchronize up with and o%serve the at-speed operation o f electronic circuits, have made them an invaluable asset in a wide range of testing applications. With the increasing use of high-speed, state-of-the-art integrated circuits in combination with the miniaturized substrates on which they are assembled, the physical access between an external test instrument and a circuit under test is being severely reduced and in some cases com letely eliminated. New test approaches such as the IEEE 1149.1 boundary scan standard provide a method t o regain electrical access t o miniaturized circuits and substrates through the use of an IC resident test ort and boundary scan architecture. The 1149.1 stanfard provides an excellent method of testing the structural integrity of the wiring interconnects between ICs on a common substrate 3,41. In addition, 1149.1 can be used to test individual Ids while they are in a nonfunctional mode. However, the 1149.1 standard cannot be used effectively for at-speed functional testing of ICs or circuits. The standard does provide a test instruction, referred t o as SamplePreload, that allows the boundary scan register t o take a snapshot sample of the data entering and leaving a functioning IC. While a s ecific application of the SampleRreload instruction has teen describedlg, its general use suffers due to problems not addressed in the standard[,]. One problem with the SamplefPreload instruction is that there is no prescribed method of synchronizing the sample operation with the operation of the host IC. Sampling data asynchronously is a hi t and miss proposition that serves no useful purpose. Another problem is that there is no prescribed method of ualifying when t o execute the sample operation in a P unctioning system. Sampling data synchronously but at random does little t o support testing. The solutions t o these potentially challenging problems is left up to the user of 1149.1. A new a proach, therefore, is required to provide a method o!functionally testing the at-speed operation of miniaturized electronic circuits. The approach described in this paper
{"title":"AN IEEE 1149.1 BASED LOGIC/SIGNATURE ANALYZER IN A CHIP","authors":"L. Whetsel","doi":"10.1109/TEST.1991.519753","DOIUrl":"https://doi.org/10.1109/TEST.1991.519753","url":null,"abstract":"This paper describes an IEEE 1149.1 based test IC that emulates the functions of logic and signature analysis test instruments. These ICs can be used at the board or multi-chip module level t o provide an embedded method of monitoring circuits at-speed. This a er assumes the reader has a basic understanding o t t f e IEEE 1149.1 ~ t a n d a r d c ~ , ~ ~ . INTRODUCTION Test instruments, such as logic analyzers, have traditionally been used t o test the at-speed interaction of functioning ICs on board designs. These tes t instruments gain access t o the circuit under test by physically contacting the circuit using a probing mechanism. The use of these test instruments t o test functioning circuitry can reveal timing sensitive and/or intermittent failures that would otherwise not be detectable in a nonfunctional test environment. The abilit of these test instruments t o s nchronize up with and o%serve the at-speed operation o f electronic circuits, have made them an invaluable asset in a wide range of testing applications. With the increasing use of high-speed, state-of-the-art integrated circuits in combination with the miniaturized substrates on which they are assembled, the physical access between an external test instrument and a circuit under test is being severely reduced and in some cases com letely eliminated. New test approaches such as the IEEE 1149.1 boundary scan standard provide a method t o regain electrical access t o miniaturized circuits and substrates through the use of an IC resident test ort and boundary scan architecture. The 1149.1 stanfard provides an excellent method of testing the structural integrity of the wiring interconnects between ICs on a common substrate 3,41. In addition, 1149.1 can be used to test individual Ids while they are in a nonfunctional mode. However, the 1149.1 standard cannot be used effectively for at-speed functional testing of ICs or circuits. The standard does provide a test instruction, referred t o as SamplePreload, that allows the boundary scan register t o take a snapshot sample of the data entering and leaving a functioning IC. While a s ecific application of the SampleRreload instruction has teen describedlg, its general use suffers due to problems not addressed in the standard[,]. One problem with the SamplefPreload instruction is that there is no prescribed method of synchronizing the sample operation with the operation of the host IC. Sampling data asynchronously is a hi t and miss proposition that serves no useful purpose. Another problem is that there is no prescribed method of ualifying when t o execute the sample operation in a P unctioning system. Sampling data synchronously but at random does little t o support testing. The solutions t o these potentially challenging problems is left up to the user of 1149.1. A new a proach, therefore, is required to provide a method o!functionally testing the at-speed operation of miniaturized electronic circuits. The approach described in this paper","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114184535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519752
Dick Chiles, J. DeJaco
Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller
{"title":"USING BOUNDARY SCAN DESCRIPTION LANGUAGE IN DESIGN","authors":"Dick Chiles, J. DeJaco","doi":"10.1109/TEST.1991.519752","DOIUrl":"https://doi.org/10.1109/TEST.1991.519752","url":null,"abstract":"Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116583211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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