Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822316
Wael Badawy, Guoqing Zhang, M. Bayoumi
Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows a novel VLSI architecture for generating content-based video object representation. The architecture uses a novel technique, borrowed from the 3D modeling, to optimize the mesh coding. The architecture generates the mesh nodes location as well as the associated motion vectors. The performance results show that the prototype contributes practical delay, and it can be used in online application and the power consumption shows that it is good enough in mobile application. Moreover, the number of bits used for the coding shows that the architecture is suitable for very low bit rate applications since it reuses the motion vector values.
{"title":"VLSI architecture for hierarchical mesh-based motion estimation","authors":"Wael Badawy, Guoqing Zhang, M. Bayoumi","doi":"10.1109/SIPS.1999.822316","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822316","url":null,"abstract":"Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows a novel VLSI architecture for generating content-based video object representation. The architecture uses a novel technique, borrowed from the 3D modeling, to optimize the mesh coding. The architecture generates the mesh nodes location as well as the associated motion vectors. The performance results show that the prototype contributes practical delay, and it can be used in online application and the power consumption shows that it is good enough in mobile application. Moreover, the number of bits used for the coding shows that the architecture is suitable for very low bit rate applications since it reuses the motion vector values.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116989851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822350
B. Bishop, T. Kelliher, M. J. Irwin
In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. MediaBench performance characteristics were examined by running MediaBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch prediction accuracy, cache hit rates, memory usage, and integer bit utilization were considered. This information can be of use in designing embedded systems targeted at multimedia applications.
{"title":"A detailed analysis of MediaBench","authors":"B. Bishop, T. Kelliher, M. J. Irwin","doi":"10.1109/SIPS.1999.822350","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822350","url":null,"abstract":"In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. MediaBench performance characteristics were examined by running MediaBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch prediction accuracy, cache hit rates, memory usage, and integer bit utilization were considered. This information can be of use in designing embedded systems targeted at multimedia applications.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822378
Y. Lai, Chi-Chou Kao, Haowei Chen
Adaptive filtering techniques are widely used in the fields of signal processing and communication such as echo/noise cancellation and speech/image coding. Adaptive filters usually need real time ability to process signal. This paper presents a high speed and flexible VLSI architecture. This filter is the digital adaptive finite impulse response (FIR) filter based on the delayed error least mean square (DELMS) algorithm. The architecture has hardware utilization efficiency (HUE) of 100%, and we can easily scale the filter without reducing the throughput rate. The timing simulation results demonstrate the effectiveness of the architecture. We have used 0.6 /spl mu/m CMOS SPTM standard cells technology to implement the chip.
{"title":"Design and implementation of an adaptive FIR filter based on delayed error LMS algorithm","authors":"Y. Lai, Chi-Chou Kao, Haowei Chen","doi":"10.1109/SIPS.1999.822378","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822378","url":null,"abstract":"Adaptive filtering techniques are widely used in the fields of signal processing and communication such as echo/noise cancellation and speech/image coding. Adaptive filters usually need real time ability to process signal. This paper presents a high speed and flexible VLSI architecture. This filter is the digital adaptive finite impulse response (FIR) filter based on the delayed error least mean square (DELMS) algorithm. The architecture has hardware utilization efficiency (HUE) of 100%, and we can easily scale the filter without reducing the throughput rate. The timing simulation results demonstrate the effectiveness of the architecture. We have used 0.6 /spl mu/m CMOS SPTM standard cells technology to implement the chip.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114522187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822351
C. Yeh, C.-C. Jay Kuo
Watermark is an important protection and identification technique that allows invisible mark to be hidden in the multimedia information such as audio, image, video, or tent and has been developed to protect digital signal against illegal reproduction and modifications. In this paper, we propose a novel method about how to embed a digital signature. This method is based on bit plane manipulation of the LSB and the decoding is easy due to the property of the signature (quasi m-array) that we used. The proposed technique for digital watermarking is also compatible with JPEG processing and can be survived after JPEG encoding.
{"title":"Digital watermarking through quasi m-arrays","authors":"C. Yeh, C.-C. Jay Kuo","doi":"10.1109/SIPS.1999.822351","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822351","url":null,"abstract":"Watermark is an important protection and identification technique that allows invisible mark to be hidden in the multimedia information such as audio, image, video, or tent and has been developed to protect digital signal against illegal reproduction and modifications. In this paper, we propose a novel method about how to embed a digital signature. This method is based on bit plane manipulation of the LSB and the decoding is easy due to the property of the signature (quasi m-array) that we used. The proposed technique for digital watermarking is also compatible with JPEG processing and can be survived after JPEG encoding.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114545648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822379
M. Vesterbacka
We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 /spl mu/m process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.
{"title":"A 14-transistor CMOS full adder with full voltage-swing nodes","authors":"M. Vesterbacka","doi":"10.1109/SIPS.1999.822379","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822379","url":null,"abstract":"We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 /spl mu/m process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122145149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822335
Mao-Hsu Yen, Sao-Jie Chen, S. Lan
To accelerate prototyping designs, we propose a new Symmetric and Programmable MCM (SPMCM) substrate, which consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Especially, the FPIC that we developed contains two kinds of polygonal routing modules and some virtual-wires to reduce the number of routing switches and pin count. For a bare-chip slot with 2n pads, the number of switches used in the polygonal routing module is less than the conventional routing module by /spl radic/(rF/sub C/n)/4 times, where the flexibility ratio r(F/sub C/) is close to 1.
{"title":"Symmetric and programmable multi-chip module for rapid prototyping system","authors":"Mao-Hsu Yen, Sao-Jie Chen, S. Lan","doi":"10.1109/SIPS.1999.822335","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822335","url":null,"abstract":"To accelerate prototyping designs, we propose a new Symmetric and Programmable MCM (SPMCM) substrate, which consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Especially, the FPIC that we developed contains two kinds of polygonal routing modules and some virtual-wires to reduce the number of routing switches and pin count. For a bare-chip slot with 2n pads, the number of switches used in the polygonal routing module is less than the conventional routing module by /spl radic/(rF/sub C/n)/4 times, where the flexibility ratio r(F/sub C/) is close to 1.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"635 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822302
T. Nishitani
Issues of system-on-a-chip are reviewed and the reduction of the initial cost, mainly occupied by chip reworks, is shown to be the most important issue. In order to reduce chip reworks, SOC design methodologies based on applications can be segregated into three classes. One of three classes is to employ a programmable approach. The expansion of this class highly depends on the introduction of powerful programmable cores. Our dynamically reconfigurable logic engine (DRLE), which utilizes a FPGA approach with dynamically re-configurable functions, seems to be a promising way.
{"title":"An approach to a multimedia system on a chip","authors":"T. Nishitani","doi":"10.1109/SIPS.1999.822302","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822302","url":null,"abstract":"Issues of system-on-a-chip are reviewed and the reduction of the initial cost, mainly occupied by chip reworks, is shown to be the most important issue. In order to reduce chip reworks, SOC design methodologies based on applications can be segregated into three classes. One of three classes is to employ a programmable approach. The expansion of this class highly depends on the introduction of powerful programmable cores. Our dynamically reconfigurable logic engine (DRLE), which utilizes a FPGA approach with dynamically re-configurable functions, seems to be a promising way.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114976536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822366
Chin-Liang, Kuo-Ming Wu, Chunhui Ou
In this paper, a new nonlinear approach for narrowband interference (NBI) suppression in code-division multiple-access (CDMA) systems is proposed. The developed scheme is an adaptive nonlinear predictor that consists of an (N+1)-level quantizer, an adaptive linear filter, and three adders, where N is the number of users in the CDMA system. It could be regarded as an enhancement to the nonlinear offset predictor presented by (Wang et al., 1997) with a more appropriate offset compensation scheme being derived and employed here. Computer simulation results support that this modified offset predictor performs much better than the original one with only a slight increase in complexity. As compared to the nearly optimal approximate conditional mean filter, it achieves almost the same performance even at very low signal-to-noise ratio, but involves much less complexity.
本文提出了一种新的抑制码分多址(CDMA)系统中窄带干扰的非线性方法。所开发的方案是一个自适应非线性预测器，由一个(N+1)级量化器、一个自适应线性滤波器和三个加法器组成，其中N为CDMA系统中的用户数。它可以看作是对(Wang et al.， 1997)提出的非线性偏移预测器的增强，这里推导并采用了更合适的偏移补偿方案。计算机仿真结果表明，改进后的偏移量预测器的性能比原来的预测器要好得多，而且复杂度略有增加。与接近最优的近似条件平均滤波器相比，即使在非常低的信噪比下，它也能达到几乎相同的性能，但涉及的复杂性要小得多。
{"title":"A nonlinear narrowband interference suppression technique for spread-spectrum CDMA communications","authors":"Chin-Liang, Kuo-Ming Wu, Chunhui Ou","doi":"10.1109/SIPS.1999.822366","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822366","url":null,"abstract":"In this paper, a new nonlinear approach for narrowband interference (NBI) suppression in code-division multiple-access (CDMA) systems is proposed. The developed scheme is an adaptive nonlinear predictor that consists of an (N+1)-level quantizer, an adaptive linear filter, and three adders, where N is the number of users in the CDMA system. It could be regarded as an enhancement to the nonlinear offset predictor presented by (Wang et al., 1997) with a more appropriate offset compensation scheme being derived and employed here. Computer simulation results support that this modified offset predictor performs much better than the original one with only a slight increase in complexity. As compared to the nearly optimal approximate conditional mean filter, it achieves almost the same performance even at very low signal-to-noise ratio, but involves much less complexity.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822339
Chanik Park, Jaewoong Chung, S. Ha
We present an efficient dataflow representation of MPEG-1 Audio (Layer III) Decoder (MP3) algorithm with controlled global states. Although dataflow graph has been a successful representation language for DSP applications, lack of global states makes it unsuitable to some applications that require periodic parameter update and dynamic behavior of function blocks. We show the global states can solve these problems and be fused into dataflow graph without any side effect. With a real-life example such as MP3 decoder, we present the novelty and usefulness of our approach.
{"title":"Efficient dataflow representation of MPEG-1 audio (layer III) decoder algorithm with controlled global states","authors":"Chanik Park, Jaewoong Chung, S. Ha","doi":"10.1109/SIPS.1999.822339","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822339","url":null,"abstract":"We present an efficient dataflow representation of MPEG-1 Audio (Layer III) Decoder (MP3) algorithm with controlled global states. Although dataflow graph has been a successful representation language for DSP applications, lack of global states makes it unsuitable to some applications that require periodic parameter update and dynamic behavior of function blocks. We show the global states can solve these problems and be fused into dataflow graph without any side effect. With a real-life example such as MP3 decoder, we present the novelty and usefulness of our approach.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822373
Pak-Cheung Lai, B. Zeng
Threshold Boolean filters (TBFs) constitute a large class of nonlinear filters which are effective in removing impulsive noise and preserving image details. The minimum mean square error (MMSE) design of TBFs is found to be a quadratic 0-1 programming problem. Unfortunately, solving the problem needs a huge number of computations. We propose an iterative search algorithm of very low complexity to solve the design problem sub-optimally. In each iteration, only one variable is considered and updated. Simulation shows that the proposed algorithm converges quickly and often converges to the optimal solution.
{"title":"Design of threshold Boolean filters under MSE criterion by iterative searching","authors":"Pak-Cheung Lai, B. Zeng","doi":"10.1109/SIPS.1999.822373","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822373","url":null,"abstract":"Threshold Boolean filters (TBFs) constitute a large class of nonlinear filters which are effective in removing impulsive noise and preserving image details. The minimum mean square error (MMSE) design of TBFs is found to be a quadratic 0-1 programming problem. Unfortunately, solving the problem needs a huge number of computations. We propose an iterative search algorithm of very low complexity to solve the design problem sub-optimally. In each iteration, only one variable is considered and updated. Simulation shows that the proposed algorithm converges quickly and often converges to the optimal solution.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124396356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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