Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822349
P. Chung, Chuan-Yu Chang, W. Chu, Hsiu-Chen Liu
In this paper, we propose a technique that reconstructs two sets of medical images acquired with different acquisition angles and anatomical cross sections into one set of images of identical scanning orientation and positions. The space correlation information among the two image stacks is first extracted and is used to correct the tilt angle and anatomical position differences found in the image stacks. Satisfactory reconstruction results were presented to prove our points.
{"title":"Medical image reconstruction from different acquisition angles","authors":"P. Chung, Chuan-Yu Chang, W. Chu, Hsiu-Chen Liu","doi":"10.1109/SIPS.1999.822349","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822349","url":null,"abstract":"In this paper, we propose a technique that reconstructs two sets of medical images acquired with different acquisition angles and anatomical cross sections into one set of images of identical scanning orientation and positions. The space correlation information among the two image stacks is first extracted and is used to correct the tilt angle and anatomical position differences found in the image stacks. Satisfactory reconstruction results were presented to prove our points.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134329815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822382
Sau-Gee Chen, R. Jiang
This paper proposes a new type of time-domain direct-form fast filtering algorithm, which composes a sum of N/2 product-of-sum terms. The sum consists of the desired current output point, as well as the half partial results of the preceding and succeeding output points. After further algebraic manipulation, the required complexity per output point is 3N/4 multiplications and 3N/4+1/2 additions. This is about 25% reduction over the direct computation. The design technique can be extended to linear-phase filtering. In this case, the new algorithm only needs 3N/8+2 multiplications and N+10 additions, which is about 25% improvement over N/2 of the direct-form computation in multiplication complexity. The new algorithm can be also iteratively applied to a convolution operation for more complexity reduction. Since the new algorithm is also a direct-form type, its realization is regular and very suitable for ASIC design.
{"title":"A new fast filtering algorithm based on algebraic composition","authors":"Sau-Gee Chen, R. Jiang","doi":"10.1109/SIPS.1999.822382","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822382","url":null,"abstract":"This paper proposes a new type of time-domain direct-form fast filtering algorithm, which composes a sum of N/2 product-of-sum terms. The sum consists of the desired current output point, as well as the half partial results of the preceding and succeeding output points. After further algebraic manipulation, the required complexity per output point is 3N/4 multiplications and 3N/4+1/2 additions. This is about 25% reduction over the direct computation. The design technique can be extended to linear-phase filtering. In this case, the new algorithm only needs 3N/8+2 multiplications and N+10 additions, which is about 25% improvement over N/2 of the direct-form computation in multiplication complexity. The new algorithm can be also iteratively applied to a convolution operation for more complexity reduction. Since the new algorithm is also a direct-form type, its realization is regular and very suitable for ASIC design.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130173340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822372
Weidong Li, L. Wanhammar
We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 /spl mu/m CMOS process, is efficient in terms of power consumption and chip area.
{"title":"A pipeline FFT processor","authors":"Weidong Li, L. Wanhammar","doi":"10.1109/SIPS.1999.822372","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822372","url":null,"abstract":"We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 /spl mu/m CMOS process, is efficient in terms of power consumption and chip area.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116446540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822329
J. Wittenburg, P. Pirsch, G. Meyer
Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-professors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.
{"title":"A multithreaded architecture approach to parallel DSPs for high performance image processing applications","authors":"J. Wittenburg, P. Pirsch, G. Meyer","doi":"10.1109/SIPS.1999.822329","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822329","url":null,"abstract":"Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-professors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133857949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822359
T. Kanazawa, A. Sugiura
Various methods are proposed for the practical use of ITS. We achieve the detection of emergency vehicles such as ambulances and fire engines by measurement which uses a spread-spectrum method. We propose a method in which another vehicle and the signal can detect the position of emergency vehicles. This method transmits different code spread-spectrum signals from the four corners of emergency vehicles. As a result, because the direction from which an emergency vehicle approaches is understood, evasive driving becomes easy for securing the traffic road, and signal control also becomes easy. As a result of experiment an excellent detection result was obtained.
{"title":"Direction detector system of an emergency vehicle for ITS by using code division multiple access","authors":"T. Kanazawa, A. Sugiura","doi":"10.1109/SIPS.1999.822359","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822359","url":null,"abstract":"Various methods are proposed for the practical use of ITS. We achieve the detection of emergency vehicles such as ambulances and fire engines by measurement which uses a spread-spectrum method. We propose a method in which another vehicle and the signal can detect the position of emergency vehicles. This method transmits different code spread-spectrum signals from the four corners of emergency vehicles. As a result, because the direction from which an emergency vehicle approaches is understood, evasive driving becomes easy for securing the traffic road, and signal control also becomes easy. As a result of experiment an excellent detection result was obtained.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822330
J. Fridman
Data alignment and code size expansion are two problems of sub-word parallel (SWP) computation. In this paper we propose a new solution to data alignment in a recently introduced SWP-extended digital signal processor, and present details of an application example. This data alignment technique offers a reduction in overhead compared to other solutions in the literature, in that it does not require aggressive loop unrolling and can be tightly scheduled in software.
{"title":"Data alignment for sub-word parallelism in DSP","authors":"J. Fridman","doi":"10.1109/SIPS.1999.822330","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822330","url":null,"abstract":"Data alignment and code size expansion are two problems of sub-word parallel (SWP) computation. In this paper we propose a new solution to data alignment in a recently introduced SWP-extended digital signal processor, and present details of an application example. This data alignment technique offers a reduction in overhead compared to other solutions in the literature, in that it does not require aggressive loop unrolling and can be tightly scheduled in software.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126091463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822380
K.S. Shim, Ik Kyun Oh, Sangjin Hong, Beom-Seon Ryu, K. Lee, Taewon Cho
A low power 8/spl times/8+20-bit MAC is designed minimizing the power consumption at each of the design levels. At algorithm level, a new method for MR-XY operation which saves 40% of transistor counts over conventional methods is proposed. A new Booth selector circuit using NMOS PTL (pass-transistor logic) which has excellent power-delay product is also proposed at transistor level. Dynamic CMOS single edge triggered flip-flops are used to reduce the number of transistors for the registers. The proposed MAC is designed with 0.6 um single-poly triple-metal CMOS process. As a result of simulation, operating frequency is over 100 MHz with 3.3 V supply voltage and the average power consumption is 51 mW at 100 MHz.
{"title":"A multi-level approach to low power MAC design","authors":"K.S. Shim, Ik Kyun Oh, Sangjin Hong, Beom-Seon Ryu, K. Lee, Taewon Cho","doi":"10.1109/SIPS.1999.822380","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822380","url":null,"abstract":"A low power 8/spl times/8+20-bit MAC is designed minimizing the power consumption at each of the design levels. At algorithm level, a new method for MR-XY operation which saves 40% of transistor counts over conventional methods is proposed. A new Booth selector circuit using NMOS PTL (pass-transistor logic) which has excellent power-delay product is also proposed at transistor level. Dynamic CMOS single edge triggered flip-flops are used to reduce the number of transistors for the registers. The proposed MAC is designed with 0.6 um single-poly triple-metal CMOS process. As a result of simulation, operating frequency is over 100 MHz with 3.3 V supply voltage and the average power consumption is 51 mW at 100 MHz.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126160616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications. Moreover, densely encoded instructions supporting memory operands, DSP-like addressing modes, and SIMD capability boost the performance while keeping the code size and hardware cost small. To maximally utilize this architecture, a software environment including a code converter, a VLIW compiler system, and a compiled simulator has also been developed. The processor core has been synthesized for LSI logic 0.25 /spl mu/m library, which results in the total gate count of 102 K. In spite of the relatively smaller issue rate, the proposed processor shows a comparable or higher performance in terms of both the cycle count and the code size when compared to the 8-issue TMS320C62xx, for DSP benchmark kernels and an H.263 video encoder.
{"title":"A 2 way VLIW processor architecture for embedded multimedia applications","authors":"Jiyang Kang, Jae-Woo Ahn, Jiyoung Cho, Ki-Il Kum, Wonyong Sung","doi":"10.1109/SIPS.1999.822326","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822326","url":null,"abstract":"As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications. Moreover, densely encoded instructions supporting memory operands, DSP-like addressing modes, and SIMD capability boost the performance while keeping the code size and hardware cost small. To maximally utilize this architecture, a software environment including a code converter, a VLIW compiler system, and a compiled simulator has also been developed. The processor core has been synthesized for LSI logic 0.25 /spl mu/m library, which results in the total gate count of 102 K. In spite of the relatively smaller issue rate, the proposed processor shows a comparable or higher performance in terms of both the cycle count and the code size when compared to the 8-issue TMS320C62xx, for DSP benchmark kernels and an H.263 video encoder.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130188524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822343
S.J. Kim, Jong-Seog Koh
In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.
{"title":"An implementation of MPEG-2 transport stream multiplexer","authors":"S.J. Kim, Jong-Seog Koh","doi":"10.1109/SIPS.1999.822343","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822343","url":null,"abstract":"In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822376
Chang-Tsun Li, D. Lou
In this paper, an edge detection technique is proposed by using the multiresolution Fourier transform (MFT) to analyze the local properties in the spatial frequency domain. Five major steps are adopted to implement the detection of edges. First, the Laplacian pyramid method is used to create a high-pass filtered image. Secondly, the Multiresolution Fourier Transform (MFT) is applied to divide the high-pass filtered image into blocks and transform each of the blocks into spatial frequency domain. Thirdly, single-feature and non-single-feature blocks are differentiated. Subsequently, the blocks containing single feature are then subject to a process for estimating the orientation and the centroid of the feature in order to locate it. Finally, the accuracy of the estimated centroid of the local feature is checked. Once all the blocks are analyzed at a resolution level, the overall procedure is repeated at the next resolution level and the blocks with their father block being classified as non-single-feature or being rejected in the accuracy check stage at the previous level are analyzed. The algorithm stops when a specific level is reached.
{"title":"Edge detection based on the multiresolution Fourier transform","authors":"Chang-Tsun Li, D. Lou","doi":"10.1109/SIPS.1999.822376","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822376","url":null,"abstract":"In this paper, an edge detection technique is proposed by using the multiresolution Fourier transform (MFT) to analyze the local properties in the spatial frequency domain. Five major steps are adopted to implement the detection of edges. First, the Laplacian pyramid method is used to create a high-pass filtered image. Secondly, the Multiresolution Fourier Transform (MFT) is applied to divide the high-pass filtered image into blocks and transform each of the blocks into spatial frequency domain. Thirdly, single-feature and non-single-feature blocks are differentiated. Subsequently, the blocks containing single feature are then subject to a process for estimating the orientation and the centroid of the feature in order to locate it. Finally, the accuracy of the estimated centroid of the local feature is checked. Once all the blocks are analyzed at a resolution level, the overall procedure is repeated at the next resolution level and the blocks with their father block being classified as non-single-feature or being rejected in the accuracy check stage at the previous level are analyzed. The algorithm stops when a specific level is reached.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129233313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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