Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822322
Suet-Fei Li, M. Wan, J. Rabaey
In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the system bottleneck. Our code generation process includes the evaluation a set of tradeoffs in system design, software engineering as well as usage of a set of local and global optimization techniques. By doing so we are able to achieve results of significantly lower overhead.
{"title":"Configuration code generation and optimizations for heterogeneous reconfigurable DSPs","authors":"Suet-Fei Li, M. Wan, J. Rabaey","doi":"10.1109/SIPS.1999.822322","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822322","url":null,"abstract":"In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the system bottleneck. Our code generation process includes the evaluation a set of tradeoffs in system design, software engineering as well as usage of a set of local and global optimization techniques. By doing so we are able to achieve results of significantly lower overhead.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133392046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822338
Leu-Shing Lau
B-spline approximation is an efficient tool for shape representation. Recently, the B-spline technique has also been employed for shape coding with regard to MPEG-4. The traditional B-spline method is a least-squared-error (LS) approach which inevitably may bring about certain undesirable peak errors. To alleviate this error, we arrange to incorporate the minimax constraint into the design goal. The resulting method, called peak-error-constrained optimal shape-representation (PECOS), is a balance between the pure LS and pure minimax design. With the aid of the peak-error-constraint, it, is easy to reduce the magnitude of the peak error at a relatively much lower cost of the root-mean-squared (rms) error. For instance, an example of 32% decrease in peak error is easily obtained at the cost of only 3.6% increase of the rms error! Two algorithms are proposed to solve the PECOS problem. Both of them run very fast and basically converge in a very small number of iterations (typically below 5 iterations).
{"title":"Peak-error-constrained optimal shape representation","authors":"Leu-Shing Lau","doi":"10.1109/SIPS.1999.822338","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822338","url":null,"abstract":"B-spline approximation is an efficient tool for shape representation. Recently, the B-spline technique has also been employed for shape coding with regard to MPEG-4. The traditional B-spline method is a least-squared-error (LS) approach which inevitably may bring about certain undesirable peak errors. To alleviate this error, we arrange to incorporate the minimax constraint into the design goal. The resulting method, called peak-error-constrained optimal shape-representation (PECOS), is a balance between the pure LS and pure minimax design. With the aid of the peak-error-constraint, it, is easy to reduce the magnitude of the peak error at a relatively much lower cost of the root-mean-squared (rms) error. For instance, an example of 32% decrease in peak error is easily obtained at the cost of only 3.6% increase of the rms error! Two algorithms are proposed to solve the PECOS problem. Both of them run very fast and basically converge in a very small number of iterations (typically below 5 iterations).","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114467230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822363
Yeong-Kang Lai, Yu-Chuan Shu
A novel one-round VLSI architecture of the block cipher, Blowfish, for data encryption/decryption has been presented. Based on a pipelined structure, efficient key management, and the mapping of the algorithm onto the data path the performance of the architecture can be increased. In addition, all important standardised modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption such as wireless communication application.
{"title":"A novel VLSI architecture for a variable-length key, 64-bit Blowfish block cipher","authors":"Yeong-Kang Lai, Yu-Chuan Shu","doi":"10.1109/SIPS.1999.822363","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822363","url":null,"abstract":"A novel one-round VLSI architecture of the block cipher, Blowfish, for data encryption/decryption has been presented. Based on a pipelined structure, efficient key management, and the mapping of the algorithm onto the data path the performance of the architecture can be increased. In addition, all important standardised modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption such as wireless communication application.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130261404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822360
Dake Liu, U. Nordqvist, Christer Svensson
A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications.
{"title":"Configuration-based architecture for high speed and general-purpose protocol processing","authors":"Dake Liu, U. Nordqvist, Christer Svensson","doi":"10.1109/SIPS.1999.822360","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822360","url":null,"abstract":"A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822375
Cheong Ngai, R. Martins
This paper proposes a computer-automated synthesis of SC decimators with a high decimating factor based on the statistical approach of the program (ISCMRATE). This methodology is implemented based on multi-decimation building blocks, such as externally cascaded, internally cascaded or ladder structures and polyphase input networks. The design criteria are given to obtain and evaluate the performance of the corresponding resulting circuits. A design example of a 7/sup th/ order SC lowpass elliptic decimator with M=10 is given to illustrate the above proposed methodology.
{"title":"Synthesis and design of a 7/sup th/ order SC lowpass decimator combining externally cascaded and ladder structures","authors":"Cheong Ngai, R. Martins","doi":"10.1109/SIPS.1999.822375","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822375","url":null,"abstract":"This paper proposes a computer-automated synthesis of SC decimators with a high decimating factor based on the statistical approach of the program (ISCMRATE). This methodology is implemented based on multi-decimation building blocks, such as externally cascaded, internally cascaded or ladder structures and polyphase input networks. The design criteria are given to obtain and evaluate the performance of the corresponding resulting circuits. A design example of a 7/sup th/ order SC lowpass elliptic decimator with M=10 is given to illustrate the above proposed methodology.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128315662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822325
H. Thomas, J. Diguet, J. Philippe
This paper comes within the framework in the application-architecture matching. The proposed methodology covers the upper part of the codesign flow which is located before the partitioning step. The issue is to provide the designer and to the partitioning step with useful information in order to design an ad hoc architecture. Also, the estimations are computed without knowledge of the implementation. The optimisation potential existing between the function are taking into account to obtain a global and dynamic cost of the application.
{"title":"A methodology for an application profiling at system level","authors":"H. Thomas, J. Diguet, J. Philippe","doi":"10.1109/SIPS.1999.822325","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822325","url":null,"abstract":"This paper comes within the framework in the application-architecture matching. The proposed methodology covers the upper part of the codesign flow which is located before the partitioning step. The issue is to provide the designer and to the partitioning step with useful information in order to design an ad hoc architecture. Also, the estimations are computed without knowledge of the implementation. The optimisation potential existing between the function are taking into account to obtain a global and dynamic cost of the application.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"2017 47","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113966439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822324
M. Wan, Hui Zhang, M. Benes, J. Rabaey
Reconfigurable architectures have emerged as a promising implementation platform to provide high-flexibility, high-performance, and low-power solutions for future wireless embedded devices. We discuss in details a reconfigurable data-flow driven architecture, including the computation model, communication mechanism, and implementation. We also describe a set of software tools developed to perform automatic mapping from algorithms to the architecture, as well as to evaluate the resulting performance and energy of the mapping. Finally, we present results on digital signal processing and wireless communication algorithms to show the energy efficiency of the system and the effectiveness of the tools. Our system shows more than one order of magnitude of improvement in terms of energy efficiency when compared to low-power programmable processors.
{"title":"A low-power reconfigurable data-flow driven DSP system","authors":"M. Wan, Hui Zhang, M. Benes, J. Rabaey","doi":"10.1109/SIPS.1999.822324","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822324","url":null,"abstract":"Reconfigurable architectures have emerged as a promising implementation platform to provide high-flexibility, high-performance, and low-power solutions for future wireless embedded devices. We discuss in details a reconfigurable data-flow driven architecture, including the computation model, communication mechanism, and implementation. We also describe a set of software tools developed to perform automatic mapping from algorithms to the architecture, as well as to evaluate the resulting performance and energy of the mapping. Finally, we present results on digital signal processing and wireless communication algorithms to show the energy efficiency of the system and the effectiveness of the tools. Our system shows more than one order of magnitude of improvement in terms of energy efficiency when compared to low-power programmable processors.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127884918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822311
Wael Badawy, Guoqing Zhang, M. Talley, M. Weeks, M. Bayoumi
This paper presents a low power 3-D discrete wavelet transform processor for medical applications. The main target of this work is the compression of Magnetic Resonance Imaging (MRI) data using a wavelet based scheme. A prototype has been developed to realize a 3-D wavelet compressor. The processor is based on an architecture that uses a centrally controlled unit to coordinate sub-systems which carry out the operations necessary for the data compression. The subsystems include a small cache memory used for block data storage, parallel high and low pass filters used for data calculation, and two coefficient units used to retrieve off-chip wavelet coefficients. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization has been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipating 0.5 W of power.
提出了一种低功耗的医用三维离散小波变换处理器。这项工作的主要目标是使用基于小波的方案压缩磁共振成像(MRI)数据。研制了实现三维小波压缩器的样机。处理器基于一种体系结构，该体系结构使用中央控制单元来协调执行数据压缩所需操作的子系统。子系统包括用于块数据存储的小型缓存存储器，用于数据计算的并行高通和低通滤波器，以及用于检索片外小波系数的两个系数单元。该处理器已采用0.6 /spl μ m CMOS(三金属)技术进行原型化，原型处理器是模块化的。它已经在功能，电路和物理层面上进行了模拟。对样机、面积、时延、功耗、利用率等性能指标进行了评价。原型机的工作频率估计为272兆赫，功耗为0.5瓦。
{"title":"A low power 3-D discrete wavelet transform processor for medical applications","authors":"Wael Badawy, Guoqing Zhang, M. Talley, M. Weeks, M. Bayoumi","doi":"10.1109/SIPS.1999.822311","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822311","url":null,"abstract":"This paper presents a low power 3-D discrete wavelet transform processor for medical applications. The main target of this work is the compression of Magnetic Resonance Imaging (MRI) data using a wavelet based scheme. A prototype has been developed to realize a 3-D wavelet compressor. The processor is based on an architecture that uses a centrally controlled unit to coordinate sub-systems which carry out the operations necessary for the data compression. The subsystems include a small cache memory used for block data storage, parallel high and low pass filters used for data calculation, and two coefficient units used to retrieve off-chip wavelet coefficients. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization has been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipating 0.5 W of power.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127425228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822368
W.N. Chen, T. Moir
A new active word boundary detection algorithm for speech is investigated in this paper. In this algorithm three microphones are used to detect the desired and undesired periods of speech by defining a geometrical 'active zone'. With three microphones this word boundary detector can retrieve the desired speech embedded with noise from varieties of noisy background. Some simulation experiments are conducted in this paper to show that the algorithm is an effective speech detecting method that exceeds an average 80% success rate.
{"title":"Active word boundary detection using three microphones","authors":"W.N. Chen, T. Moir","doi":"10.1109/SIPS.1999.822368","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822368","url":null,"abstract":"A new active word boundary detection algorithm for speech is investigated in this paper. In this algorithm three microphones are used to detect the desired and undesired periods of speech by defining a geometrical 'active zone'. With three microphones this word boundary detector can retrieve the desired speech embedded with noise from varieties of noisy background. Some simulation experiments are conducted in this paper to show that the algorithm is an effective speech detecting method that exceeds an average 80% success rate.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822318
L. Ang, H. Cheung, K. Eshraghian
In this paper, we present a hardware architecture for very high resolution (VHR) scalable video coding using the virtual zerotree (VZT) algorithm, a variant of the embedded zerotree wavelet (EZW) algorithm. The VZT architecture is regular and modular and is suitable for VLSI implementation. The output of the architecture is a data stream containing the virtual map, significance map and successive-approximation quantization symbols of the VZT algorithm. The approach is based on an efficient scheme to determine ancestor-descendant relationships in the wavelet coefficient data stream by rearrangement of the data stream for simpler VLSI implementation. The approach uses the sign-magnitude binary representation of the rearranged wavelet coefficients to form a single bit data stream as the input into the architecture. The coding and quantization for the VZT algorithm are formulated in view of the single bit data stream input and the corresponding VLSI architecture to implement the formulated requirements is presented.
{"title":"VLSI architecture for very high resolution scalable video coding using the virtual zerotree","authors":"L. Ang, H. Cheung, K. Eshraghian","doi":"10.1109/SIPS.1999.822318","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822318","url":null,"abstract":"In this paper, we present a hardware architecture for very high resolution (VHR) scalable video coding using the virtual zerotree (VZT) algorithm, a variant of the embedded zerotree wavelet (EZW) algorithm. The VZT architecture is regular and modular and is suitable for VLSI implementation. The output of the architecture is a data stream containing the virtual map, significance map and successive-approximation quantization symbols of the VZT algorithm. The approach is based on an efficient scheme to determine ancestor-descendant relationships in the wavelet coefficient data stream by rearrangement of the data stream for simpler VLSI implementation. The approach uses the sign-magnitude binary representation of the rearranged wavelet coefficients to form a single bit data stream as the input into the architecture. The coding and quantization for the VZT algorithm are formulated in view of the single bit data stream input and the corresponding VLSI architecture to implement the formulated requirements is presented.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134450981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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