Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822310
Yeu-Horng Shiau, Pei-Yin Chen, J. Jou
In this paper, we propose an efficient gray-based block-matching algorithm (GBMA) and its VLSI architecture. Based on the gray system theory, the GBMA can determine the better motion vectors of image blocks quickly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as TSS, CS, PHODS, FSS, and SES, in terms of four different measures: 1) average MSE per pixel, 2) average PSNR, 3) average prediction errors per pixel, and 4) average search points per frame. The VLSI architecture of the algorithm has been designed and implemented, and it can yield a search rate of 680 K blocks/sec with a clock rate of 66 MHz.
{"title":"A gray-based block-matching algorithm and its VLSI architecture","authors":"Yeu-Horng Shiau, Pei-Yin Chen, J. Jou","doi":"10.1109/SIPS.1999.822310","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822310","url":null,"abstract":"In this paper, we propose an efficient gray-based block-matching algorithm (GBMA) and its VLSI architecture. Based on the gray system theory, the GBMA can determine the better motion vectors of image blocks quickly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as TSS, CS, PHODS, FSS, and SES, in terms of four different measures: 1) average MSE per pixel, 2) average PSNR, 3) average prediction errors per pixel, and 4) average search points per frame. The VLSI architecture of the algorithm has been designed and implemented, and it can yield a search rate of 680 K blocks/sec with a clock rate of 66 MHz.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132744277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822364
Hyunman Chang, M. Sunwoo
We describe an area efficient pipelined Reed-Solomon (RS) decoder. We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid's algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 2/sup 8/, i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates.
{"title":"Design of an area efficient Reed-Solomon decoder ASIC chip","authors":"Hyunman Chang, M. Sunwoo","doi":"10.1109/SIPS.1999.822364","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822364","url":null,"abstract":"We describe an area efficient pipelined Reed-Solomon (RS) decoder. We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid's algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 2/sup 8/, i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124783751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822345
Tae-Hua Lan, A.H. Tewflk, Po-Chin Hu
In this paper we design a novel transcoding algorithm to transcode and compress a JPEG or MPEG bitstream to a fully embedded one. Due to the efficiency of multigrid embedded (MGE) coding used to code non-zero quantized DCT coefficients, it actually compresses JPEG or MPEG bitstreams from 9% to 30%. This "transcompression" method has many applications for the Internet and multimedia networks. Since most "original" images or video files stored on computers around the world are in JPEG or MPEG formats, our algorithm provides a simple and efficient way to redistribute pictures/video files across the Internet.
{"title":"JPEG transcompressor and Internet applications","authors":"Tae-Hua Lan, A.H. Tewflk, Po-Chin Hu","doi":"10.1109/SIPS.1999.822345","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822345","url":null,"abstract":"In this paper we design a novel transcoding algorithm to transcode and compress a JPEG or MPEG bitstream to a fully embedded one. Due to the efficiency of multigrid embedded (MGE) coding used to code non-zero quantized DCT coefficients, it actually compresses JPEG or MPEG bitstreams from 9% to 30%. This \"transcompression\" method has many applications for the Internet and multimedia networks. Since most \"original\" images or video files stored on computers around the world are in JPEG or MPEG formats, our algorithm provides a simple and efficient way to redistribute pictures/video files across the Internet.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124871886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822377
P. Israsena, S. Summerfield
Allpass digital filters are major building blocks in many digital filter architectures. In this paper an optimal pipelined architecture for a 2nd order allpass section based on 3-port adaptor is proposed. Optimal pipelining improves the filter's overall performance in term of power-delay-area by 4.8 times using 1 /spl mu/m CMOS standard cell design and by 10 times using custom cells. Given the same clock speed and without the use of supply voltage scaling, the architecture consumes 58% less power than the non-pipelined equivalent using custom cell implementation and by 50% using standard cells. With a maximum throughput of 277 MHz, the adaptor's power consumption is 5.44 mW/MHz, representing a 64% improvement in power efficiency relative to the non-pipelined standard cell adaptor.
{"title":"Optimal systolic block size for low power high speed digital allpass filters based on the 3-port adaptor","authors":"P. Israsena, S. Summerfield","doi":"10.1109/SIPS.1999.822377","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822377","url":null,"abstract":"Allpass digital filters are major building blocks in many digital filter architectures. In this paper an optimal pipelined architecture for a 2nd order allpass section based on 3-port adaptor is proposed. Optimal pipelining improves the filter's overall performance in term of power-delay-area by 4.8 times using 1 /spl mu/m CMOS standard cell design and by 10 times using custom cells. Given the same clock speed and without the use of supply voltage scaling, the architecture consumes 58% less power than the non-pipelined equivalent using custom cell implementation and by 50% using standard cells. With a maximum throughput of 277 MHz, the adaptor's power consumption is 5.44 mW/MHz, representing a 64% improvement in power efficiency relative to the non-pipelined standard cell adaptor.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123195266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822337
S. Dutta, D. Singh, V. Mehra
This paper describes the architecture, functionality and design of TM-2700-a digital television and media processor chip from Philips Semiconductors. The chip not only supports all eighteen digital television picture formats prescribed by the United States Advanced Television Systems Committee (ATSC), from standard-definition to wide-angle high-definition video, but has also the power to handle High-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2 video, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. TM-2700 is a programmable processor with a very powerful, general-purpose Very Long Instruction Word (VLIW) Central Processing Unit (CPU) core that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. Aided by an array of peripheral devices and high-performance buses, the CPU core facilitates concurrent processing of audio, video, graphics, and communication-data.
{"title":"Architecture and implementation of a single-chip programmable digital television and media processor","authors":"S. Dutta, D. Singh, V. Mehra","doi":"10.1109/SIPS.1999.822337","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822337","url":null,"abstract":"This paper describes the architecture, functionality and design of TM-2700-a digital television and media processor chip from Philips Semiconductors. The chip not only supports all eighteen digital television picture formats prescribed by the United States Advanced Television Systems Committee (ATSC), from standard-definition to wide-angle high-definition video, but has also the power to handle High-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2 video, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. TM-2700 is a programmable processor with a very powerful, general-purpose Very Long Instruction Word (VLIW) Central Processing Unit (CPU) core that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. Aided by an array of peripheral devices and high-performance buses, the CPU core facilitates concurrent processing of audio, video, graphics, and communication-data.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822352
C. Lecordier, O. Ingremeau, E. Martin
We present in this article a method to analyse the intrinsic transient fault tolerance of signal and image processing algorithms for DSP applications. This method allows to protect only non-tolerant parts and consequently to decrease time and memory overheads. Results are given for an algorithm of embedded satellite image compression.
{"title":"Analysis of the intrinsic transient fault tolerance of a signal and image processing algorithm implemented on a DSP","authors":"C. Lecordier, O. Ingremeau, E. Martin","doi":"10.1109/SIPS.1999.822352","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822352","url":null,"abstract":"We present in this article a method to analyse the intrinsic transient fault tolerance of signal and image processing algorithms for DSP applications. This method allows to protect only non-tolerant parts and consequently to decrease time and memory overheads. Results are given for an algorithm of embedded satellite image compression.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"120 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-20DOI: 10.1109/SIPS.1999.822365
Jye-Jong Leu, A. Wu
The Booth-encoded Montgomery modular multiplication algorithm is proposed to reduce the iteration number to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding technique to shorten the critical path. Finally, we propose the 2 bit-digit-serial pipelined architecture to process RSA en/decryption in a more efficient way. By applying the proposed algorithm in RSA design, the hardware complexity can be reduced by 15% compared with most RSA VLSI designs using the Montgomery modular multiplication algorithm.
{"title":"A scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem","authors":"Jye-Jong Leu, A. Wu","doi":"10.1109/SIPS.1999.822365","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822365","url":null,"abstract":"The Booth-encoded Montgomery modular multiplication algorithm is proposed to reduce the iteration number to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding technique to shorten the critical path. Finally, we propose the 2 bit-digit-serial pipelined architecture to process RSA en/decryption in a more efficient way. By applying the proposed algorithm in RSA design, the hardware complexity can be reduced by 15% compared with most RSA VLSI designs using the Montgomery modular multiplication algorithm.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131087910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.1999.822370
E. Brockmeyer, C. Ghez, J. D'Eer, F. Catthoor, H. de Man
FFTs are important modules in embedded telecom systems, many of which require low-power real-time implementations. This paper describes a technique for aggressively localizing data accesses in a (inverse) fast Fourier transformation at the source code level. The global I/O functionality is not modified and neither is the bit-true arithmetic behavior. Typically 20 to 50% of the background memory accesses can be saved. A heavily parametrizable solution is proposed which leads to a family of power optimized algorithm codes. Moreover, efficient coding details for specific instances are shown.
{"title":"Parametrizable behavioral IP module for a data-localized low-power FFT","authors":"E. Brockmeyer, C. Ghez, J. D'Eer, F. Catthoor, H. de Man","doi":"10.1109/SIPS.1999.822370","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822370","url":null,"abstract":"FFTs are important modules in embedded telecom systems, many of which require low-power real-time implementations. This paper describes a technique for aggressively localizing data accesses in a (inverse) fast Fourier transformation at the source code level. The global I/O functionality is not modified and neither is the bit-true arithmetic behavior. Typically 20 to 50% of the background memory accesses can be saved. A heavily parametrizable solution is proposed which leads to a family of power optimized algorithm codes. Moreover, efficient coding details for specific instances are shown.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132230099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.1999.822334
S. Masud, J. McCanny
A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.
{"title":"Rapid VLSI design of biorthogonal wavelet transform cores","authors":"S. Masud, J. McCanny","doi":"10.1109/SIPS.1999.822334","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822334","url":null,"abstract":"A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterised in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125329372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.1999.822331
K. Masselos, F. Catthoor, C. Goutis, H. Deman
The data storage and transfers related power consumption, which forms an important part of the total system power consumption, should be reduced in realizations of multimedia applications on programmable multimedia processors. In earlier work, we have formalized a methodology to achieve this. This methodology is based on the application of a number of power optimizing code transformations to a system-level description of the target application. Our script has recently been extended explicitly to take into consideration the required performance (in number of execution cycles), which is the overriding constraint in real-time multimedia applications. In this paper, we focus on a systematic use methodology that allows to apply this script in practice in a manual way on a complex application, including the necessary local design iterations. Experimental results from a real-life data-dominated application demonstrate that the application of the proposed systematic approach leads to significant power and performance gains compared to reference designs.
{"title":"A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors","authors":"K. Masselos, F. Catthoor, C. Goutis, H. Deman","doi":"10.1109/SIPS.1999.822331","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822331","url":null,"abstract":"The data storage and transfers related power consumption, which forms an important part of the total system power consumption, should be reduced in realizations of multimedia applications on programmable multimedia processors. In earlier work, we have formalized a methodology to achieve this. This methodology is based on the application of a number of power optimizing code transformations to a system-level description of the target application. Our script has recently been extended explicitly to take into consideration the required performance (in number of execution cycles), which is the overriding constraint in real-time multimedia applications. In this paper, we focus on a systematic use methodology that allows to apply this script in practice in a manual way on a complex application, including the necessary local design iterations. Experimental results from a real-life data-dominated application demonstrate that the application of the proposed systematic approach leads to significant power and performance gains compared to reference designs.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"30 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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