Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273165
M. Daraban, D. Pitica
Usually crosstalk problems are resolved by using physical methods like, guard tracing or increasing the distance between adjacent traces, [1]. Even if these methods yield good results, the bus surface is increased on the printed circuit board (PCB). A solution to this problem is to encode the sent information. By using crosstalk avoidance codes (CAC), there can be resolved crosstalk and inter-symbol interference (ISI) problems. CAC are developed by imposing rules regarding which switching pattern can be sent via the parallel data bus. By doing so, there are created forbidden transition channels (FTC). The purpose of the CAC is to enable a high speed transmission on a PCB built by using mainstream technologies without the high speed manufacturing processes.
{"title":"Bus encoding algorithm to reduce crosstalk effects","authors":"M. Daraban, D. Pitica","doi":"10.1109/ISSE.2012.6273165","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273165","url":null,"abstract":"Usually crosstalk problems are resolved by using physical methods like, guard tracing or increasing the distance between adjacent traces, [1]. Even if these methods yield good results, the bus surface is increased on the printed circuit board (PCB). A solution to this problem is to encode the sent information. By using crosstalk avoidance codes (CAC), there can be resolved crosstalk and inter-symbol interference (ISI) problems. CAC are developed by imposing rules regarding which switching pattern can be sent via the parallel data bus. By doing so, there are created forbidden transition channels (FTC). The purpose of the CAC is to enable a high speed transmission on a PCB built by using mainstream technologies without the high speed manufacturing processes.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116506204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273117
P. Mashkov, B. Gyoch, H. Beloev, S. Penchev
The aims of this work are connected with development of new method of LEDs' mounting onto the heat sink in lighting equipment. The technique involves usage of copper pins instead of standard MCPCBs. LEDs are soldered on copper pins. Mounting of LEDs demands boring holes in the heat sink and fixing copper pins into the holes by thermal conductive epoxy resin only. LED lamp is made using new technology and LEDs' thermal performance investigations are made at various ambient conditions (air temperatures from 20°C to 45°C) and different current values through LEDs - up to 600 mA. Temperature regimes of operation of power LEDs soldered on MCPCBs and on copper pins (and mounted on heat sink) are experimentally tested and compared. Experimental results show that utilization of copper pins underneath LED thermal pads ensures good dissipation of heat, good manufacturability, enables varied designs of light equipment and is cost effective.
{"title":"LED lamp - design and thermal management investigations","authors":"P. Mashkov, B. Gyoch, H. Beloev, S. Penchev","doi":"10.1109/ISSE.2012.6273117","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273117","url":null,"abstract":"The aims of this work are connected with development of new method of LEDs' mounting onto the heat sink in lighting equipment. The technique involves usage of copper pins instead of standard MCPCBs. LEDs are soldered on copper pins. Mounting of LEDs demands boring holes in the heat sink and fixing copper pins into the holes by thermal conductive epoxy resin only. LED lamp is made using new technology and LEDs' thermal performance investigations are made at various ambient conditions (air temperatures from 20°C to 45°C) and different current values through LEDs - up to 600 mA. Temperature regimes of operation of power LEDs soldered on MCPCBs and on copper pins (and mounted on heat sink) are experimentally tested and compared. Experimental results show that utilization of copper pins underneath LED thermal pads ensures good dissipation of heat, good manufacturability, enables varied designs of light equipment and is cost effective.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124355771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273097
A. Bonea, A. Brodeala, M. Vlădescu, P. Svasta
The work aims to assess the conductivity of Silver tracks printed using a state-of-the-art PixDro LP50 inkjet printer which has the capability to print conductive tracks with width as low as 50μm. The conductivity of tracks with different dimensions is measured using a Keithley measurement setup. The equivalent resistivity depends on the material, printing technology and geometrical dimensions. Profile measurements indicate a track thickness of around 300nm. The optimal printing resolution appears to be 450dpi, ensuring conductivity for all selected track widths from 50μm to 400μm. This paper analyses the influence of the layout on the electrical properties with a focus on determining the minimum metal quantity necessary to have tracks with good conductivity.
{"title":"Electrical conductivity of inkjet printed silver tracks","authors":"A. Bonea, A. Brodeala, M. Vlădescu, P. Svasta","doi":"10.1109/ISSE.2012.6273097","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273097","url":null,"abstract":"The work aims to assess the conductivity of Silver tracks printed using a state-of-the-art PixDro LP50 inkjet printer which has the capability to print conductive tracks with width as low as 50μm. The conductivity of tracks with different dimensions is measured using a Keithley measurement setup. The equivalent resistivity depends on the material, printing technology and geometrical dimensions. Profile measurements indicate a track thickness of around 300nm. The optimal printing resolution appears to be 450dpi, ensuring conductivity for all selected track widths from 50μm to 400μm. This paper analyses the influence of the layout on the electrical properties with a focus on determining the minimum metal quantity necessary to have tracks with good conductivity.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273155
Ina Toteva, A. Andonova
Gate-grounded NMOS is often used as ESD protection for circuit design. The ESD behavior of the NMOS transistor is based on the snapback action of its parasitic, lateral NPN BJT. Modeling this behavior of NMOS devices is very important for design of ICs, because there are no standard models, which can be used for describing high current regions in the NMOS snapback characteristic. In this paper an approach of modeling snapback characteristic of NMOS device, intended for use as ESD clamp in IC I/O cells, is proposed. The modeled snapback characteristic is simulated and evaluated using PSPICE.
{"title":"Modeling NMOS snapback characteristic using PSpice","authors":"Ina Toteva, A. Andonova","doi":"10.1109/ISSE.2012.6273155","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273155","url":null,"abstract":"Gate-grounded NMOS is often used as ESD protection for circuit design. The ESD behavior of the NMOS transistor is based on the snapback action of its parasitic, lateral NPN BJT. Modeling this behavior of NMOS devices is very important for design of ICs, because there are no standard models, which can be used for describing high current regions in the NMOS snapback characteristic. In this paper an approach of modeling snapback characteristic of NMOS device, intended for use as ESD clamp in IC I/O cells, is proposed. The modeled snapback characteristic is simulated and evaluated using PSPICE.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"103 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273127
M. Branzei, I. Plotog, F. Miculescu, G. Vărzaru, P. Svasta, A. Thumm
The continuous trend towards high density and miniaturization of electronic devices involves the use of multiple reflow processes in assembling technologies for second level of interconnections in electronic packaging hierarchy. According to the “4P” Soldering Model concept (4PSMC), considering the Pad-Paste-Pin-Process elements as Key Process Input Variables (KPIV), the solder joints are the result of KPIV synergistically interactions and correlations with consequences over their microstructure. In the paper, taking into consideration the cooling rate influence over intermetallic compounds (IMC) formation and microstructure, there was described the investigations over electrical and mechanical properties of solder joints resulted from multiple reflow Vapor Phase Soldering (VPS) process, in terms of 4PSMC. Maintaining the pad, pin and paste of KPIV as references measurements of solder joints resistances and shear forces were perform as function of VPS process's number for two values of cooling rate, respectively IMC microstructures and stereofractography studies. The results of the studies performed and presented in the paper will be use for improving process control in order to assure the solder joints reliability, to minimize losses on VPS lines, to reduce defects number and rework time.
{"title":"Solder joints properties as function of multiple reflow Vapor Phase Soldering process","authors":"M. Branzei, I. Plotog, F. Miculescu, G. Vărzaru, P. Svasta, A. Thumm","doi":"10.1109/ISSE.2012.6273127","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273127","url":null,"abstract":"The continuous trend towards high density and miniaturization of electronic devices involves the use of multiple reflow processes in assembling technologies for second level of interconnections in electronic packaging hierarchy. According to the “4P” Soldering Model concept (4PSMC), considering the Pad-Paste-Pin-Process elements as Key Process Input Variables (KPIV), the solder joints are the result of KPIV synergistically interactions and correlations with consequences over their microstructure. In the paper, taking into consideration the cooling rate influence over intermetallic compounds (IMC) formation and microstructure, there was described the investigations over electrical and mechanical properties of solder joints resulted from multiple reflow Vapor Phase Soldering (VPS) process, in terms of 4PSMC. Maintaining the pad, pin and paste of KPIV as references measurements of solder joints resistances and shear forces were perform as function of VPS process's number for two values of cooling rate, respectively IMC microstructures and stereofractography studies. The results of the studies performed and presented in the paper will be use for improving process control in order to assure the solder joints reliability, to minimize losses on VPS lines, to reduce defects number and rework time.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128297033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273169
N. Gutzeit, J. Muller, C. Reinlein, S. Gebhardt
In this paper the challenging manufacturing process of a deformable mirror for the wave front correction of a high energy laser is described. During this process the LTCC membrane as the base component with integrated sensors must endure several postfire processes at temperatures of up to 900°C without any degradation of the sensors' characteristics. In order to optimize the sensors, various combinations of resistor and conductor pastes and different geometries are characterized. The usability and the performance of the sensor elements after temperature treatment are investigated by measuring the resistance and its resistance temperature characteristic.
{"title":"LTCC membranes With integrated heating structures, temperature sensors and strain gauges","authors":"N. Gutzeit, J. Muller, C. Reinlein, S. Gebhardt","doi":"10.1109/ISSE.2012.6273169","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273169","url":null,"abstract":"In this paper the challenging manufacturing process of a deformable mirror for the wave front correction of a high energy laser is described. During this process the LTCC membrane as the base component with integrated sensors must endure several postfire processes at temperatures of up to 900°C without any degradation of the sensors' characteristics. In order to optimize the sensors, various combinations of resistor and conductor pastes and different geometries are characterized. The usability and the performance of the sensor elements after temperature treatment are investigated by measuring the resistance and its resistance temperature characteristic.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273149
D. Demeter, J. Banský
This paper is concerning with a virtual laboratory, which is implemented at the Department of technologies in Electronics and which will be used for distant and blended e-Learning of the technologies in electronics, as well as supporting the classical theoretical lectures. The laboratory itself is based on 360° panorama pictures created from every laboratory at our department. We have integrated into the system some basic information about equipment's, such as the name and type of the equipment, the technological procedures for which it can be used, some safety regulations related to working with the equipment and we have attached the user manual for equipment, if we had it available. The technological processes and laboratory exercises are covered by education videos and flash animations created by our colleagues. This system should help our students to get familiar with the laboratory equipment as well as with the technologies and techniques used at our department. This system is mainly designed for students, who have limited access to the laboratories (e.g. persons with some disability) and for the external students. It is also suitable for using in standard education process, where the number of the students is bigger, than the capacity of the laboratories. It should also support the lecturer at the theoretical lectures. In the future, the virtual laboratory will be used by the researchers for remote access of the laboratory equipment.
{"title":"Virtual laboratory for the e-learning education in the electronics technologies","authors":"D. Demeter, J. Banský","doi":"10.1109/ISSE.2012.6273149","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273149","url":null,"abstract":"This paper is concerning with a virtual laboratory, which is implemented at the Department of technologies in Electronics and which will be used for distant and blended e-Learning of the technologies in electronics, as well as supporting the classical theoretical lectures. The laboratory itself is based on 360° panorama pictures created from every laboratory at our department. We have integrated into the system some basic information about equipment's, such as the name and type of the equipment, the technological procedures for which it can be used, some safety regulations related to working with the equipment and we have attached the user manual for equipment, if we had it available. The technological processes and laboratory exercises are covered by education videos and flash animations created by our colleagues. This system should help our students to get familiar with the laboratory equipment as well as with the technologies and techniques used at our department. This system is mainly designed for students, who have limited access to the laboratories (e.g. persons with some disability) and for the external students. It is also suitable for using in standard education process, where the number of the students is bigger, than the capacity of the laboratories. It should also support the lecturer at the theoretical lectures. In the future, the virtual laboratory will be used by the researchers for remote access of the laboratory equipment.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129427671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273125
R. Kisiel, Z. Szczepański, P. Firek, J. Grochowski, M. Myśliwiec, M. Guziewicz
This work is devoted attaching technology between SiC structures and DBC substrates for creating SiC devices able to work at temperature up to 350°C. Our current work was concentrated on finding so called “pressure sintering” procedure in air using Ag micro particles. A special test samples with a size corresponding to the dimension of the SiC structures were assembled to DBC substrates with different surface finishing by Ag micro powder sintering. In the first series of experiments DBC substrates with Cu electroplated by Ni (3÷5 μm) and Au (above 1 μm) were used. It was found that by modifying application procedure of Ag micro powder onto DBC substrate with Cu/Ni/Au metallization, it is possible to obtain good adhesion between attached samples. The sintering is performed in air at temperature of 400°C for 40 min and pressure of 10 MPa. In the second series of experiments the SiC structures with Ni/Au metallization were assembled to DBC substrate with Cu/Ni/Au metallization. The adhesion higher than 10 MPa was obtained for such prepared samples.
{"title":"Silver micropowders as SiC die attach material for high temperature applications","authors":"R. Kisiel, Z. Szczepański, P. Firek, J. Grochowski, M. Myśliwiec, M. Guziewicz","doi":"10.1109/ISSE.2012.6273125","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273125","url":null,"abstract":"This work is devoted attaching technology between SiC structures and DBC substrates for creating SiC devices able to work at temperature up to 350°C. Our current work was concentrated on finding so called “pressure sintering” procedure in air using Ag micro particles. A special test samples with a size corresponding to the dimension of the SiC structures were assembled to DBC substrates with different surface finishing by Ag micro powder sintering. In the first series of experiments DBC substrates with Cu electroplated by Ni (3÷5 μm) and Au (above 1 μm) were used. It was found that by modifying application procedure of Ag micro powder onto DBC substrate with Cu/Ni/Au metallization, it is possible to obtain good adhesion between attached samples. The sintering is performed in air at temperature of 400°C for 40 min and pressure of 10 MPa. In the second series of experiments the SiC structures with Ni/Au metallization were assembled to DBC substrate with Cu/Ni/Au metallization. The adhesion higher than 10 MPa was obtained for such prepared samples.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273089
Y. Dzhenkov
The article is concerned to an elaboration of an image intensifier power supply. Here is represented the circuit that generate the high voltage needed for the screen. The circuit is represented by a blocking generator, who is followed by a voltage multiplier. In my work I'm trying to create a simple, but reliable model of a power supply that is powered by two standard AA batteries.
{"title":"Image intensifier power supply","authors":"Y. Dzhenkov","doi":"10.1109/ISSE.2012.6273089","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273089","url":null,"abstract":"The article is concerned to an elaboration of an image intensifier power supply. Here is represented the circuit that generate the high voltage needed for the screen. The circuit is represented by a blocking generator, who is followed by a voltage multiplier. In my work I'm trying to create a simple, but reliable model of a power supply that is powered by two standard AA batteries.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-05-09DOI: 10.1109/ISSE.2012.6273121
S. Kirsten, J. Uhlemann, M. Braunschweig, K. Wolter
Development of smart medical devices for long-term implantation requires new encapsulation technologies with a special focus on flexible packaging of electronic devices. Biocompatible, high performance polymers seem to be suitable for such applications, however their protective function i.e. suppressing harmful interactions between the human and the foreign body is still unknown. Here, we evaluated this protective function of six polymers with regard to surface properties, water absorption and water solubility. Among all polymers investigated, silicone (low-consistency) showed the best characteristics compared to epoxy resin or polyurethane.
{"title":"Packaging of electronic devices for long-term implantation","authors":"S. Kirsten, J. Uhlemann, M. Braunschweig, K. Wolter","doi":"10.1109/ISSE.2012.6273121","DOIUrl":"https://doi.org/10.1109/ISSE.2012.6273121","url":null,"abstract":"Development of smart medical devices for long-term implantation requires new encapsulation technologies with a special focus on flexible packaging of electronic devices. Biocompatible, high performance polymers seem to be suitable for such applications, however their protective function i.e. suppressing harmful interactions between the human and the foreign body is still unknown. Here, we evaluated this protective function of six polymers with regard to surface properties, water absorption and water solubility. Among all polymers investigated, silicone (low-consistency) showed the best characteristics compared to epoxy resin or polyurethane.","PeriodicalId":277579,"journal":{"name":"2012 35th International Spring Seminar on Electronics Technology","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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