Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785953
I. Adesida, A. Mahajan, G. Cueva
Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.
{"title":"InP-based HEMTs for high speed, low power circuit applications","authors":"I. Adesida, A. Mahajan, G. Cueva","doi":"10.1109/ICSICT.1998.785953","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785953","url":null,"abstract":"Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132355296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a manufacturing process of a bipolar IC with a Zener diode. The Zener diode is manufactured by a process which is compatible with the ordinary bipolar IC process. Since the breakdown voltage of the Zener diode is not equal to the emitter-base breakdown voltage of the longitudinal n-p-n transistors, the doping concentration in the positive area of the Zener diode is not the same as the doping concentration in the base area of the n-p-n transistor. The doping concentration and junction depth of the positive of the Zener diode is decided by its breakdown voltage value. It is produced by another implantation dose and followed by a drive-in step. Hence this process utilizes two boron implantations during the base area formation, one is used to form the base area of ordinary n-p-n transistors, another is used to make the positive of the Zener diode. The relationship between the implantation dose and breakdown voltage of the Zener diode is investigated. A bipolar ASIC with a Zener diode was fabricated by this process.
{"title":"Manufacturing process of bipolar IC with Zener diode","authors":"Jianfeng Wang, Jianmin Cao, Yongming Shen, Yuefang Jiang","doi":"10.1109/ICSICT.1998.785795","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785795","url":null,"abstract":"This paper describes a manufacturing process of a bipolar IC with a Zener diode. The Zener diode is manufactured by a process which is compatible with the ordinary bipolar IC process. Since the breakdown voltage of the Zener diode is not equal to the emitter-base breakdown voltage of the longitudinal n-p-n transistors, the doping concentration in the positive area of the Zener diode is not the same as the doping concentration in the base area of the n-p-n transistor. The doping concentration and junction depth of the positive of the Zener diode is decided by its breakdown voltage value. It is produced by another implantation dose and followed by a drive-in step. Hence this process utilizes two boron implantations during the base area formation, one is used to form the base area of ordinary n-p-n transistors, another is used to make the positive of the Zener diode. The relationship between the implantation dose and breakdown voltage of the Zener diode is investigated. A bipolar ASIC with a Zener diode was fabricated by this process.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785964
Hu Dexiu
Semiconductor laser amplifier (SLA) will be an important device in the fields of both of fiber-optic communication and optical information processing. In this paper the SLA's future is analyzed. Some experimental results about SLA and its application for wavelength conversion are studied.
{"title":"Semiconductor laser amplifier and applications","authors":"Hu Dexiu","doi":"10.1109/ICSICT.1998.785964","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785964","url":null,"abstract":"Semiconductor laser amplifier (SLA) will be an important device in the fields of both of fiber-optic communication and optical information processing. In this paper the SLA's future is analyzed. Some experimental results about SLA and its application for wavelength conversion are studied.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786088
Ru Huang, Bing Yang, Xing Zhang, Yangyuan Wang
The comprehensive design guidelines for SOI gate controlled hybrid transistor (GCHT) are provided in this paper for the first time, especially for GCHT operating at low voltage, which is an advantageous operating region of GCHT. The investigated mechanisms in this study involve short channel effects, current driving capability, device off-characteristics and open-circuit voltage gain. The design curves for low operating voltage are presented by synthesizing the results, with tradeoffs between different parameter requirements for different effects illustrated explicitly. The allowable design region is greatly-broadened, pointing out the direction for deep submicron device development.
{"title":"Design consideration for SOI gate controlled hybrid transistor operating at low voltage","authors":"Ru Huang, Bing Yang, Xing Zhang, Yangyuan Wang","doi":"10.1109/ICSICT.1998.786088","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786088","url":null,"abstract":"The comprehensive design guidelines for SOI gate controlled hybrid transistor (GCHT) are provided in this paper for the first time, especially for GCHT operating at low voltage, which is an advantageous operating region of GCHT. The investigated mechanisms in this study involve short channel effects, current driving capability, device off-characteristics and open-circuit voltage gain. The design curves for low operating voltage are presented by synthesizing the results, with tradeoffs between different parameter requirements for different effects illustrated explicitly. The allowable design region is greatly-broadened, pointing out the direction for deep submicron device development.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"74 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134428052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785960
Wu Jie, Guo Fang-min, Xia Guan-qun
By variation of the thickness and doping concentration of the p/sup +/ and intrinsic regions, the barrier height and asymmetry of the structure can be independently varied. A model is developed to investigate the extent to which the above factors may affect the PDBDs' dc characteristics.
{"title":"Design consideration for planar doped barrier diodes' dc characteristics","authors":"Wu Jie, Guo Fang-min, Xia Guan-qun","doi":"10.1109/ICSICT.1998.785960","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785960","url":null,"abstract":"By variation of the thickness and doping concentration of the p/sup +/ and intrinsic regions, the barrier height and asymmetry of the structure can be independently varied. A model is developed to investigate the extent to which the above factors may affect the PDBDs' dc characteristics.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134452823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786526
Chang Liu
MEMS technology can enable new circuit components. Current examples include RF signal switches, tunable capacitors and inductors, resonant filters, antennas, and relays. These components, all involving micromechanical principles, can provide enhanced performances and reconfigurability, reduced component sizes, and potentially simplified system-level design. I will discuss our DARPA-funded efforts in developing electromechanical RF switches, high-gain antennas, and new types of planar waveguides. Thermal-mechanical RF switches exhibit low on-state insertion loss and high off-state isolation compared with conventional transistor-based counterparts, while operating under IC-compatible bias conditions.
{"title":"Micro electromechanical systems (MEMS): technology and future applications in circuits","authors":"Chang Liu","doi":"10.1109/ICSICT.1998.786526","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786526","url":null,"abstract":"MEMS technology can enable new circuit components. Current examples include RF signal switches, tunable capacitors and inductors, resonant filters, antennas, and relays. These components, all involving micromechanical principles, can provide enhanced performances and reconfigurability, reduced component sizes, and potentially simplified system-level design. I will discuss our DARPA-funded efforts in developing electromechanical RF switches, high-gain antennas, and new types of planar waveguides. Thermal-mechanical RF switches exhibit low on-state insertion loss and high off-state isolation compared with conventional transistor-based counterparts, while operating under IC-compatible bias conditions.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133462698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785897
Fengying Yao, Bizhou Li, Min Zhang
Fixed-point DSP implementation of the decoder and the synthesizer of a real time vocoder with 1.4 kbps bit rate has been accomplished instead of the usual realization of low bit rate vocoder in floating point DSP. Replacing floating point values with fixed-point ones and other approaches have been adopted to reach a real time solution. The implemented fixed-point decoder and synthesizer run at 11.3 MIPS on the average and occupy 1246 words of program memory, 1338 words of table ROM and 814 words of RAM in a 40 MHz TMS320C50 DSP chip. The results indicate the possibility to implement the whole vocoder with low cost fixed-point DSP.
{"title":"A fixed-point DSP implementation for a low bit rate vocoder","authors":"Fengying Yao, Bizhou Li, Min Zhang","doi":"10.1109/ICSICT.1998.785897","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785897","url":null,"abstract":"Fixed-point DSP implementation of the decoder and the synthesizer of a real time vocoder with 1.4 kbps bit rate has been accomplished instead of the usual realization of low bit rate vocoder in floating point DSP. Replacing floating point values with fixed-point ones and other approaches have been adopted to reach a real time solution. The implemented fixed-point decoder and synthesizer run at 11.3 MIPS on the average and occupy 1246 words of program memory, 1338 words of table ROM and 814 words of RAM in a 40 MHz TMS320C50 DSP chip. The results indicate the possibility to implement the whole vocoder with low cost fixed-point DSP.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133495613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785822
H. Jia, Xiaojun Jin, Jinshu Zhang, Pei-yi Chen, P. Tsien
Ultra High Vacuum Chemical Vapor Deposition (UHV/CVD) is carried out to deposit silicon. The deposition is carried out in the temperature range of 550 to 800/spl deg/C. Electrochemical etching is used to test the defects in epitaxial films. Two different ways of etching were performed to validate the thin film etching. The results is almost the same. The defects are visible by the microscope at about 600/spl times/. It is found that the film quality is good in two extreme temperature ranges, i.e. 500 to 700/spl deg/C and above 750/spl deg/C, which was also observed by other authors. The defect density is estimated to be in the order of 10/sup 6/ to 10/sup 8/ cm/sup -2/, including line defects, even micro-defects because of the poor environment cleanliness.
{"title":"Electrochemical etching used on UHV/CVD epitaxial thin films","authors":"H. Jia, Xiaojun Jin, Jinshu Zhang, Pei-yi Chen, P. Tsien","doi":"10.1109/ICSICT.1998.785822","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785822","url":null,"abstract":"Ultra High Vacuum Chemical Vapor Deposition (UHV/CVD) is carried out to deposit silicon. The deposition is carried out in the temperature range of 550 to 800/spl deg/C. Electrochemical etching is used to test the defects in epitaxial films. Two different ways of etching were performed to validate the thin film etching. The results is almost the same. The defects are visible by the microscope at about 600/spl times/. It is found that the film quality is good in two extreme temperature ranges, i.e. 500 to 700/spl deg/C and above 750/spl deg/C, which was also observed by other authors. The defect density is estimated to be in the order of 10/sup 6/ to 10/sup 8/ cm/sup -2/, including line defects, even micro-defects because of the poor environment cleanliness.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114094163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786439
Jeng-Hua Wei, Si‐Chen Lee
In order to reduce the bias-induced degradation in hydrogenated amorphous silicon thin film transistors (a-Si:H TFT), a deuterated amorphous silicon layer prepared by deuterium plasma treatment is used as the active layer. It is demonstrated that the stability, i.e., the shifts of threshold voltage and subthreshold swing, of deuterated amorphous silicon thin film transistor can be indeed improved as compared to the hydrogenated ones. This result is consistent with the improvement of the light-induced degradation in deuterated amorphous silicon films and this improvement can be explained by the efficient coupling between Si-D wagging mode and amorphous silicon phonon mode.
{"title":"The improved stability of deuterated amorphous silicon thin film transistor","authors":"Jeng-Hua Wei, Si‐Chen Lee","doi":"10.1109/ICSICT.1998.786439","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786439","url":null,"abstract":"In order to reduce the bias-induced degradation in hydrogenated amorphous silicon thin film transistors (a-Si:H TFT), a deuterated amorphous silicon layer prepared by deuterium plasma treatment is used as the active layer. It is demonstrated that the stability, i.e., the shifts of threshold voltage and subthreshold swing, of deuterated amorphous silicon thin film transistor can be indeed improved as compared to the hydrogenated ones. This result is consistent with the improvement of the light-induced degradation in deuterated amorphous silicon films and this improvement can be explained by the efficient coupling between Si-D wagging mode and amorphous silicon phonon mode.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114166264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785934
Chen Guping, Zhu Zhaohui
A basic review of ESD protection mechanism is presented and a typical ESD on chip protection circuit used in IC card is discussed. Some critical factors correlated to ESD performance ore considered to form physical structure of protection device in the CMOS technology.
{"title":"ESD protection circuit in IC card","authors":"Chen Guping, Zhu Zhaohui","doi":"10.1109/ICSICT.1998.785934","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785934","url":null,"abstract":"A basic review of ESD protection mechanism is presented and a typical ESD on chip protection circuit used in IC card is discussed. Some critical factors correlated to ESD performance ore considered to form physical structure of protection device in the CMOS technology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117294258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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