Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785973
F. Shiwei, Xie Xuesong, Liu Wei, Lu Changzhi, He Yan, Shen Guangdi
Using the terminal voltage method, we measured and analyzed the thermal characteristics of the laser diodes (LD). From heating response curves, it is possible to determine the thermal resistance, R/sub th/ of different layers of the packaged LDs. The dependence of the R/sub th/ on the working current was measured. It shows much difference between below and above threshold current. This gives much information about the coupling between thermal and optical properties.
{"title":"The analysis of thermal characteristics of the laser diode by transient thermal response method","authors":"F. Shiwei, Xie Xuesong, Liu Wei, Lu Changzhi, He Yan, Shen Guangdi","doi":"10.1109/ICSICT.1998.785973","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785973","url":null,"abstract":"Using the terminal voltage method, we measured and analyzed the thermal characteristics of the laser diodes (LD). From heating response curves, it is possible to determine the thermal resistance, R/sub th/ of different layers of the packaged LDs. The dependence of the R/sub th/ on the working current was measured. It shows much difference between below and above threshold current. This gives much information about the coupling between thermal and optical properties.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130916759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785845
G. Minghui, Zhao Haijun, A. Bandyopadhyay, C. Jiang, Foo Pang Dow
This paper describes a low cost, CMOS foundry compatible BiCMOS process for 1.9 GHz RF applications. It keeps the simple feature of the triple-well single-poly approach while achieving much higher f/sub T/ by utilizing novel c-well profile engineering to reduce base and collector series resistance.
{"title":"High speed low cost BiCMOS for RF applications using profile engineering","authors":"G. Minghui, Zhao Haijun, A. Bandyopadhyay, C. Jiang, Foo Pang Dow","doi":"10.1109/ICSICT.1998.785845","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785845","url":null,"abstract":"This paper describes a low cost, CMOS foundry compatible BiCMOS process for 1.9 GHz RF applications. It keeps the simple feature of the triple-well single-poly approach while achieving much higher f/sub T/ by utilizing novel c-well profile engineering to reduce base and collector series resistance.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786103
S. Bengtsson
Silicon-on-insulator (SOI) materials are expected to get increased attention for mainstream CMOS as well as for high frequency or high voltage applications. Of the existing methods for manufacture of SOI materials, wafer bonding combined with smartcut seems to be the most promising approach. In the case of wafer bonding, surface micro-roughness, wafer dimensions, surface chemistry and ambient pressure all influence the result. In the smartcut technology, hydrogen implantation and an annealing step can be controlled for a precise splitting of a silicon wafer, thereby forming a thin silicon film. In this presentation the application of wafer bonding and smartcut for formation of SOI materials is reviewed.
{"title":"Wafer bonding and smartcut for formation of silicon-on-insulator materials","authors":"S. Bengtsson","doi":"10.1109/ICSICT.1998.786103","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786103","url":null,"abstract":"Silicon-on-insulator (SOI) materials are expected to get increased attention for mainstream CMOS as well as for high frequency or high voltage applications. Of the existing methods for manufacture of SOI materials, wafer bonding combined with smartcut seems to be the most promising approach. In the case of wafer bonding, surface micro-roughness, wafer dimensions, surface chemistry and ambient pressure all influence the result. In the smartcut technology, hydrogen implantation and an annealing step can be controlled for a precise splitting of a silicon wafer, thereby forming a thin silicon film. In this presentation the application of wafer bonding and smartcut for formation of SOI materials is reviewed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785789
Xing Zhang, X. Xi, Ru Huang, Yangyuan Wang
In this paper we present the total dose radiation characterization of CMOS/SIMOX devices with CoSi/sub 2/ salicide. Various SIMOX devices, such as with or without CoSi/sub 2/, are applied during irradiation in order to define the better radiation hardened process for SOI MOSFETs and ring oscillators. As the experimental results show, the application of Co salicide on SOI CMOS circuits not only reduces the source/drain series resistance, but also improves significantly the SOI radiation hardness properties in terms of threshold voltage shift, junction leakage and CMOS ring oscillator propagation delay.
{"title":"The effect of cobalt salicide on SOI CMOS radiation characteristics","authors":"Xing Zhang, X. Xi, Ru Huang, Yangyuan Wang","doi":"10.1109/ICSICT.1998.785789","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785789","url":null,"abstract":"In this paper we present the total dose radiation characterization of CMOS/SIMOX devices with CoSi/sub 2/ salicide. Various SIMOX devices, such as with or without CoSi/sub 2/, are applied during irradiation in order to define the better radiation hardened process for SOI MOSFETs and ring oscillators. As the experimental results show, the application of Co salicide on SOI CMOS circuits not only reduces the source/drain series resistance, but also improves significantly the SOI radiation hardness properties in terms of threshold voltage shift, junction leakage and CMOS ring oscillator propagation delay.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123013473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786099
R. Bower
A variety of technologies have been applied to the formation of three-dimensional microstructures in the past two decades. In this talk the author describes work in his group to form three-dimensional structures using direct bonding and smart cut techniques.
{"title":"3-dimensional microelectronic integration","authors":"R. Bower","doi":"10.1109/ICSICT.1998.786099","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786099","url":null,"abstract":"A variety of technologies have been applied to the formation of three-dimensional microstructures in the past two decades. In this talk the author describes work in his group to form three-dimensional structures using direct bonding and smart cut techniques.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121258072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785925
Qiu Xiaohai, C. Hongyi
Latches and flip-flops used in low power circuits are discussed in this paper. Two kinds of latches of 5-T and 4-T are evolved from the standard 8-T static latch for low power application. Simulation results show that the 4-T latch has the lowest power consumption with no speed penalty. The 4-T latch is usually considered as dynamic. However, detailed analysis shows that it may be static under certain conditions, which are also given in this paper. Single-edge-trigged (SET) flip-flops and double-edge-trigged (DET) flip-flop based on these latches are also presented. Significant power and area savings can achieve by using 4-T latches.
{"title":"Discussion on the low-power CMOS latches and flip-flops","authors":"Qiu Xiaohai, C. Hongyi","doi":"10.1109/ICSICT.1998.785925","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785925","url":null,"abstract":"Latches and flip-flops used in low power circuits are discussed in this paper. Two kinds of latches of 5-T and 4-T are evolved from the standard 8-T static latch for low power application. Simulation results show that the 4-T latch has the lowest power consumption with no speed penalty. The 4-T latch is usually considered as dynamic. However, detailed analysis shows that it may be static under certain conditions, which are also given in this paper. Single-edge-trigged (SET) flip-flops and double-edge-trigged (DET) flip-flop based on these latches are also presented. Significant power and area savings can achieve by using 4-T latches.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786122
Chenglu Lin, Miao Zhang, X. Duo, R. Scholz, U. Gosele
Physical phenomena such as blistering and flaking of silicon under high dose H/sup +/ ion implantation have successfully been applied to the Smart-cut SOI process. In this study, a novel gettering method using nanovoids induced by H/sup +/ or He/sup +/ implantation has been studied to remove Cu and Ni impurities from the top Si layer of SOI wafers. He/sup +/ and H/sup +/ ions were implanted into the substrates of SIMOX (separation by implantation of oxygen) wafers to form a layer of nanocavities beneath the BOX layer. The gettering of Cu and Ni impurities, which were implanted into the top Si layer, to the voids has been studied by SIMS (secondary ion mass spectroscopy). XTEM (cross-sectional transmission electron microscopy) was employed to investigate the microstructure of the He/sup +/ and H/sup +/ implantation-induced voids in silicon. The results indicate that the voids induced by He/sup +/ and H/sup +/ implantation are strong gettering centers for Cu and Ni in SIMOX wafers. He/sup +/ ion implantation is found to be more suitable for void layer formation and gettering than H/sup +/ implantation.
{"title":"Nanovoid layer induced by He/sup +/ and H/sup +/ implantation and its gettering effect in SOI wafers","authors":"Chenglu Lin, Miao Zhang, X. Duo, R. Scholz, U. Gosele","doi":"10.1109/ICSICT.1998.786122","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786122","url":null,"abstract":"Physical phenomena such as blistering and flaking of silicon under high dose H/sup +/ ion implantation have successfully been applied to the Smart-cut SOI process. In this study, a novel gettering method using nanovoids induced by H/sup +/ or He/sup +/ implantation has been studied to remove Cu and Ni impurities from the top Si layer of SOI wafers. He/sup +/ and H/sup +/ ions were implanted into the substrates of SIMOX (separation by implantation of oxygen) wafers to form a layer of nanocavities beneath the BOX layer. The gettering of Cu and Ni impurities, which were implanted into the top Si layer, to the voids has been studied by SIMS (secondary ion mass spectroscopy). XTEM (cross-sectional transmission electron microscopy) was employed to investigate the microstructure of the He/sup +/ and H/sup +/ implantation-induced voids in silicon. The results indicate that the voids induced by He/sup +/ and H/sup +/ implantation are strong gettering centers for Cu and Ni in SIMOX wafers. He/sup +/ ion implantation is found to be more suitable for void layer formation and gettering than H/sup +/ implantation.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121660420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785957
Cong Gu, G. Qian, You-Wei Liu
Based on the proposed many models for GaAs MESFET, we put forth a newly modified large-signal model for 4 W 12 mm multi-cell microwave power GaAs MESFET in this paper. The newly improved model presented here includes the analytical expressions of I/sub ds/(V/sub gs/, V/sub ds/) elements operating at microwave frequency in large signal. Also comparison with three kinds of the original formula proposed by Materka, Jastrzebski and Curtice, we found that the modified I/sub ds/ in here is more accuracy.
{"title":"Nonlinear modeling of 4 W 12 mm multi-cell microwave power GaAs MESFET","authors":"Cong Gu, G. Qian, You-Wei Liu","doi":"10.1109/ICSICT.1998.785957","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785957","url":null,"abstract":"Based on the proposed many models for GaAs MESFET, we put forth a newly modified large-signal model for 4 W 12 mm multi-cell microwave power GaAs MESFET in this paper. The newly improved model presented here includes the analytical expressions of I/sub ds/(V/sub gs/, V/sub ds/) elements operating at microwave frequency in large signal. Also comparison with three kinds of the original formula proposed by Materka, Jastrzebski and Curtice, we found that the modified I/sub ds/ in here is more accuracy.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"404 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786061
M. Hong
Growth of an oxide mixture, Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/), in ultra-high vacuum, on clean and ordered GaAs[100] surface has produced atomically smooth oxide/GaAs interfaces with a low interfacial density of states. Both enhancement-mode p- and n-channel GaAs metal oxide semiconductor field effect transistors (MOSFETs) on GaAs semi-insulating substrates with inversion were demonstrated using this novel oxide as the gate dielectric and a conventional ion-implant technology. Depletion-mode GaAs MOSFETs with accumulation were also fabricated. The Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) films with thickness varying from 500 to 50 /spl Aring/ show a low leakage current density of 10/sup -9/ A/cm/sup 2/ at low gate bias up to 2.5 V, and electrical breakdown fields of >10 MV/cm.
{"title":"GaAs MOSFETs using Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric","authors":"M. Hong","doi":"10.1109/ICSICT.1998.786061","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786061","url":null,"abstract":"Growth of an oxide mixture, Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/), in ultra-high vacuum, on clean and ordered GaAs[100] surface has produced atomically smooth oxide/GaAs interfaces with a low interfacial density of states. Both enhancement-mode p- and n-channel GaAs metal oxide semiconductor field effect transistors (MOSFETs) on GaAs semi-insulating substrates with inversion were demonstrated using this novel oxide as the gate dielectric and a conventional ion-implant technology. Depletion-mode GaAs MOSFETs with accumulation were also fabricated. The Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) films with thickness varying from 500 to 50 /spl Aring/ show a low leakage current density of 10/sup -9/ A/cm/sup 2/ at low gate bias up to 2.5 V, and electrical breakdown fields of >10 MV/cm.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122633511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785858
J. Freytag, I. Wennemuth
Palladium (Pd) wire is a favourable metal for wire bonding electronic devices operating an enhanced temperatures. The bonding process was investigated and the significant process parameters were identified. Different parameter sets were worked out for various bonding machines. The separation of the wire after the bonding process was found to be decisive for the quality of the bond. Thermal ageing at enhanced temperatures (i.e. 300/spl deg/C for 1000 h) causes no degradation of the bonds.
{"title":"Wire bonding technique for high temperature applications","authors":"J. Freytag, I. Wennemuth","doi":"10.1109/ICSICT.1998.785858","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785858","url":null,"abstract":"Palladium (Pd) wire is a favourable metal for wire bonding electronic devices operating an enhanced temperatures. The bonding process was investigated and the significant process parameters were identified. Different parameter sets were worked out for various bonding machines. The separation of the wire after the bonding process was found to be decisive for the quality of the bond. Thermal ageing at enhanced temperatures (i.e. 300/spl deg/C for 1000 h) causes no degradation of the bonds.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122773656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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