Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785774
Ruichen Liu, C. Pai
Key interconnect issues for giga-scale integration, interconnect architecture, delay and yield, are examined. Even using new materials. Cu and low K dielectric (K=2), interconnect delay still dominates and clock speed of 2 GHz for large circuits is not achievable without new innovation in architecture. Cumulative yield loss from multiple levels of interconnect will dominate the die yield, and the more promising reverse-scaling architecture suffers more severe yield loss due to increased die size. Overall, interconnect technology, at giga-scale integration will be one of the most challenging tasks and innovation in architecture is needed.
{"title":"Interconnect technology for giga-scale integration","authors":"Ruichen Liu, C. Pai","doi":"10.1109/ICSICT.1998.785774","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785774","url":null,"abstract":"Key interconnect issues for giga-scale integration, interconnect architecture, delay and yield, are examined. Even using new materials. Cu and low K dielectric (K=2), interconnect delay still dominates and clock speed of 2 GHz for large circuits is not achievable without new innovation in architecture. Cumulative yield loss from multiple levels of interconnect will dominate the die yield, and the more promising reverse-scaling architecture suffers more severe yield loss due to increased die size. Overall, interconnect technology, at giga-scale integration will be one of the most challenging tasks and innovation in architecture is needed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785778
C. Case
Summary form only given, as follows. With the IC industry projected to grow to $273 billion by the year 2000 and worldwide electronic production to $1 trillion in the same period, the author discusses the macroeconomics and demographic trends that will sustain this growth. Applications, opportunity drivers and production are all discussed, by region. The Semiconductor Industry Association's National Technology Roadmap for Semiconductor forecasts 1 GHz 14 cm/sup 2/ chips by the year 2010; part of burden in meeting the cost/performance challenges to keep the industry on this roadmap falls on the IC back-end interconnection. The increased complexity supporting enhanced performance of the these IC's comes from additional wiring levels, greater interconnect density and the total interconnect length. The author explores these complexity issues and the economic trade-off between performance and functionality.
{"title":"IC manufacturing options to break the cost/performance bottleneck","authors":"C. Case","doi":"10.1109/ICSICT.1998.785778","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785778","url":null,"abstract":"Summary form only given, as follows. With the IC industry projected to grow to $273 billion by the year 2000 and worldwide electronic production to $1 trillion in the same period, the author discusses the macroeconomics and demographic trends that will sustain this growth. Applications, opportunity drivers and production are all discussed, by region. The Semiconductor Industry Association's National Technology Roadmap for Semiconductor forecasts 1 GHz 14 cm/sup 2/ chips by the year 2010; part of burden in meeting the cost/performance challenges to keep the industry on this roadmap falls on the IC back-end interconnection. The increased complexity supporting enhanced performance of the these IC's comes from additional wiring levels, greater interconnect density and the total interconnect length. The author explores these complexity issues and the economic trade-off between performance and functionality.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786135
Chen Xu, Jingyan Zhang, Lixin Zhao, J. Deng, Changbao Tao, G. Gao, Jinyu Du, Ji Luo, Deshu Zou, Jianxing Chen, G. Shen
Ion implantation and the side-wall oxide self-aligned technique was used to reduce the extrinsic base resistance of a SiGe HBT. The sheet resistance of the SiGe layer was reduced over 20 times under proper implantation and annealing parameters, and ohmic contacting was also improved. This can greatly enhance the frequency performance and reduce the noise figure of SiGe HBT. The SiGe sheet resistance is sensitive to the implantation and annealing parameters. For our samples an implantation dose of 10/sup 16//cm/sup 3/ and energy of 35 kev, annealing temperature from 960/spl deg/C to 1000/spl deg/C is suitable.
{"title":"The reduction of base resistance of SiGe/Si HBT via ion implantation and side-wall oxide self-aligned technique","authors":"Chen Xu, Jingyan Zhang, Lixin Zhao, J. Deng, Changbao Tao, G. Gao, Jinyu Du, Ji Luo, Deshu Zou, Jianxing Chen, G. Shen","doi":"10.1109/ICSICT.1998.786135","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786135","url":null,"abstract":"Ion implantation and the side-wall oxide self-aligned technique was used to reduce the extrinsic base resistance of a SiGe HBT. The sheet resistance of the SiGe layer was reduced over 20 times under proper implantation and annealing parameters, and ohmic contacting was also improved. This can greatly enhance the frequency performance and reduce the noise figure of SiGe HBT. The SiGe sheet resistance is sensitive to the implantation and annealing parameters. For our samples an implantation dose of 10/sup 16//cm/sup 3/ and energy of 35 kev, annealing temperature from 960/spl deg/C to 1000/spl deg/C is suitable.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"188 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114120571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785811
Q.W. Pen, van den Aj Berg, L.K. Nanvpr, J. Slabbekoorn, C. Visser
High power excimer laser annealing is used to activate dopants implanted in polysilicon layers. Sheet resistances as low os 50 /spl Omega///spl square/ are achieved for thin polysilicon layers on oxide, and low ohmic contacts have been produced to implanted junctions elevated by a polysilicon layer. The influence of the thickness of either the poly or the underlying oxide is evaluated.
{"title":"Low-ohmic contacts by excimer laser annealing of implanted polysilicon","authors":"Q.W. Pen, van den Aj Berg, L.K. Nanvpr, J. Slabbekoorn, C. Visser","doi":"10.1109/ICSICT.1998.785811","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785811","url":null,"abstract":"High power excimer laser annealing is used to activate dopants implanted in polysilicon layers. Sheet resistances as low os 50 /spl Omega///spl square/ are achieved for thin polysilicon layers on oxide, and low ohmic contacts have been produced to implanted junctions elevated by a polysilicon layer. The influence of the thickness of either the poly or the underlying oxide is evaluated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786455
He Yu-liang, Peng Yingcai, Yu Minbin, Liu Ming, Liu Yuexia, X. Gangyi, Luo Jiajun, Wang Tianmin
Nanocrystalline silicon films on crystalline silicon diodes were fabricated and electrically characterized. The nc-Si:H film was deposited by plasma enhanced chemical vapor deposition. With the difference of the thickness of the nc-Si:H film and the doping type of the c-Si substrate two kinds of diodes, tunneling diodes and heterojunction diodes, were formed. For the tunneling diode, resonant tunneling and quantum staircases were observed in its I-V and /spl sigma/-V curves in liquid nitrogen temperature range (/spl sim/77 K). For heterojunction diodes, we found some unique characters differing from other semiconductor heterojunctions. Both of these devices indicate quantum tunneling features in the conduction mechanism.
{"title":"A study of electrical properties on nc-Si/c-Si heterojunction diodes","authors":"He Yu-liang, Peng Yingcai, Yu Minbin, Liu Ming, Liu Yuexia, X. Gangyi, Luo Jiajun, Wang Tianmin","doi":"10.1109/ICSICT.1998.786455","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786455","url":null,"abstract":"Nanocrystalline silicon films on crystalline silicon diodes were fabricated and electrically characterized. The nc-Si:H film was deposited by plasma enhanced chemical vapor deposition. With the difference of the thickness of the nc-Si:H film and the doping type of the c-Si substrate two kinds of diodes, tunneling diodes and heterojunction diodes, were formed. For the tunneling diode, resonant tunneling and quantum staircases were observed in its I-V and /spl sigma/-V curves in liquid nitrogen temperature range (/spl sim/77 K). For heterojunction diodes, we found some unique characters differing from other semiconductor heterojunctions. Both of these devices indicate quantum tunneling features in the conduction mechanism.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131928258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785869
D. Hesse, R. Mattheis, P. Werner
Growth kinetics and interface structures of epitaxial, nanometer-sized NiSi/sub 2/ islands of A- and B-orientations on Si(111) single-crystal substrates are studied by RBS, TEM/SAED, and high-resolution TEM on cross sections. The islands grow by an in situ solid state reaction between the silicon substrate and a nickel vapour at temperatures of 300/spl deg/C and 400/spl deg/C. Owing to a crossover of the thermal expansion curves of NiSi/sub 2/ and Si at 400/spl deg/C, stresses determine the shares of (three-dimensional) A-islands and (two-dimensional) B-islands at different temperatures. Furthermore, A-islands contain dislocations, whereas B-islands are completely free from lattice defects, with the exception of interfacial steps of various heights occurring at the NiSi/sub 2//Si(111) growth fronts of both island types. These steps play an essential role in the island growth. The difference in the reaction kinetics observed between A- and B-islands at 400/spl deg/C is explained in terms of different kinetic reaction barriers present at the structurally different NiSi/sub 2/Si(111) growth fronts under the A-and B-islands.
{"title":"The effect of stress and kinetic reaction barriers on the reactive growth of nanometer-sized epitaxial NiSi/sub 2/ islands on Si(111)","authors":"D. Hesse, R. Mattheis, P. Werner","doi":"10.1109/ICSICT.1998.785869","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785869","url":null,"abstract":"Growth kinetics and interface structures of epitaxial, nanometer-sized NiSi/sub 2/ islands of A- and B-orientations on Si(111) single-crystal substrates are studied by RBS, TEM/SAED, and high-resolution TEM on cross sections. The islands grow by an in situ solid state reaction between the silicon substrate and a nickel vapour at temperatures of 300/spl deg/C and 400/spl deg/C. Owing to a crossover of the thermal expansion curves of NiSi/sub 2/ and Si at 400/spl deg/C, stresses determine the shares of (three-dimensional) A-islands and (two-dimensional) B-islands at different temperatures. Furthermore, A-islands contain dislocations, whereas B-islands are completely free from lattice defects, with the exception of interfacial steps of various heights occurring at the NiSi/sub 2//Si(111) growth fronts of both island types. These steps play an essential role in the island growth. The difference in the reaction kinetics observed between A- and B-islands at 400/spl deg/C is explained in terms of different kinetic reaction barriers present at the structurally different NiSi/sub 2/Si(111) growth fronts under the A-and B-islands.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132198593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785859
H. Okabayashi, D. Grosjean, M. Komatsu, H. Mori
Both depth- and in-plane-resolved information is essential for analysis of electromigration (EM) in layered interconnect lines. We demonstrate the usefulness of a combination of in situ side-view TEM, SEM and EPMA for this purpose. We have analyzed EM in Al-2 wt%Cu bamboo-grain drift lines using these techniques. The analysis leads to the conclusions that large precipitates near the cathode end cause voiding when Ca depletes from them, and that the variation in precipitate sites may be one of the causes of the variation of voiding sites in the cathode area, which have a strong influence on the EM reliability. It was also clarified that Cu that migrated from upstream mostly accumulated at preexisting precipitates at the anode, and no new precipitate formation was observed.
{"title":"In-situ TEM studies of damage formation under electromigration in Al interconnects","authors":"H. Okabayashi, D. Grosjean, M. Komatsu, H. Mori","doi":"10.1109/ICSICT.1998.785859","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785859","url":null,"abstract":"Both depth- and in-plane-resolved information is essential for analysis of electromigration (EM) in layered interconnect lines. We demonstrate the usefulness of a combination of in situ side-view TEM, SEM and EPMA for this purpose. We have analyzed EM in Al-2 wt%Cu bamboo-grain drift lines using these techniques. The analysis leads to the conclusions that large precipitates near the cathode end cause voiding when Ca depletes from them, and that the variation in precipitate sites may be one of the causes of the variation of voiding sites in the cathode area, which have a strong influence on the EM reliability. It was also clarified that Cu that migrated from upstream mostly accumulated at preexisting precipitates at the anode, and no new precipitate formation was observed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132717362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785815
R. R. Jin
This paper will receive and report advancements in new generation CMP equipment (MIRRA(R)) development for different CMP applications in IC fabrication: SOI, silicon/polysilicon, shallow trench isolation (STI), oxide (PMD and ILD), W, Cu, Al. The impact of new generation CMP equipment on IC device fabrication and its performance is also discussed.
{"title":"New generation CMP equipment and its Impact on IC devices","authors":"R. R. Jin","doi":"10.1109/ICSICT.1998.785815","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785815","url":null,"abstract":"This paper will receive and report advancements in new generation CMP equipment (MIRRA(R)) development for different CMP applications in IC fabrication: SOI, silicon/polysilicon, shallow trench isolation (STI), oxide (PMD and ILD), W, Cu, Al. The impact of new generation CMP equipment on IC device fabrication and its performance is also discussed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132834880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785915
X. Xi, Hongmei Wang, Xing Zhang, Yangyuan Wang
A new analytical current model in the strong inversion operation region for fully depleted SOI/MOSFET with channel lengths down to deep submicrometer range is developed with only one single expression for both linear and saturation region without using a smoothing function. The convergence when employed in circuit simulators is improved. Measurements on devices of varied geometry show good agreement with model predictions.
{"title":"A new physical I-V model of deep-submicron FD SOI MOSFETs for analogue/digital circuit simulation","authors":"X. Xi, Hongmei Wang, Xing Zhang, Yangyuan Wang","doi":"10.1109/ICSICT.1998.785915","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785915","url":null,"abstract":"A new analytical current model in the strong inversion operation region for fully depleted SOI/MOSFET with channel lengths down to deep submicrometer range is developed with only one single expression for both linear and saturation region without using a smoothing function. The convergence when employed in circuit simulators is improved. Measurements on devices of varied geometry show good agreement with model predictions.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785887
G. Ru, J. Liu, X. Qu, Bingzong Li, C. Detavernier, R. Van Meirhaeghe, F. Cardon
With the continued scaling down of device features surface roughness of silicides used as contacts is a growing concern. In this work we present an atomic force microscopy (AFM) study of thin CoSi/sub 2/ films formed by solid state reaction. Four structures, Co/Si, TiN/Co/Si, Ti/Co/Si and Co/Ti/Si, were used to form the silicide. A study of the thermal stability of these films was made. The topography and surface roughness of CoSi/sub 2/ related to thermal agglomeration were investigated in detail post-annealing at 950/spl deg/C with time duration varying from 60 to 300 s was applied to the CoSi/sub 2/ formed from Co/Si reaction. The surface roughness increases with the anneal time. With a TiN capping layer or Ti interfacial layer in deposited structures the surface roughness significantly decreases compared to that from Co/Si reaction, especially in the case of high temperature annealing processes. The sheet resistance of all CoSi/sub 2/ was measured by the four point probe technique and correlated to the roughness.
{"title":"An atomic force microscopy study of thin CoSi/sub 2/ films formed by solid state reaction","authors":"G. Ru, J. Liu, X. Qu, Bingzong Li, C. Detavernier, R. Van Meirhaeghe, F. Cardon","doi":"10.1109/ICSICT.1998.785887","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785887","url":null,"abstract":"With the continued scaling down of device features surface roughness of silicides used as contacts is a growing concern. In this work we present an atomic force microscopy (AFM) study of thin CoSi/sub 2/ films formed by solid state reaction. Four structures, Co/Si, TiN/Co/Si, Ti/Co/Si and Co/Ti/Si, were used to form the silicide. A study of the thermal stability of these films was made. The topography and surface roughness of CoSi/sub 2/ related to thermal agglomeration were investigated in detail post-annealing at 950/spl deg/C with time duration varying from 60 to 300 s was applied to the CoSi/sub 2/ formed from Co/Si reaction. The surface roughness increases with the anneal time. With a TiN capping layer or Ti interfacial layer in deposited structures the surface roughness significantly decreases compared to that from Co/Si reaction, especially in the case of high temperature annealing processes. The sheet resistance of all CoSi/sub 2/ was measured by the four point probe technique and correlated to the roughness.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132441687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：