Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786077
Wenhong Li, Jinsheng Luo
In this paper, a novel analytical physical model for a thin film SOI RESURF structure is developed, based on the 2D Poisson equation, and the influence of the field SiO/sub 2/ interface charge is considered. The thin film SOI RESURF structure is analyzed using this novel model. There are two electric field peak values at the interfaces of the p/sup +/n and n/sup +/n junctions. The potential distribution is similar to a step between the p/sup +/n and n/sup +/n junctions. The field SiO/sub 2/ interface charge makes the electric field increase at the interface of the p/sup +/n junction, and reduces the electric field at the interface of the n/sup +/n junction. The analytical results agree with the simulations of MEDICI.
{"title":"A novel analytical physical model for thin film SOI RESURF structure based on 2-D Poisson equation","authors":"Wenhong Li, Jinsheng Luo","doi":"10.1109/ICSICT.1998.786077","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786077","url":null,"abstract":"In this paper, a novel analytical physical model for a thin film SOI RESURF structure is developed, based on the 2D Poisson equation, and the influence of the field SiO/sub 2/ interface charge is considered. The thin film SOI RESURF structure is analyzed using this novel model. There are two electric field peak values at the interfaces of the p/sup +/n and n/sup +/n junctions. The potential distribution is similar to a step between the p/sup +/n and n/sup +/n junctions. The field SiO/sub 2/ interface charge makes the electric field increase at the interface of the p/sup +/n junction, and reduces the electric field at the interface of the n/sup +/n junction. The analytical results agree with the simulations of MEDICI.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125881534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786138
Deyi Kong, Y. Li, Tongli Wei, Weidong Nie, W. Qian
In this paper, we have presented quantitative expressions of the collector space-charge-region (SCR) width of SiGe base HBTs with a lowly doped punch-through collector. Calculated results show a discontinuity occurs at the critical point between no punch-through and punch-through. The influence of the discontinuity on base and frequency performance has been discussed, Conclusions from our work may be also applicable to Si-BJTs.
{"title":"The influence of punch-through in lowly doped collector on base for npn SiGe base HBTs with high f/sub T/","authors":"Deyi Kong, Y. Li, Tongli Wei, Weidong Nie, W. Qian","doi":"10.1109/ICSICT.1998.786138","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786138","url":null,"abstract":"In this paper, we have presented quantitative expressions of the collector space-charge-region (SCR) width of SiGe base HBTs with a lowly doped punch-through collector. Calculated results show a discontinuity occurs at the critical point between no punch-through and punch-through. The influence of the discontinuity on base and frequency performance has been discussed, Conclusions from our work may be also applicable to Si-BJTs.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785913
Li-Fu Chang, Y. Hsu, M. Chi
A new cell structure for minimizing bit-line coupling noise in DRAM with stack capacitor is proposed in this paper. The node capacitors are fabricated in between bit-lines, so that the bit-line to bit-line capacitance coupling is blocked by the node capacitor and is shielded by the plate. This scheme is referred to as Capacitor-Equiplanar-to-Bitline (CEB). In this way, as 3D simulation shows, the bit-line coupling noise can be almost eliminated to <1% of total bit-line capacitance. The SPICE simulation shows /spl sim/3 ns faster bit-line signal sensing in 0.25 /spl mu/m 64 Mb CMOS DRAM. The CEB scheme also leads to a smaller topology and a simpler fabrication process.
{"title":"A new DRAM cell structure with Capacitor-Equiplanar-to-Bitline (CEB) for bitline coupling noise elimination","authors":"Li-Fu Chang, Y. Hsu, M. Chi","doi":"10.1109/ICSICT.1998.785913","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785913","url":null,"abstract":"A new cell structure for minimizing bit-line coupling noise in DRAM with stack capacitor is proposed in this paper. The node capacitors are fabricated in between bit-lines, so that the bit-line to bit-line capacitance coupling is blocked by the node capacitor and is shielded by the plate. This scheme is referred to as Capacitor-Equiplanar-to-Bitline (CEB). In this way, as 3D simulation shows, the bit-line coupling noise can be almost eliminated to <1% of total bit-line capacitance. The SPICE simulation shows /spl sim/3 ns faster bit-line signal sensing in 0.25 /spl mu/m 64 Mb CMOS DRAM. The CEB scheme also leads to a smaller topology and a simpler fabrication process.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128268602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785933
A. Wang, C. Tsay
A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology.
{"title":"A new design methodology using simulation for on-chip ESD protection designs for integrated circuits","authors":"A. Wang, C. Tsay","doi":"10.1109/ICSICT.1998.785933","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785933","url":null,"abstract":"A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"229 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120881862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785929
Liao Xiaoyong, Ji Lijiu
A new Quadru-Tree algorithm, by which the transition probabilities of circuit nodes, including all internal and output nodes, can be exactly worked out, and its program implementation are presented in this paper. As evidence of its accuracy and efficiency, the result of one example run in the prototype is reported, as well.
{"title":"Quadru-tree algorithm for transition probability in CMOS IC power estimation","authors":"Liao Xiaoyong, Ji Lijiu","doi":"10.1109/ICSICT.1998.785929","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785929","url":null,"abstract":"A new Quadru-Tree algorithm, by which the transition probabilities of circuit nodes, including all internal and output nodes, can be exactly worked out, and its program implementation are presented in this paper. As evidence of its accuracy and efficiency, the result of one example run in the prototype is reported, as well.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785956
Liang Ruigang, Wang Jian-nong, W. Yuqi, Dong Wenfu, Wu Dexin
A novel fabrication process, based on selective wet etching and GaAs air-bridge was developed to produce AlAs/GaAs, AlAs/InAs/GaAs quantum dots double barrier quantum well sub-micron resonant tunneling diodes (RTD), and the peak to valley current ratio could be over 20. A new model of multilevel logic SRAM with RTDs was proposed.
{"title":"Quantum resonant tunneling effect and multi-value logic memory","authors":"Liang Ruigang, Wang Jian-nong, W. Yuqi, Dong Wenfu, Wu Dexin","doi":"10.1109/ICSICT.1998.785956","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785956","url":null,"abstract":"A novel fabrication process, based on selective wet etching and GaAs air-bridge was developed to produce AlAs/GaAs, AlAs/InAs/GaAs quantum dots double barrier quantum well sub-micron resonant tunneling diodes (RTD), and the peak to valley current ratio could be over 20. A new model of multilevel logic SRAM with RTDs was proposed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124057588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785902
Bingxin Li, Lihong Jia, H. Tenhunen
In this paper a comprehensive method of analog modeling and simulation is given, in which models at different hierarchy levels are used in an optimized combination. To meet the conflicting requirements of simulation efficiency and accuracy, analog HDL is used as the bridge between high level behavioral models and low level transistor models. In this way both requirements are satisfied. A 5th order oversampling sigma-delta modulator is employed to demonstrate the design and modeling practice.
{"title":"Optimization of analog modeling and simulation","authors":"Bingxin Li, Lihong Jia, H. Tenhunen","doi":"10.1109/ICSICT.1998.785902","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785902","url":null,"abstract":"In this paper a comprehensive method of analog modeling and simulation is given, in which models at different hierarchy levels are used in an optimized combination. To meet the conflicting requirements of simulation efficiency and accuracy, analog HDL is used as the bridge between high level behavioral models and low level transistor models. In this way both requirements are satisfied. A 5th order oversampling sigma-delta modulator is employed to demonstrate the design and modeling practice.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785965
J. Chengzhou, Liao Huailin, Li Guohui
A punch-through type AlGaAs-GaAs heterojunction phototransistor with a guarding modulation electrode is analyzed by a numerical procedure. The augmented drift-diffusion model is regarded as a suitable model to describe the device, and the coupled equations are solved by the successive line overrelaxation method. The distribution of carriers and electric potential, transportation of non-equilibrium carriers and frequency characteristics are computed systematically. Preliminary results are presented and discussed briefly.
{"title":"A numerical analysis for heterojunction phototransistor","authors":"J. Chengzhou, Liao Huailin, Li Guohui","doi":"10.1109/ICSICT.1998.785965","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785965","url":null,"abstract":"A punch-through type AlGaAs-GaAs heterojunction phototransistor with a guarding modulation electrode is analyzed by a numerical procedure. The augmented drift-diffusion model is regarded as a suitable model to describe the device, and the coupled equations are solved by the successive line overrelaxation method. The distribution of carriers and electric potential, transportation of non-equilibrium carriers and frequency characteristics are computed systematically. Preliminary results are presented and discussed briefly.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121489480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785852
C. Ting, D. Papapanayiotou, Mei Zhu
Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.
{"title":"Electro-chemical deposition technology for ULSI multilevel copper interconnects","authors":"C. Ting, D. Papapanayiotou, Mei Zhu","doi":"10.1109/ICSICT.1998.785852","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785852","url":null,"abstract":"Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127573759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785914
Xiaoyan Liu, Jinfeng Kang, R. Han
Based on the studies of the two dimensional nature of electrons in inversion layer of the ultra thin gate oxide MOSFET model to describe tunneling effect and inversion layer quantization effect on deep submicron MOSFET's threshold voltage is developed. By using of this model the influence of tunneling effect and the inversion layer quantization effect on the MOSFET threshold voltage can be estimated.
{"title":"The influence of tunneling effect and inversion layer quantization effect on deep submicron MOSFET","authors":"Xiaoyan Liu, Jinfeng Kang, R. Han","doi":"10.1109/ICSICT.1998.785914","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785914","url":null,"abstract":"Based on the studies of the two dimensional nature of electrons in inversion layer of the ultra thin gate oxide MOSFET model to describe tunneling effect and inversion layer quantization effect on deep submicron MOSFET's threshold voltage is developed. By using of this model the influence of tunneling effect and the inversion layer quantization effect on the MOSFET threshold voltage can be estimated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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