Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785863
T. Oku, H. Mori, M. Murakami
Thermally stable, thin W/sub 2/N, TaN, and TaC diffusion barrier layers between Cu and Si were developed by a radio-frequency sputtering method. The W/sub 2/N(8 nm), TaN(8 nm) and TaC(5 nm) barrier layers were found to prevent Cu diffusion to Si after annealing at 600, 700, and 600/spl deg/C for 30 min, respectively. From the microstructural and diffusional analyses, the Cu diffusion mechanism through the barrier layers was explained by grain boundary and lattice diffusion.
{"title":"Diffusion barriers for copper interconnects","authors":"T. Oku, H. Mori, M. Murakami","doi":"10.1109/ICSICT.1998.785863","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785863","url":null,"abstract":"Thermally stable, thin W/sub 2/N, TaN, and TaC diffusion barrier layers between Cu and Si were developed by a radio-frequency sputtering method. The W/sub 2/N(8 nm), TaN(8 nm) and TaC(5 nm) barrier layers were found to prevent Cu diffusion to Si after annealing at 600, 700, and 600/spl deg/C for 30 min, respectively. From the microstructural and diffusional analyses, the Cu diffusion mechanism through the barrier layers was explained by grain boundary and lattice diffusion.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129002425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786546
Shizhi Wang
In this paper an overview of both new and existing spin-on dielectric materials used in the manufacture of integrated circuit devices will be presented. Present day integrated circuit devices have 2 to 3 levels of metal interconnects, and future devices may contain upwards of 6 metal levels. This evolving structural complexity necessitates the development of low dielectric constant insulators keeping the RC time constant of the metal-insulator structure to a minimum. This meets the needs of today's high clock speed devices. In addition, spin-on dielectric films must be capable of withstanding temperatures in excess of 400/spl deg/C, resistant to water absorption, have good adhesion to underlying films, generate crack free films ranging in thickness from 0.1 to 1 /spl mu/m, and possess excellent mechanical and electrical strength. Spin-on dielectric films can be classified into four families: silicate, siloxane, organic, and nanoporous silicate. Silicates are silicon dioxide films formed by the cross-linking reaction of hydroxylated-silicate oligomers. Siloxanes are silicate compounds that are either partially or fully methylated. The addition of the methyl group lowers the film stress, lowers the dielectric constant by lowering the film density, and at the same time improves the gap fill and planarization of these films. Hydrogen, and have hydrogenmethyl siloxane combinations are under evaluation as well. Organic dielectrics are currently receiving a lot of attention from semiconductor device manufacturers and have-the benefit that thick, crack free, films can be formed. Organic polymers, on the other hand, are limited by their thermal stability. Nanoporous silicates overcome this issue by retaining a thermally stable silicon-oxygen backbone but make use of a modified xerogel technology to impart a nanoporous film structure resulting in ultra-low dielectric constant films.
{"title":"Spin-on dielectric films-a general overview","authors":"Shizhi Wang","doi":"10.1109/ICSICT.1998.786546","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786546","url":null,"abstract":"In this paper an overview of both new and existing spin-on dielectric materials used in the manufacture of integrated circuit devices will be presented. Present day integrated circuit devices have 2 to 3 levels of metal interconnects, and future devices may contain upwards of 6 metal levels. This evolving structural complexity necessitates the development of low dielectric constant insulators keeping the RC time constant of the metal-insulator structure to a minimum. This meets the needs of today's high clock speed devices. In addition, spin-on dielectric films must be capable of withstanding temperatures in excess of 400/spl deg/C, resistant to water absorption, have good adhesion to underlying films, generate crack free films ranging in thickness from 0.1 to 1 /spl mu/m, and possess excellent mechanical and electrical strength. Spin-on dielectric films can be classified into four families: silicate, siloxane, organic, and nanoporous silicate. Silicates are silicon dioxide films formed by the cross-linking reaction of hydroxylated-silicate oligomers. Siloxanes are silicate compounds that are either partially or fully methylated. The addition of the methyl group lowers the film stress, lowers the dielectric constant by lowering the film density, and at the same time improves the gap fill and planarization of these films. Hydrogen, and have hydrogenmethyl siloxane combinations are under evaluation as well. Organic dielectrics are currently receiving a lot of attention from semiconductor device manufacturers and have-the benefit that thick, crack free, films can be formed. Organic polymers, on the other hand, are limited by their thermal stability. Nanoporous silicates overcome this issue by retaining a thermally stable silicon-oxygen backbone but make use of a modified xerogel technology to impart a nanoporous film structure resulting in ultra-low dielectric constant films.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124009024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786495
Liu Litian, L. Zhijian
This article introduces MEMS development in the Institute of Microelectronic at Tsinghua University. Several MEMS devices: smart sensors, micromotors, micropump and microphone are described.
{"title":"MEMS developments in Tsinghua University","authors":"Liu Litian, L. Zhijian","doi":"10.1109/ICSICT.1998.786495","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786495","url":null,"abstract":"This article introduces MEMS development in the Institute of Microelectronic at Tsinghua University. Several MEMS devices: smart sensors, micromotors, micropump and microphone are described.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"36 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785768
T. Ning
The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 /spl mu/m is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement.
{"title":"CMOS performance and density trends as we approach 0.1 /spl mu/m","authors":"T. Ning","doi":"10.1109/ICSICT.1998.785768","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785768","url":null,"abstract":"The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 /spl mu/m is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"307 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124368152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786136
Zhang Wan-rong, Li Zhi-guo, Luo Jin-sheng, Chang Yao-Hai, Chen Jian-xin, Shen Guang-di
In this paper, the carrier freeze-out in strained p-Si/sub 1-x/Ge/sub x/ layers grown on [001] substrates is studied analytically. It is found that as the Ge fraction increases, the valence effective density of states (N/sub V/)/sub SiGe//(N/sub V/)Si normalized by that in Si decreases. Furthermore, as the temperature becomes lower, the decrease in (N/sub V/)/sub SiGe//(N/sub V/)Si becomes more rapid. It is also show that as the Ge fraction increases, although it has little effect on the ionized doping concentration at room temperature, the ionized doping concentration increases at low temperatures compared with that in Si. This implies that carrier freeze-out is mitigated at low temperatures, which can have a beneficial effect on the operation of Si/sub -x/Ge/sub x/-based devices at low temperatures.
{"title":"Carrier freeze-out in strained p-Si/sub 1-x/Ge/sub x/ layers","authors":"Zhang Wan-rong, Li Zhi-guo, Luo Jin-sheng, Chang Yao-Hai, Chen Jian-xin, Shen Guang-di","doi":"10.1109/ICSICT.1998.786136","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786136","url":null,"abstract":"In this paper, the carrier freeze-out in strained p-Si/sub 1-x/Ge/sub x/ layers grown on [001] substrates is studied analytically. It is found that as the Ge fraction increases, the valence effective density of states (N/sub V/)/sub SiGe//(N/sub V/)Si normalized by that in Si decreases. Furthermore, as the temperature becomes lower, the decrease in (N/sub V/)/sub SiGe//(N/sub V/)Si becomes more rapid. It is also show that as the Ge fraction increases, although it has little effect on the ionized doping concentration at room temperature, the ionized doping concentration increases at low temperatures compared with that in Si. This implies that carrier freeze-out is mitigated at low temperatures, which can have a beneficial effect on the operation of Si/sub -x/Ge/sub x/-based devices at low temperatures.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124161172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785981
Xiukun He, Q. Ru, Li Ding
In this paper we have investigated the characteristics of undoped SI-GaAs crystals and carried out related experiments concerning device processes. We have analyzed the relationship between the material and device properties and studied the effect of the various parameters and their distribution in the SI-GaAs crystal on the device characteristics.
{"title":"The influence of SI-GaAs crystal property on device characteristic","authors":"Xiukun He, Q. Ru, Li Ding","doi":"10.1109/ICSICT.1998.785981","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785981","url":null,"abstract":"In this paper we have investigated the characteristics of undoped SI-GaAs crystals and carried out related experiments concerning device processes. We have analyzed the relationship between the material and device properties and studied the effect of the various parameters and their distribution in the SI-GaAs crystal on the device characteristics.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128127550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785958
J. Ao, Shiyong Liu, Q. Zeng, Yonglin Zhao, K. Cai, Xian-jie Li, Xhixian Jiao, Jianjun Gao, Chun-Guang Liang
The design, fabrication and characteristics of a AlGaAs/InGaAs PHEMT monolithic transimpedance preamplifier is described. The PHEMT material used here is based on /spl delta/-doped carrier supplying layer and GaAs/AlGaAs superlattice buffer. The transconductance and output conductance of a 1 /spl mu/m-gate PHEMT is 250 mS/mm and 8mS/mm respectively with threshold voltage of -1.2 v, the maximum saturation current density is 235 mS/mm. On-wafer network analysis with HP8510 network analyzer shows its cut-off frequency of 21 GHz and maximum oscillation frequency of 40 GHz. Transimpedance preamplifier its measured maximum transimpedance gain of 51.4 dB/spl Omega/ with -3 dB bandwidth no less than 5.05 GHz. The input equivalent-noise current density is 13 PA//spl radic/Hz.
{"title":"AlGaAs/InGaAs PHEMT preamplifier for optical communication systems","authors":"J. Ao, Shiyong Liu, Q. Zeng, Yonglin Zhao, K. Cai, Xian-jie Li, Xhixian Jiao, Jianjun Gao, Chun-Guang Liang","doi":"10.1109/ICSICT.1998.785958","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785958","url":null,"abstract":"The design, fabrication and characteristics of a AlGaAs/InGaAs PHEMT monolithic transimpedance preamplifier is described. The PHEMT material used here is based on /spl delta/-doped carrier supplying layer and GaAs/AlGaAs superlattice buffer. The transconductance and output conductance of a 1 /spl mu/m-gate PHEMT is 250 mS/mm and 8mS/mm respectively with threshold voltage of -1.2 v, the maximum saturation current density is 235 mS/mm. On-wafer network analysis with HP8510 network analyzer shows its cut-off frequency of 21 GHz and maximum oscillation frequency of 40 GHz. Transimpedance preamplifier its measured maximum transimpedance gain of 51.4 dB/spl Omega/ with -3 dB bandwidth no less than 5.05 GHz. The input equivalent-noise current density is 13 PA//spl radic/Hz.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125457393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785939
Wang Hua, Lu Zong Li, Zhang Jian Zhong
The very large scale integration used for the design and fabrication of modern microelectronics devices should have good suitability for temperature. For example the space grade IC should withstand hard temperature shock from +125/spl deg/C to -55/spl deg/C or reverse in 5 mins. For failure analysis techniques, it is necessary to investigate the performance of an IC under different temperatures. Therefore the demand for new test equipment arises, which can cool or heat ICs to make the die temperature of the IC change from high to low or from low to high. There are some mechanical refrigeration systems that you can choose, but it is difficult to control the temperature of the IC, and this kind of apparatus often has problems in the summer. We have developed a new equipment with working temperatures in the range of -55/spl deg/C/spl sim/+125/spl deg/C, it uses a thermoelectric cooler as cooling or heating units. We can easily control the cold plate temperature by means of regulating the input voltage. In this equipment, the cold side can be smoothly regulated, stabilized and indicated on the display. This paper introduces the design of the control system and multistage TEM cooling system, the cooling power of which is 3 W, when the temperature of cold side is -55/spl deg/C and hot side is 30/spl deg/C.
{"title":"The new equipment for IC testing","authors":"Wang Hua, Lu Zong Li, Zhang Jian Zhong","doi":"10.1109/ICSICT.1998.785939","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785939","url":null,"abstract":"The very large scale integration used for the design and fabrication of modern microelectronics devices should have good suitability for temperature. For example the space grade IC should withstand hard temperature shock from +125/spl deg/C to -55/spl deg/C or reverse in 5 mins. For failure analysis techniques, it is necessary to investigate the performance of an IC under different temperatures. Therefore the demand for new test equipment arises, which can cool or heat ICs to make the die temperature of the IC change from high to low or from low to high. There are some mechanical refrigeration systems that you can choose, but it is difficult to control the temperature of the IC, and this kind of apparatus often has problems in the summer. We have developed a new equipment with working temperatures in the range of -55/spl deg/C/spl sim/+125/spl deg/C, it uses a thermoelectric cooler as cooling or heating units. We can easily control the cold plate temperature by means of regulating the input voltage. In this equipment, the cold side can be smoothly regulated, stabilized and indicated on the display. This paper introduces the design of the control system and multistage TEM cooling system, the cooling power of which is 3 W, when the temperature of cold side is -55/spl deg/C and hot side is 30/spl deg/C.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125665956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785837
Jiang Yanfeng, L. Siyuan, Li Hairong, Meng Xionghui
For BSIT, it is well-known that the ideal relation between the drain current and the drain voltage with respect to the source is pentode-like, the saturated property. But the result from practical measurements shows I/sub D/ increases slightly with rising V/sub D/, just like the phenomenon observed in a BJT, which is affected by "base width modulation". The authors deduce that the main cause is "gate-biasing effect". In this article, the effect is discussed in detail.
{"title":"Influence of \"gate-biasing effect\" on BSIT's saturated property","authors":"Jiang Yanfeng, L. Siyuan, Li Hairong, Meng Xionghui","doi":"10.1109/ICSICT.1998.785837","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785837","url":null,"abstract":"For BSIT, it is well-known that the ideal relation between the drain current and the drain voltage with respect to the source is pentode-like, the saturated property. But the result from practical measurements shows I/sub D/ increases slightly with rising V/sub D/, just like the phenomenon observed in a BJT, which is affected by \"base width modulation\". The authors deduce that the main cause is \"gate-biasing effect\". In this article, the effect is discussed in detail.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785797
Zhang Zheng-Xuam, Lue Jin-Sheng, Yuan Ron-Feng, Hei Bao-ping, Jiang Jing-Ho
In this paper the radiation response of two types of CMOS devices exposed to /sup 60/Co is studied. The two types of CMOS devices were denoted as hardened and unhardened, respectively. Using MOSFET I-V characteristics, threshold-voltage shifts dependence on the radiation dose, voltage shifts due to radiation-induced interface traps and oxide traps dependence on the radiation dose and the density of radiation-induced interface traps dependence on the radiation dose, were analysed under two different dose rates. The dependence of a CMOS inverter's transfer-voltage shifts on radiation dose was analysed also.
{"title":"The total dose effect on two types of CMOS devices","authors":"Zhang Zheng-Xuam, Lue Jin-Sheng, Yuan Ron-Feng, Hei Bao-ping, Jiang Jing-Ho","doi":"10.1109/ICSICT.1998.785797","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785797","url":null,"abstract":"In this paper the radiation response of two types of CMOS devices exposed to /sup 60/Co is studied. The two types of CMOS devices were denoted as hardened and unhardened, respectively. Using MOSFET I-V characteristics, threshold-voltage shifts dependence on the radiation dose, voltage shifts due to radiation-induced interface traps and oxide traps dependence on the radiation dose and the density of radiation-induced interface traps dependence on the radiation dose, were analysed under two different dose rates. The dependence of a CMOS inverter's transfer-voltage shifts on radiation dose was analysed also.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127931499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：