Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785864
C. Hu, R. Rosenberg
Summary form only given. The electromigration in 0.15 /spl mu/m to 10 /spl mu/m wide and 0.3 /spl mu/m thick Cu lines deposited by physical vapor deposition has been investigated using both resistance and edge displacement techniques in the sample temperature range 225/spl deg/C-405/spl deg/C. For wide polycrystalline lines (>1 /spl mu/m), the dominant diffusion mechanism is a mixture of grain boundary and surface diffusion, while in narrow lines (< 1 /spl mu/m) the dominant mechanism is surface transport. The electromigration lifetime of fine Cu lines is estimated.
{"title":"Electromigration mechanisms in Cu lines","authors":"C. Hu, R. Rosenberg","doi":"10.1109/ICSICT.1998.785864","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785864","url":null,"abstract":"Summary form only given. The electromigration in 0.15 /spl mu/m to 10 /spl mu/m wide and 0.3 /spl mu/m thick Cu lines deposited by physical vapor deposition has been investigated using both resistance and edge displacement techniques in the sample temperature range 225/spl deg/C-405/spl deg/C. For wide polycrystalline lines (>1 /spl mu/m), the dominant diffusion mechanism is a mixture of grain boundary and surface diffusion, while in narrow lines (< 1 /spl mu/m) the dominant mechanism is surface transport. The electromigration lifetime of fine Cu lines is estimated.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121599848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785932
Huang Lingyi, Zhu Uajiang, Qiu Yuling, Ye Qing, Chen Chaoshu, Chen Xiaodong, Su Zhenjiang, Liu Zhao, Wang Yuhui, Chen Xia
This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 /spl mu/m CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the "variable parameter" cell and "buried" cell were used to correct a timing violation.
{"title":"A high speed base library and macro library design methodology for submicron and deep submicron ULSI","authors":"Huang Lingyi, Zhu Uajiang, Qiu Yuling, Ye Qing, Chen Chaoshu, Chen Xiaodong, Su Zhenjiang, Liu Zhao, Wang Yuhui, Chen Xia","doi":"10.1109/ICSICT.1998.785932","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785932","url":null,"abstract":"This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 /spl mu/m CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the \"variable parameter\" cell and \"buried\" cell were used to correct a timing violation.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785977
Xinghong Zhang, G. Xia, Yuansen Xu, Yufen Yang, Zhanguo Wang
The influence of interface states on the characteristics of AlGaAs/GaAs high electron mobility transistor (HEMT) direct current (DC) output has been quantitatively analyzed in the first time using an analytical model of HEMT DC output. Considering the action of the interface states in a AlGaAs/GaAs heterostructure, we have analyzed in detail the effect of interface states on I-V characteristics and transconductance of HEMT. Our calculated results show that the control capability of the gate voltage on the channel current reduces with increasing density of interface states, the transconductance of device decreases. Hence, the existence of the interface states degrades the performance of HEMT.
{"title":"The influence of interface states on the characteristics of HEMT DC output","authors":"Xinghong Zhang, G. Xia, Yuansen Xu, Yufen Yang, Zhanguo Wang","doi":"10.1109/ICSICT.1998.785977","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785977","url":null,"abstract":"The influence of interface states on the characteristics of AlGaAs/GaAs high electron mobility transistor (HEMT) direct current (DC) output has been quantitatively analyzed in the first time using an analytical model of HEMT DC output. Considering the action of the interface states in a AlGaAs/GaAs heterostructure, we have analyzed in detail the effect of interface states on I-V characteristics and transconductance of HEMT. Our calculated results show that the control capability of the gate voltage on the channel current reduces with increasing density of interface states, the transconductance of device decreases. Hence, the existence of the interface states degrades the performance of HEMT.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132541864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786092
Bing Yang, Ru Huang, Xing Zhang, Yangyuan Wang
For silicon-on-insulator (SOI) technology compared with the bulk circuit, an obvious improvement in power consumption and speed is always observed for the corresponding SOI circuit. Due to their electrical properties, SOI devices may be a solution for low-power application. But FD devices and PD devices have different properties. Detailed analysis and comparison between the different SOI devices operating at low voltage is needed. In this paper, Medici 4.0 is used to study FD and FD devices. Different device parameter influence on devices and circuits behaviour is described.
{"title":"Channel design of silicon-on-insulator (SOI) MOSFET for low-voltage low-power application","authors":"Bing Yang, Ru Huang, Xing Zhang, Yangyuan Wang","doi":"10.1109/ICSICT.1998.786092","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786092","url":null,"abstract":"For silicon-on-insulator (SOI) technology compared with the bulk circuit, an obvious improvement in power consumption and speed is always observed for the corresponding SOI circuit. Due to their electrical properties, SOI devices may be a solution for low-power application. But FD devices and PD devices have different properties. Detailed analysis and comparison between the different SOI devices operating at low voltage is needed. In this paper, Medici 4.0 is used to study FD and FD devices. Different device parameter influence on devices and circuits behaviour is described.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785847
M. Chi
Active pixel sensors (APS) based on CMOS technology challenges CCD image sensors in many aspects for high performance imaging systems, such as, low-voltage operation, low-power consumption, random image access, highly integrated functionality, high resolution, fast readout, CMOS compatible fabrication and low cost. In this paper various active CMOS pixel designs and circuit components for high performance imaging systems are reviewed. The emerging CMOS technologies for integrating all these components into camera-on-a-chip are reviewed.
{"title":"Technologies for high performance CMOS active pixel imaging system-on-a-chip","authors":"M. Chi","doi":"10.1109/ICSICT.1998.785847","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785847","url":null,"abstract":"Active pixel sensors (APS) based on CMOS technology challenges CCD image sensors in many aspects for high performance imaging systems, such as, low-voltage operation, low-power consumption, random image access, highly integrated functionality, high resolution, fast readout, CMOS compatible fabrication and low cost. In this paper various active CMOS pixel designs and circuit components for high performance imaging systems are reviewed. The emerging CMOS technologies for integrating all these components into camera-on-a-chip are reviewed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130685720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786201
Huang-Chung Cheng, Chun‐Yao Huang, Jing-Wei Lin, J. Kung
In this paper, hydrogenated amorphous silicon and polycrystalline silicon thin film transistors have been stressed with various conditions including DC and AC. Charge trapping and defect state creation are the two mechanisms to degrade the transfer characteristics of the TFTs. For a-Si:H TFTs, the charge trapping occurs at a high silicon content in silicon nitride (SiN/sub x/) gate dielectrics or performs at high gate electrical field. Defect state creation dominates at low hydrogen concentration in a-Si:H. At the performance of AC signal, the degradation of transfer curves is associated with bias, frequency, and duty cycle. The characteristics of a-Si:H TFTs shift more with increasing bias voltage and duty cycle. For the frequency effect, the transfer characteristics of a-Si:H TFTs decrease with increasing AC frequency under negative AC signal stress, however, they are independent of the frequency under positive AC signal stress.
{"title":"The reliability of amorphous silicon thin film transistors for LCD under DC and AC stresses","authors":"Huang-Chung Cheng, Chun‐Yao Huang, Jing-Wei Lin, J. Kung","doi":"10.1109/ICSICT.1998.786201","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786201","url":null,"abstract":"In this paper, hydrogenated amorphous silicon and polycrystalline silicon thin film transistors have been stressed with various conditions including DC and AC. Charge trapping and defect state creation are the two mechanisms to degrade the transfer characteristics of the TFTs. For a-Si:H TFTs, the charge trapping occurs at a high silicon content in silicon nitride (SiN/sub x/) gate dielectrics or performs at high gate electrical field. Defect state creation dominates at low hydrogen concentration in a-Si:H. At the performance of AC signal, the degradation of transfer curves is associated with bias, frequency, and duty cycle. The characteristics of a-Si:H TFTs shift more with increasing bias voltage and duty cycle. For the frequency effect, the transfer characteristics of a-Si:H TFTs decrease with increasing AC frequency under negative AC signal stress, however, they are independent of the frequency under positive AC signal stress.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124287939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785800
P. Chu
Microcavities or bubbles formed by hydrogen and helium plasma immersion ion implantation (PIII) possess intriguing properties. For example, they emit light similar to porous silicon, but because they are buried, the optical properties are not affected by surface conditions such as those encountered by conventional porous silicon materials. These bubbles also form excellent internal gettering sites for metallic impurities and are stable even at high temperature. Last but not least, the ion-cut/bonding technology utilizing the mechanical stress created by these microcavities to achieve thin film transfer is used to fabricate silicon-on-insulator (SOI).
{"title":"Microcavity engineering using plasma immersion ion implantation","authors":"P. Chu","doi":"10.1109/ICSICT.1998.785800","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785800","url":null,"abstract":"Microcavities or bubbles formed by hydrogen and helium plasma immersion ion implantation (PIII) possess intriguing properties. For example, they emit light similar to porous silicon, but because they are buried, the optical properties are not affected by surface conditions such as those encountered by conventional porous silicon materials. These bubbles also form excellent internal gettering sites for metallic impurities and are stable even at high temperature. Last but not least, the ion-cut/bonding technology utilizing the mechanical stress created by these microcavities to achieve thin film transfer is used to fabricate silicon-on-insulator (SOI).","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124818647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.786121
T. Hara
This paper reviews the delamination of thin Si layer in H/sup +/ implanted Si layers. Layer properties of the device Si layer were measured by minority carrier lifetime technique.
本文综述了H/sup +/注入硅层中薄硅层的分层现象。采用少数载流子寿命技术测量了器件硅层的层性。
{"title":"Delamination of thin Si layer in the H/sup +/ implanted Si for the manufacture of SOI Si wafer-fundamental phenomena and the properties of the delaminated Si layers","authors":"T. Hara","doi":"10.1109/ICSICT.1998.786121","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786121","url":null,"abstract":"This paper reviews the delamination of thin Si layer in H/sup +/ implanted Si layers. Layer properties of the device Si layer were measured by minority carrier lifetime technique.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128623714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785817
Lixin Zhao, G. Shen, G. Gao, Chen Xu, Jinyu Du, Deshu Zou, Jianxing Chen
Ni-Cr thin films with different thicknesses have been fabricated on the dielectric substrate silicon dioxide (SiO/sub 2/) by using magnetron sputtering and vacuum evaporation and annealed at different temperatures. The sheet resistance and the strip line microwave impedance of the Ni-Cr thin film are measured. The results show that they are influenced strongly by the thickness and the annealing temperature. These problems are analyzed in detail including the effects of the carrier tunnel transport, the oxidation, the condensation and the stabilization in the thin film.
{"title":"The resistance characteristics of the Ni-Cr thin films and their influence on the integrated circuits","authors":"Lixin Zhao, G. Shen, G. Gao, Chen Xu, Jinyu Du, Deshu Zou, Jianxing Chen","doi":"10.1109/ICSICT.1998.785817","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785817","url":null,"abstract":"Ni-Cr thin films with different thicknesses have been fabricated on the dielectric substrate silicon dioxide (SiO/sub 2/) by using magnetron sputtering and vacuum evaporation and annealed at different temperatures. The sheet resistance and the strip line microwave impedance of the Ni-Cr thin film are measured. The results show that they are influenced strongly by the thickness and the annealing temperature. These problems are analyzed in detail including the effects of the carrier tunnel transport, the oxidation, the condensation and the stabilization in the thin film.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"94 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127286401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-21DOI: 10.1109/ICSICT.1998.785808
Dacleng Zhang, J. Wan, G. Yan, Ting Li, D. Tian, Ke-Qiang Deng
Bulk silicon micromachining is becoming a hot topic in MEMS technology. This is mainly attributed to the breakthrough of high aspect ratio silicon etching. This article provides a new method of high aspect ratio silicon etching using fluorine based chemistries, SF/sub 6/ and C/sub 4/F/sub 8/, in an ICP system with a function of processing gases switching. The experiments demonstrate that the process results can meet most demands in bulk silicon micromachining processes. Two examples of a dry etching release process and fabrication of micro-silicon model are given to show the application of this technique.
{"title":"High aspect ratio Si etching technique and application","authors":"Dacleng Zhang, J. Wan, G. Yan, Ting Li, D. Tian, Ke-Qiang Deng","doi":"10.1109/ICSICT.1998.785808","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785808","url":null,"abstract":"Bulk silicon micromachining is becoming a hot topic in MEMS technology. This is mainly attributed to the breakthrough of high aspect ratio silicon etching. This article provides a new method of high aspect ratio silicon etching using fluorine based chemistries, SF/sub 6/ and C/sub 4/F/sub 8/, in an ICP system with a function of processing gases switching. The experiments demonstrate that the process results can meet most demands in bulk silicon micromachining processes. Two examples of a dry etching release process and fabrication of micro-silicon model are given to show the application of this technique.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130615711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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