Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00075
W. Lai
A multi-band low-pass sigma-delta ($Sigma Delta$) modulator with cascaded integrators and voltage-controlled oscillator with divider are presented for phase locked loop controller. The proposed prototype of phase locked loop was implemented in tsmc 0.18 $mu$m CMOS process. Another feature is that only one set loop filter is designed to promote multi-band by auto-switching capacitors with quantum algorithm from phase frequency detector to achieve a multi-band solution. Experimental have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for low power multi-band phase locked loop sensor control applications.
提出了一种带级联积分器的多频带低通sigma-delta ($Sigma Delta$)调制器和带分频器的压控振荡器作为锁相环控制器。提出的锁相环原型在tsmc 0.18 $mu$ m CMOS工艺中实现。另一个特点是只设计了一个固定环路滤波器，通过自开关电容器与相位频率检测器的量子算法来促进多频段，从而实现多频段解决方案。实验在1/2 MHz范围内实现了42/33 dB的SNDR，分别用于低功率多频带锁相环传感器控制应用。
{"title":"Continuous-Time Sigma-Delta Modulator with Filter and Voltage-Controlled Oscillator Chip Design in Phase Locked Loop for Sensor Control","authors":"W. Lai","doi":"10.1109/iSES52644.2021.00075","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00075","url":null,"abstract":"A multi-band low-pass sigma-delta ($Sigma Delta$) modulator with cascaded integrators and voltage-controlled oscillator with divider are presented for phase locked loop controller. The proposed prototype of phase locked loop was implemented in tsmc 0.18 $mu$m CMOS process. Another feature is that only one set loop filter is designed to promote multi-band by auto-switching capacitors with quantum algorithm from phase frequency detector to achieve a multi-band solution. Experimental have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for low power multi-band phase locked loop sensor control applications.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125022987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00085
Antaryami Panigrahi, Gaurav Jyoti Dutta, Swarnav Bora, Kaushik Roy Baruah, Mukul Paul
A control centric analysis and design of the low drop out (LDO) voltage regulator is presented in this work. The design complexity involving interdependence of regulating loop in frequency domain and the performance parameters for voltage regulator is simplified for intuition by the development of signal flow graph (SFG). A model based on the SFG is developed and tested in Matlab/Simulink environment for a desired time and frequency domain specification. Time domain optimisation for a given steady state accuracy and settling is formulated based on the developed model.
{"title":"Analysis and Modelling of pMOS based Classical Low Drop Out Regulators: A Time Domain Perspective","authors":"Antaryami Panigrahi, Gaurav Jyoti Dutta, Swarnav Bora, Kaushik Roy Baruah, Mukul Paul","doi":"10.1109/iSES52644.2021.00085","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00085","url":null,"abstract":"A control centric analysis and design of the low drop out (LDO) voltage regulator is presented in this work. The design complexity involving interdependence of regulating loop in frequency domain and the performance parameters for voltage regulator is simplified for intuition by the development of signal flow graph (SFG). A model based on the SFG is developed and tested in Matlab/Simulink environment for a desired time and frequency domain specification. Time domain optimisation for a given steady state accuracy and settling is formulated based on the developed model.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123080358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00057
V. Koundinya, Madanu Karun Chand, D. Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, R. Vaddi
Analog-to-Digital Converter (ADC) design plays an important role for accurate and efficient interfacing of real-world signals for IoT platforms embedded with multiple sensors. In this paper, a Flash or direct conversion 4-bit and 5-bit ADCs are designed and implemented in 90nm CMOS. The performance of the flash ADC is evaluated against important performance metrices. The proposed 4-bit ADC achieve a power consumption of 1.41mW, SNR of 26.184dB, 3.71 ENOB and 16.19 pJ/step of FoM and 5-bit ADC achieve a power consumption of 2.921mW, SNR of 31.149dB, 4.51 ENOB and 19.12 pJ/step of FoM.
{"title":"Design and Analysis of 4-bit and 5-bit Flash ADC’s in 90nm CMOS Technology for Energy Efficient IoT Applications","authors":"V. Koundinya, Madanu Karun Chand, D. Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, R. Vaddi","doi":"10.1109/iSES52644.2021.00057","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00057","url":null,"abstract":"Analog-to-Digital Converter (ADC) design plays an important role for accurate and efficient interfacing of real-world signals for IoT platforms embedded with multiple sensors. In this paper, a Flash or direct conversion 4-bit and 5-bit ADCs are designed and implemented in 90nm CMOS. The performance of the flash ADC is evaluated against important performance metrices. The proposed 4-bit ADC achieve a power consumption of 1.41mW, SNR of 26.184dB, 3.71 ENOB and 16.19 pJ/step of FoM and 5-bit ADC achieve a power consumption of 2.921mW, SNR of 31.149dB, 4.51 ENOB and 19.12 pJ/step of FoM.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117015959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00091
Sakshi Singh, Shalini Agrawal, Tina Sahu, Debanjan Das
Pipelines are considered to be a part of the transportation sector. The pipeline industry moves various substances such as crude oil, refined petroleum products, and natural gas within thousands of miles of pipelines. There may be various reasons that can cause the failure of these pipeline systems, resulting in some serious disasters. So, it is necessary to detect the leakage of water and oil pipelines by which the accidents can be avoided and damage is minimal. This paper proposes iPipe, i.e. an intelligent water pipeline monitoring and leakage detection system that is based on an acoustic signal method to detect and locate leaks in pipelines by using a network of acoustic and GPS sensors to continuously monitor the sound in the vicinity of the pipe. The system uses signal processing to identify the frequency and characteristics of leak sound and machine learning techniques to differentiate between characteristic sound and the normal sounds in the environment near the pipe. The sensors provide information about the leak as soon as possible to the designated endpoint i.e, cloud server. All of them have different locations and IDs so that it is possible to know where the data came from. This work reduces the need for human intervention by automatically notifying about the leakage. The proposed system has the ability to detect leaks with an accuracy of 95.6%.
{"title":"iPipe: Water Pipeline Monitoring and Leakage Detection","authors":"Sakshi Singh, Shalini Agrawal, Tina Sahu, Debanjan Das","doi":"10.1109/iSES52644.2021.00091","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00091","url":null,"abstract":"Pipelines are considered to be a part of the transportation sector. The pipeline industry moves various substances such as crude oil, refined petroleum products, and natural gas within thousands of miles of pipelines. There may be various reasons that can cause the failure of these pipeline systems, resulting in some serious disasters. So, it is necessary to detect the leakage of water and oil pipelines by which the accidents can be avoided and damage is minimal. This paper proposes iPipe, i.e. an intelligent water pipeline monitoring and leakage detection system that is based on an acoustic signal method to detect and locate leaks in pipelines by using a network of acoustic and GPS sensors to continuously monitor the sound in the vicinity of the pipe. The system uses signal processing to identify the frequency and characteristics of leak sound and machine learning techniques to differentiate between characteristic sound and the normal sounds in the environment near the pipe. The sensors provide information about the leak as soon as possible to the designated endpoint i.e, cloud server. All of them have different locations and IDs so that it is possible to know where the data came from. This work reduces the need for human intervention by automatically notifying about the leakage. The proposed system has the ability to detect leaks with an accuracy of 95.6%.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132209175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00047
Anju Rajput, Tripti Dua, R. Kumawat, Avireni Srinivasulu
In the wake of stretched need for movable, light weighted and battery wielded devices, diminishing power consumption, increasing area efficiency and increasing speed of the devices are the foremost crucial factors at present. This paper includes proposals for 16T and 8T half subtractor designs and as they are contrasted with the existing 14T half subtractor design. Simulation of the proposed designs are carried out at various supply voltages i.e., 0. 6V, 0.7V and 0. 8V and in different technologies which are 45nm, 32nm and 16nm technologies which indicate that the proposed designs are technology independent as well. Comparative research communicates that the proposed designs perform better and also yield better results with regards to power dissipation and transistor count as well.
{"title":"Novel CMOS and PTL Based Half Subtractor Designs","authors":"Anju Rajput, Tripti Dua, R. Kumawat, Avireni Srinivasulu","doi":"10.1109/iSES52644.2021.00047","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00047","url":null,"abstract":"In the wake of stretched need for movable, light weighted and battery wielded devices, diminishing power consumption, increasing area efficiency and increasing speed of the devices are the foremost crucial factors at present. This paper includes proposals for 16T and 8T half subtractor designs and as they are contrasted with the existing 14T half subtractor design. Simulation of the proposed designs are carried out at various supply voltages i.e., 0. 6V, 0.7V and 0. 8V and in different technologies which are 45nm, 32nm and 16nm technologies which indicate that the proposed designs are technology independent as well. Comparative research communicates that the proposed designs perform better and also yield better results with regards to power dissipation and transistor count as well.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115798779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00054
Gonella Vijayakanthi, J. P. Mohanty, Ayass Kant Swain, K. Mahapatra
Power Side-Channel analysis recovers sensitive information not only from physical proximity to a device but also from basic knowledge of sample leaked data collection. With minimum mean squared error metric, power analysis using a deep learning test case increase confidence level of proper identification of leaked data. Comparison with state-of-the art technology in this work shows improved performance in the non-profiled SCA category of detection. The deep learning technique aids in calculating the average loss gradient values and the loss values, both being calculated by taking the traces in mathworks implementation as the training data and the MSB values of the intermediate values as the training labels to reveal the expected secret key. Moreover iterative training of some machine learning techniques with different FPGA boards implementing cryptographic designs increased the accuracy of leakage detection at an earlier stage to a better extent.
{"title":"Differential Metric based Deep Learning Methodology for Non-Profiled Side Channel Analysis","authors":"Gonella Vijayakanthi, J. P. Mohanty, Ayass Kant Swain, K. Mahapatra","doi":"10.1109/iSES52644.2021.00054","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00054","url":null,"abstract":"Power Side-Channel analysis recovers sensitive information not only from physical proximity to a device but also from basic knowledge of sample leaked data collection. With minimum mean squared error metric, power analysis using a deep learning test case increase confidence level of proper identification of leaked data. Comparison with state-of-the art technology in this work shows improved performance in the non-profiled SCA category of detection. The deep learning technique aids in calculating the average loss gradient values and the loss values, both being calculated by taking the traces in mathworks implementation as the training data and the MSB values of the intermediate values as the training labels to reveal the expected secret key. Moreover iterative training of some machine learning techniques with different FPGA boards implementing cryptographic designs increased the accuracy of leakage detection at an earlier stage to a better extent.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00088
Aayush Gupta, Daksh Thapar, Sujay Deb
The COVID-19 pandemic presents an unprecedented challenge to public health, food systems and the demand and supply chains. “Coronavirus” spreads when an infected person coughs, sneezes or talks, and droplets from their mouth are launched into the air and inhaled by people in the vicinity. Mid-2021 witnessed the production and supply of effective vaccines against Coronavirus, and around 4.5 billion vaccine doses have been utilised globally, reducing fatalities significantly. Given the Government’s plans to ease quarantine restrictions for schools, offices, and public places, Social Distancing has become even more critical than ever before. This project incorporates Computer Vision techniques using the high-performance YOLOv4 library, DSFD Face detector, Deep Learning Darknet and Pre-trained ResNet models, and RaspberryPi to create a plug-and-play extension for CCTV cameras established in public places. The system uses the frame by frame information of CCTVs to detect people and classify violations of Social Distancing norms. The device also performs real-time Face Mask Detection, and this technique is robust to varying geometries of face masks and degrees of natural illumination. In case of a detected violation of Social Distancing norms, a buzzer blares in the background. The timestamp of violation with the snapshot of the frame highlighting the associated people is sent to a database and emailed to a centralised server for further investigation.
{"title":"Smart Camera for Enforcing Social Distancing","authors":"Aayush Gupta, Daksh Thapar, Sujay Deb","doi":"10.1109/iSES52644.2021.00088","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00088","url":null,"abstract":"The COVID-19 pandemic presents an unprecedented challenge to public health, food systems and the demand and supply chains. “Coronavirus” spreads when an infected person coughs, sneezes or talks, and droplets from their mouth are launched into the air and inhaled by people in the vicinity. Mid-2021 witnessed the production and supply of effective vaccines against Coronavirus, and around 4.5 billion vaccine doses have been utilised globally, reducing fatalities significantly. Given the Government’s plans to ease quarantine restrictions for schools, offices, and public places, Social Distancing has become even more critical than ever before. This project incorporates Computer Vision techniques using the high-performance YOLOv4 library, DSFD Face detector, Deep Learning Darknet and Pre-trained ResNet models, and RaspberryPi to create a plug-and-play extension for CCTV cameras established in public places. The system uses the frame by frame information of CCTVs to detect people and classify violations of Social Distancing norms. The device also performs real-time Face Mask Detection, and this technique is robust to varying geometries of face masks and degrees of natural illumination. In case of a detected violation of Social Distancing norms, a buzzer blares in the background. The timestamp of violation with the snapshot of the frame highlighting the associated people is sent to a database and emailed to a centralised server for further investigation.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00025
Ankita Porwal, Chitrakant Sahu, C. Periasamy
In this paper; a p-type double gate junctionless field effect transistor (DG-JLFET) based on Silicon (Si), germanium(Ge), and silicon-germanium $left(S i_{0.7} mathrm{Ge}_{0.3}right)$ are investigated for analog/RF application. This paper aims to improve the performance of the DG-JLFET for analog and high-speed digital applications based on Moores law by introducing Ge and SiGe as channel materials and compare with conventional Si-based DG-JLFET. The electrical properties like carrier mobility and saturation voltage can be modulated by adjusting the mole fraction in compound semiconductor materials like SiGe. The optimized values of mobility and saturation voltage of SiGe have for their applicability in junctionless transistors has been found at $mathrm{S} S i_{0.7} mathrm{Ge}_{0.3}$. The simulated results infer that the performance of $S i_{0.7} G e_{0.3}$ based JLFET is better than that of Si-based DGJLFET yielding twofold increment in transconductance $left(g_{m}right)$, 1.4 times higher cut-off frequency $left(f_{T}right), 1.4$ times capacitance ratio $left(frac{C_{g s}}{C_{g d}}right), 2.3$ times early voltage (VEA), and 2 times output conductance $left(g_{d s}right)$. The results establish the potential advantages of compound semiconductor materials for their applicability in advanced field effect transistors.
在本文中;研究了一种基于硅(Si)、锗(Ge)和硅锗$left(S i_{0.7} mathrm{Ge}_{0.3}right)$的p型双栅无结场效应晶体管(DG-JLFET)，用于模拟/射频应用。本文旨在通过引入Ge和SiGe作为通道材料，提高基于摩尔定律的DG-JLFET在模拟和高速数字应用中的性能，并与传统的si基DG-JLFET进行比较。通过调节SiGe等化合物半导体材料的摩尔分数，可以调节载流子迁移率和饱和电压等电学特性。SiGe在无结晶体管中的迁移率和饱和电压的优化值已在$mathrm{S} S i_{0.7} mathrm{Ge}_{0.3}$上找到。仿真结果表明，$S i_{0.7} G e_{0.3}$基JLFET的性能优于硅基DGJLFET，其跨导率增加2倍$left(g_{m}right)$，截止频率提高1.4倍$left(f_{T}right), 1.4$倍电容比$left(frac{C_{g s}}{C_{g d}}right), 2.3$倍早期电压(VEA)，输出电导增加2倍$left(g_{d s}right)$。结果表明，复合半导体材料在应用于先进场效应晶体管方面具有潜在的优势。
{"title":"Comparative Analog Analysis of Si, Ge and Si0.7Ge0.3 Channel Based DG-JLFET","authors":"Ankita Porwal, Chitrakant Sahu, C. Periasamy","doi":"10.1109/iSES52644.2021.00025","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00025","url":null,"abstract":"In this paper; a p-type double gate junctionless field effect transistor (DG-JLFET) based on Silicon (Si), germanium(Ge), and silicon-germanium $left(S i_{0.7} mathrm{Ge}_{0.3}right)$ are investigated for analog/RF application. This paper aims to improve the performance of the DG-JLFET for analog and high-speed digital applications based on Moores law by introducing Ge and SiGe as channel materials and compare with conventional Si-based DG-JLFET. The electrical properties like carrier mobility and saturation voltage can be modulated by adjusting the mole fraction in compound semiconductor materials like SiGe. The optimized values of mobility and saturation voltage of SiGe have for their applicability in junctionless transistors has been found at $mathrm{S} S i_{0.7} mathrm{Ge}_{0.3}$. The simulated results infer that the performance of $S i_{0.7} G e_{0.3}$ based JLFET is better than that of Si-based DGJLFET yielding twofold increment in transconductance $left(g_{m}right)$, 1.4 times higher cut-off frequency $left(f_{T}right), 1.4$ times capacitance ratio $left(frac{C_{g s}}{C_{g d}}right), 2.3$ times early voltage (VEA), and 2 times output conductance $left(g_{d s}right)$. The results establish the potential advantages of compound semiconductor materials for their applicability in advanced field effect transistors.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128108097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00016
C. Shekhar, S. Qureshi
This paper presents a low power phase-locked loop implementation in indigenous SCL 180 nm CMOS technology. Fabricated PLL chip occupies an area of $0.005 mm^{2}$ including phase frequency detector, charge pump, current starved voltage controlled oscillator and divide by 4 block. An off-chip passive loop filter is used due to fab limitations. The frequency range of PLL varies from 10 to 105 MHz as shown in test results. The PLL chip consumes 0.28 mA ($approx 500 mu mathrm{W})$ from a 1.8 V supply while producing 50 MHz output clock. The measured phase noise is -100 dBc/Hz at 100 kHz.
本文提出了一种基于国产SCL 180 nm CMOS技术的低功耗锁相环实现方法。制作的锁相环芯片占地$0.005 mm^{2}$，包括相位频率检测器，电荷泵，电流饥渴压控振荡器，并除以4块。由于晶圆厂的限制，采用片外无源环路滤波器。测试结果显示，锁相环的频率范围为10 ～ 105 MHz。锁相环芯片从1.8 V电源消耗0.28 mA ($approx 500 mu mathrm{W})$)，同时产生50 MHz输出时钟。测得的相位噪声在100 kHz时为-100 dBc/Hz。
{"title":"Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology","authors":"C. Shekhar, S. Qureshi","doi":"10.1109/iSES52644.2021.00016","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00016","url":null,"abstract":"This paper presents a low power phase-locked loop implementation in indigenous SCL 180 nm CMOS technology. Fabricated PLL chip occupies an area of $0.005 mm^{2}$ including phase frequency detector, charge pump, current starved voltage controlled oscillator and divide by 4 block. An off-chip passive loop filter is used due to fab limitations. The frequency range of PLL varies from 10 to 105 MHz as shown in test results. The PLL chip consumes 0.28 mA ($approx 500 mu mathrm{W})$ from a 1.8 V supply while producing 50 MHz output clock. The measured phase noise is -100 dBc/Hz at 100 kHz.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131385100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00056
L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad
An energy-efficient approximate multiplier is designed by using an approximate compressor for image and video processing applications. This paper proposes an approximate 4:2 compressor design with an 18.75% error rate that consumes on an average 15% less energy compared with the existing designs from the literature. This paper proposes two variants of the multiplier, one with only approximate compressors and another one with approximate and accurate compressors.
{"title":"Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications","authors":"L. Krishna, J. B. Rao, Ayesha Sk, S. Veeramachaneni, S. Mahammad","doi":"10.1109/iSES52644.2021.00056","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00056","url":null,"abstract":"An energy-efficient approximate multiplier is designed by using an approximate compressor for image and video processing applications. This paper proposes an approximate 4:2 compressor design with an 18.75% error rate that consumes on an average 15% less energy compared with the existing designs from the literature. This paper proposes two variants of the multiplier, one with only approximate compressors and another one with approximate and accurate compressors.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130823750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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