Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582395
D. Eisenbiegler, Ramayya Kumar, C. Blumenröhr
This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfils the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches.
{"title":"A constructive approach towards correctness of synthesis-application within retiming","authors":"D. Eisenbiegler, Ramayya Kumar, C. Blumenröhr","doi":"10.1109/EDTC.1997.582395","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582395","url":null,"abstract":"This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfils the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125629379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582363
O. Coudert
This paper presents a ZBDD (Zero-Suppressed Binary Decision Diagram) based framework that solves a collection of graph optimization problems. We show how these problems reduce to three primitive problems, and how the later can be solved exactly using ZBDDs. The application of this framework is illustrated on multilayer planar routing, where it can solve real-life instances that cannot be handled otherwise.
{"title":"Solving graph optimization problems with ZBDDs","authors":"O. Coudert","doi":"10.1109/EDTC.1997.582363","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582363","url":null,"abstract":"This paper presents a ZBDD (Zero-Suppressed Binary Decision Diagram) based framework that solves a collection of graph optimization problems. We show how these problems reduce to three primitive problems, and how the later can be solved exactly using ZBDDs. The application of this framework is illustrated on multilayer planar routing, where it can solve real-life instances that cannot be handled otherwise.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133938763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582425
J. Leijten, J. V. Meerbergen, A. Timmer, J. Jess
PROPHID is a design method for high-performance systems with a focus on high-throughput signal processing applications. It makes use of a novel stream-based multi-processor architecture, consisting of data-driven autonomous processors interconnected by a programmable connection network. The key element is the communication arbiter which controls the flow of data between processors. Variable rates and data-dependent processing times are handled efficiently by performing scheduling at run time. We give an overview of the characteristics and advantages of the architecture as well as some implementation results.
{"title":"PROPHID: a data-driven multi-processor architecture for high-performance DSP","authors":"J. Leijten, J. V. Meerbergen, A. Timmer, J. Jess","doi":"10.1109/EDTC.1997.582425","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582425","url":null,"abstract":"PROPHID is a design method for high-performance systems with a focus on high-throughput signal processing applications. It makes use of a novel stream-based multi-processor architecture, consisting of data-driven autonomous processors interconnected by a programmable connection network. The key element is the communication arbiter which controls the flow of data between processors. Variable rates and data-dependent processing times are handled efficiently by performing scheduling at run time. We give an overview of the characteristics and advantages of the architecture as well as some implementation results.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115012594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582329
G. Lu, G. Sou
A CMOS, self-biasing, single-supply op amp is presented. It is designed with regulated cascode transistors for gain enhancement and a common-mode feedback technique for bias stabilisation of complementary regulated cascodes. It enables supply voltage lowering to about 2|V/sub /spl tau//|+2|V/sub ds,sat/| with the maintain of high-gain operation. At V/sub dd/=1.8 V, the measured DC gain of the op-amp is 115 dB, with a unity-gain frequency of 8.6 MHz for a capacitive load of 20 pF.
{"title":"A CMOS low-voltage, high-gain op-amp","authors":"G. Lu, G. Sou","doi":"10.1109/EDTC.1997.582329","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582329","url":null,"abstract":"A CMOS, self-biasing, single-supply op amp is presented. It is designed with regulated cascode transistors for gain enhancement and a common-mode feedback technique for bias stabilisation of complementary regulated cascodes. It enables supply voltage lowering to about 2|V/sub /spl tau//|+2|V/sub ds,sat/| with the maintain of high-gain operation. At V/sub dd/=1.8 V, the measured DC gain of the op-amp is 115 dB, with a unity-gain frequency of 8.6 MHz for a capacitive load of 20 pF.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115070034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582377
Hsiao-Ping Tseng, C. Sechen
We present a gridless multi-layer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell routing region into top and bottom parts. Our router routes nets in both the channel (if needed) and over-the-cell. The router uses a combined constraint graph and tile expansion algorithm. It achieves channelless solutions for the Primary1 circuit by routing over the cell in three layers. For classical channel routing examples, it achieves solutions at density for Deutsch's difficult example in two, three, four and five metal layers. It also generates equal or better results compared to the best of the previous channel routers for all the examples we have tried.
{"title":"A gridless multi-layer router for standard cell circuits using CTM cells","authors":"Hsiao-Ping Tseng, C. Sechen","doi":"10.1109/EDTC.1997.582377","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582377","url":null,"abstract":"We present a gridless multi-layer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell routing region into top and bottom parts. Our router routes nets in both the channel (if needed) and over-the-cell. The router uses a combined constraint graph and tile expansion algorithm. It achieves channelless solutions for the Primary1 circuit by routing over the cell in three layers. For classical channel routing examples, it achieves solutions at density for Deutsch's difficult example in two, three, four and five metal layers. It also generates equal or better results compared to the best of the previous channel routers for all the examples we have tried.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114114191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582360
R. Cmar, S. Vernalde
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for different video standards. The parameters by which the ME is described allow for a variety of architecture implementations. The parameters specify the level of parallelism reflected by multiple allocation of computational resources, and the use of configurable cache memories. The obtained VHDL description of the ME module is well suited for VLSI implementation.
{"title":"Highly scalable parallel parametrizable architecture of the motion estimator","authors":"R. Cmar, S. Vernalde","doi":"10.1109/EDTC.1997.582360","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582360","url":null,"abstract":"In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for different video standards. The parameters by which the ME is described allow for a variety of architecture implementations. The parameters specify the level of parallelism reflected by multiple allocation of computational resources, and the use of configurable cache memories. The obtained VHDL description of the ME module is well suited for VLSI implementation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582379
R. O. Duarte, M. Nicolaidis, H. Bederr, Y. Zorian
Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths.
{"title":"Fault-secure shifter design: results and implementations","authors":"R. O. Duarte, M. Nicolaidis, H. Bederr, Y. Zorian","doi":"10.1109/EDTC.1997.582379","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582379","url":null,"abstract":"Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114767778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582328
P. Bénabès, M. Keramat, R. Kielbasa
A methodology for analysis and synthesis of lowpass sigma-delta (/spl Sigma//spl Delta/) converters is presented in this paper. This method permits to synthesize /spl Sigma//spl Delta/ modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of continuous-time model and using a discrete simulator which is more efficient than an analog simulator. Finally, a realistic design of a second-order /spl Sigma//spl Delta/ modulator with a compensation of the non ideal behavior of DAC is given. Moreover, simulation results show a good agreement with the theoretical bases.
{"title":"A methodology for designing continuous-time sigma-delta modulators","authors":"P. Bénabès, M. Keramat, R. Kielbasa","doi":"10.1109/EDTC.1997.582328","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582328","url":null,"abstract":"A methodology for analysis and synthesis of lowpass sigma-delta (/spl Sigma//spl Delta/) converters is presented in this paper. This method permits to synthesize /spl Sigma//spl Delta/ modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of continuous-time model and using a discrete simulator which is more efficient than an analog simulator. Finally, a realistic design of a second-order /spl Sigma//spl Delta/ modulator with a compensation of the non ideal behavior of DAC is given. Moreover, simulation results show a good agreement with the theoretical bases.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126701789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582378
K. Chakraborty, P. Mazumder
A framework for integrating boundary scan (IEEE 1149.1) with board-level self-testing of word-oriented, multiport static RAM chips is proposed. Innovative parallel versions of functional duplex march tests (FDMs) for detecting complex couplings are developed. This approach produces significantly smaller cycle-time penalty during normal operation than built-in self-testing (BIST). It produces two orders of magnitude test acceleration as compared to pure boundary scan testing without BIST (i.e., by using EXTEST and SAMPLE/PRELOAD instructions only).
{"title":"A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs","authors":"K. Chakraborty, P. Mazumder","doi":"10.1109/EDTC.1997.582378","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582378","url":null,"abstract":"A framework for integrating boundary scan (IEEE 1149.1) with board-level self-testing of word-oriented, multiport static RAM chips is proposed. Innovative parallel versions of functional duplex march tests (FDMs) for detecting complex couplings are developed. This approach produces significantly smaller cycle-time penalty during normal operation than built-in self-testing (BIST). It produces two orders of magnitude test acceleration as compared to pure boundary scan testing without BIST (i.e., by using EXTEST and SAMPLE/PRELOAD instructions only).","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129386820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582413
C. Schneider
In this paper a method of architecture exploration and selection is presented. Compared with other approaches, no special tools or modeling languages are needed-instead the models and tools of the ASIC design flow are used. The architecture trade-off process is performed iteratively, and considers information from different levels of abstraction in parallel. At system level, software and behavioral models, which are part of executable specifications are examined to get the necessary top-down information (performance). Bottom-up information (hardware costs) for irregular hardware structures is obtained by generating, analyzing and synthesizing VHDL code at RT-Level. For regular structures, formulas or tables can be used to estimate area and timing. The proposed approach was successfully performed for parts of a multimedia design, where an executable specification (in 'C') was available together with the standard.
{"title":"A methodology for hardware architecture trade-off at different levels of abstraction","authors":"C. Schneider","doi":"10.1109/EDTC.1997.582413","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582413","url":null,"abstract":"In this paper a method of architecture exploration and selection is presented. Compared with other approaches, no special tools or modeling languages are needed-instead the models and tools of the ASIC design flow are used. The architecture trade-off process is performed iteratively, and considers information from different levels of abstraction in parallel. At system level, software and behavioral models, which are part of executable specifications are examined to get the necessary top-down information (performance). Bottom-up information (hardware costs) for irregular hardware structures is obtained by generating, analyzing and synthesizing VHDL code at RT-Level. For regular structures, formulas or tables can be used to estimate area and timing. The proposed approach was successfully performed for parts of a multimedia design, where an executable specification (in 'C') was available together with the standard.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"722 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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