Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735174
S. Miropolsky, Alexander Sapadinsky, S. Frei
Development of accurate system models of immunity test setups might be extremely time consuming or even impossible. Here a new generalized approach to develop accurate component-based models of different system-level EMC test setups is proposed on the example of a BCI test setup. An equivalent circuit modelling of the components in LF range is combined with measurement-based macromodelling in HF range. The developed models show high accuracy up to 1 GHz. The issues of floating PCB configurations and incorporation of low frequency behaviour could be solved. Both frequency and time-domain simulations are possible. Arbitrary system configurations can be assembled quickly using the proposed component models. Any kind of system simulation like parametric variation and worst-case analysis can be performed with high accuracy.
{"title":"A generalized accurate modelling method for automotive bulk current injection (BCI) test setups up to 1 GHz","authors":"S. Miropolsky, Alexander Sapadinsky, S. Frei","doi":"10.1109/EMCCOMPO.2013.6735174","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735174","url":null,"abstract":"Development of accurate system models of immunity test setups might be extremely time consuming or even impossible. Here a new generalized approach to develop accurate component-based models of different system-level EMC test setups is proposed on the example of a BCI test setup. An equivalent circuit modelling of the components in LF range is combined with measurement-based macromodelling in HF range. The developed models show high accuracy up to 1 GHz. The issues of floating PCB configurations and incorporation of low frequency behaviour could be solved. Both frequency and time-domain simulations are possible. Arbitrary system configurations can be assembled quickly using the proposed component models. Any kind of system simulation like parametric variation and worst-case analysis can be performed with high accuracy.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123934057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735178
Kyungsoo Kim, W. Nah, Soyoung Kim
This paper presents several Schmitt trigger logic gates with enhanced noise immunity using variable threshold voltage technique for sub-threshold voltage operation. The proposed logic gates are based on buffer design using dynamic threshold voltage MOS (DTMOS) for low power operation (VDD=0.4V). Our solution dramatically improves noise immunity of logic gates with much less switching power consumption and significant area reduction compared with CMOS Schmitt triggers at the expense of slight increase in delay. The proposed noise immune gate design scheme is verified with an example digital circuit.
{"title":"Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits","authors":"Kyungsoo Kim, W. Nah, Soyoung Kim","doi":"10.1109/EMCCOMPO.2013.6735178","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735178","url":null,"abstract":"This paper presents several Schmitt trigger logic gates with enhanced noise immunity using variable threshold voltage technique for sub-threshold voltage operation. The proposed logic gates are based on buffer design using dynamic threshold voltage MOS (DTMOS) for low power operation (VDD=0.4V). Our solution dramatically improves noise immunity of logic gates with much less switching power consumption and significant area reduction compared with CMOS Schmitt triggers at the expense of slight increase in delay. The proposed noise immune gate design scheme is verified with an example digital circuit.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124507590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735177
Y. Hayashi, N. Homma, T. Aoki, Y. Okugawa, Y. Akiyama
This paper presents a time-domain visualization method for tracing electromagnetic (EM) radiation associated with information leakage from cryptographic ICs on the printed circuit board (PCB) surface. In recent years, security threats based on EM analysis attacks on cryptographic devices are attracting considerable attention due to their relative simplicity in practice. Some of the most cost-effective countermeasures against such attacks can be implemented at the PCB level. In order to implement such countermeasures effectively, critical parts (i.e., information sources and information propagation paths) on the board should be identified in advance. The key idea behind this identification is to calculate a correlation between measured EM traces and EM intensity values estimated from correct information (secret key) in the time domain. Transient analysis can reveal information propagation paths even if the EM signal carrying information is weak in comparison with noise generated from other components. Through an experiment, we confirm that EM radiation associated with information leakage can be traced even in situations where the information signal is obscured by background noise.
{"title":"Transient analysis of EM radiation associated with information leakage from cryptographic ICs","authors":"Y. Hayashi, N. Homma, T. Aoki, Y. Okugawa, Y. Akiyama","doi":"10.1109/EMCCOMPO.2013.6735177","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735177","url":null,"abstract":"This paper presents a time-domain visualization method for tracing electromagnetic (EM) radiation associated with information leakage from cryptographic ICs on the printed circuit board (PCB) surface. In recent years, security threats based on EM analysis attacks on cryptographic devices are attracting considerable attention due to their relative simplicity in practice. Some of the most cost-effective countermeasures against such attacks can be implemented at the PCB level. In order to implement such countermeasures effectively, critical parts (i.e., information sources and information propagation paths) on the board should be identified in advance. The key idea behind this identification is to calculate a correlation between measured EM traces and EM intensity values estimated from correct information (secret key) in the time domain. Transient analysis can reveal information propagation paths even if the EM signal carrying information is weak in comparison with noise generated from other components. Through an experiment, we confirm that EM radiation associated with information leakage can be traced even in situations where the information signal is obscured by background noise.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134281408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735194
Yin-Cheng Chang, S. Hsu, Yen-Tang Chang, Chiu-Kuo Chen, Hsu-Chen Cheng, D. Chang
The direct RF power injection (DPI) measurement up to 18 GHz is proposed to investigate the IC immunity. The DPI method is reviewed and the consideration of extending frequency range is discussed. Furthermore, the details of the measurement setup are depicted in this work. The critical part, on-board injection network in the power injection path with a 3 dB bandwidth of 18.7 GHz is realized. A low dropout regulator (LDO) is used to demonstrate the test setup. The proposed DPI test with the experimental results shows the significance up to 18 GHz.
{"title":"The direct RF power injection method up to 18 GHz for investigating IC's susceptibility","authors":"Yin-Cheng Chang, S. Hsu, Yen-Tang Chang, Chiu-Kuo Chen, Hsu-Chen Cheng, D. Chang","doi":"10.1109/EMCCOMPO.2013.6735194","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735194","url":null,"abstract":"The direct RF power injection (DPI) measurement up to 18 GHz is proposed to investigate the IC immunity. The DPI method is reviewed and the consideration of extending frequency range is discussed. Furthermore, the details of the measurement setup are depicted in this work. The critical part, on-board injection network in the power injection path with a 3 dB bandwidth of 18.7 GHz is realized. A low dropout regulator (LDO) is used to demonstrate the test setup. The proposed DPI test with the experimental results shows the significance up to 18 GHz.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"389 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735196
K. Iokibe, Y. Toyota
An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.
{"title":"Estimation of data-dependent power voltage variations of FPGA by equivalent circuit modeling from on-board measurements","authors":"K. Iokibe, Y. Toyota","doi":"10.1109/EMCCOMPO.2013.6735196","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735196","url":null,"abstract":"An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130754691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-21DOI: 10.1109/ISEMC.2013.6670493
S. Muroga, Y. Shimada, Y. Endo, S. Tanaka, M. Yamaguchi, N. Azuma, M. Nagata, M. Murakami, K. Hori, Shin-ichiro Takahashi
A long term evolution (LTE)-class CMOS radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip is developed in our project for the next generation cell phone handsets in order to clarify the on-chip-level noise coupling and demonstrate the noise attenuation using the soft magnetic thin film as an on-chip electromagnetic noise suppressor. The TEG chip equips a noise generator and a RF receiver block. The RF block amplifies and demodulates transmitted signals to IQ signals. A Co85Zr3Nb12 soft magnetic thin film is integrated onto the TEG chip as a noise suppressor. In this report, the noise generator is driven by a clock signal of 124.803 MHz and generates 17th harmonics of 2,165 MHz conflicts with the LTE band 1 (2,110 - 2,170 MHz). As a result, the in-band digital noise was suppressed 5-20 dB by the Co-Zr-Nb thin film as an integrated noise suppressor.
{"title":"In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film","authors":"S. Muroga, Y. Shimada, Y. Endo, S. Tanaka, M. Yamaguchi, N. Azuma, M. Nagata, M. Murakami, K. Hori, Shin-ichiro Takahashi","doi":"10.1109/ISEMC.2013.6670493","DOIUrl":"https://doi.org/10.1109/ISEMC.2013.6670493","url":null,"abstract":"A long term evolution (LTE)-class CMOS radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip is developed in our project for the next generation cell phone handsets in order to clarify the on-chip-level noise coupling and demonstrate the noise attenuation using the soft magnetic thin film as an on-chip electromagnetic noise suppressor. The TEG chip equips a noise generator and a RF receiver block. The RF block amplifies and demodulates transmitted signals to IQ signals. A Co85Zr3Nb12 soft magnetic thin film is integrated onto the TEG chip as a noise suppressor. In this report, the noise generator is driven by a clock signal of 124.803 MHz and generates 17th harmonics of 2,165 MHz conflicts with the LTE band 1 (2,110 - 2,170 MHz). As a result, the in-band digital noise was suppressed 5-20 dB by the Co-Zr-Nb thin film as an integrated noise suppressor.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EMCCOMPO.2013.6735189
H. Fujita, H. Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, T. Sudo
Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level. So chip level counter-measure is even more important to reduce EMI as an excitation source of noise. In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip. One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors. Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design. It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region.
{"title":"Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures","authors":"H. Fujita, H. Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, T. Sudo","doi":"10.1109/EMCCOMPO.2013.6735189","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735189","url":null,"abstract":"Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level. So chip level counter-measure is even more important to reduce EMI as an excitation source of noise. In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip. One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors. Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design. It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127731679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EMCCOMPO.2013.6735195
W. Ichimura, S. Kiyoshige, Masahiro Terasaki, R. Kobayashi, G. Kubo, H. Otsuka, T. Sudo
Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, power supply noise and total PDN impedance have been examined by changing the number of power supply terminals. As a result, it has been proved that anti-resonance peaks could be controlled by on-die capacitance and the number of power supply terminals. Simulated anti-resonance peak frequencies were well correlated with the peak frequency spectra of measured power supply noise.
{"title":"Anti-resonance peak frequency control by variable on-die capacitance","authors":"W. Ichimura, S. Kiyoshige, Masahiro Terasaki, R. Kobayashi, G. Kubo, H. Otsuka, T. Sudo","doi":"10.1109/EMCCOMPO.2013.6735195","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735195","url":null,"abstract":"Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, power supply noise and total PDN impedance have been examined by changing the number of power supply terminals. As a result, it has been proved that anti-resonance peaks could be controlled by on-die capacitance and the number of power supply terminals. Simulated anti-resonance peak frequencies were well correlated with the peak frequency spectra of measured power supply noise.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125315221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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