Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735198
Shih-Yi Yuan
This paper proposes a model building process for conducted electromagnetic interference (cEMI) model of microcontroller (μC) considering software effect. Due to the fast advances of embedded system design technologies, software now is capable of controlling nearly all the features of electronic modules, which means software can actually affect EMI characteristics of target modules. Thus, a software-level EMI model is essential for electronic modules. Due to intellectual property (IP) considerations, IC designers seldom expose the internal architecture details of their IC products to EMI modelers. Because the internal module behaviors are unknown, it makes EMI modeling very difficult. This paper proposes a block-box cEMI modeling procedure for μC. The concept is based on a set of block-box impulse response (BBIR) functions. BBIR modeling method is based only on measurement information and treats the target as a block-box. After the model building process, the cEMI behavior of a new testing boards (or modules) with the same μC can be estimated. This model is verified by a case study. From the experiment results, it shows that the proposed method can estimate different machine code cEMI behaviors. The estimated result is in good accordance with the measurements both in time-domain and frequency-domain. The results also shows the internal impedances of a μC are quite different among machine codes executed by the μC.
{"title":"A microcontrller conducted EMI model building for software-level effect","authors":"Shih-Yi Yuan","doi":"10.1109/EMCCOMPO.2013.6735198","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735198","url":null,"abstract":"This paper proposes a model building process for conducted electromagnetic interference (cEMI) model of microcontroller (μC) considering software effect. Due to the fast advances of embedded system design technologies, software now is capable of controlling nearly all the features of electronic modules, which means software can actually affect EMI characteristics of target modules. Thus, a software-level EMI model is essential for electronic modules. Due to intellectual property (IP) considerations, IC designers seldom expose the internal architecture details of their IC products to EMI modelers. Because the internal module behaviors are unknown, it makes EMI modeling very difficult. This paper proposes a block-box cEMI modeling procedure for μC. The concept is based on a set of block-box impulse response (BBIR) functions. BBIR modeling method is based only on measurement information and treats the target as a block-box. After the model building process, the cEMI behavior of a new testing boards (or modules) with the same μC can be estimated. This model is verified by a case study. From the experiment results, it shows that the proposed method can estimate different machine code cEMI behaviors. The estimated result is in good accordance with the measurements both in time-domain and frequency-domain. The results also shows the internal impedances of a μC are quite different among machine codes executed by the μC.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735193
D. Jung, Heegon Kim, Jonghoon J. Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi
Vertical interconnections of stacked chips through the silicon substrates have enabled higher performance of electronic products with lower power consumption. The advantage of through silicon via (TSV) technique can be maximized by increasing the number of I/Os, which requires fine pitch and smaller diameter. The scale-down of TSVs results in decreased yield level caused by lack of precision in fabrication process. Among various types of possible defects, open defect creates a disconnection in the channel, electrically separating the transmitting terminal from the receiving target. In this paper, the equivalent circuit model for open defect is proposed and inserted as circuit component in a circuit model for defect-free channel. Open defect is analyzed in different locations along the channel to examine the effect in signal transmission characteristics.
{"title":"Modeling and analysis of open defect in through silicon via (TSV) channel","authors":"D. Jung, Heegon Kim, Jonghoon J. Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi","doi":"10.1109/EMCCOMPO.2013.6735193","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735193","url":null,"abstract":"Vertical interconnections of stacked chips through the silicon substrates have enabled higher performance of electronic products with lower power consumption. The advantage of through silicon via (TSV) technique can be maximized by increasing the number of I/Os, which requires fine pitch and smaller diameter. The scale-down of TSVs results in decreased yield level caused by lack of precision in fabrication process. Among various types of possible defects, open defect creates a disconnection in the channel, electrically separating the transmitting terminal from the receiving target. In this paper, the equivalent circuit model for open defect is proposed and inserted as circuit component in a circuit model for defect-free channel. Open defect is analyzed in different locations along the channel to examine the effect in signal transmission characteristics.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117078373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735183
T. Funaki
The development of high voltage SiC power MOSFET has made the fast switching of high voltage possible. The high dv/dt caused by fast high voltage switching induces the difficulty of mal-operation of power MOSFET with the self turn-on phenomenon by the fluctuation of gate voltage. This phenomenon is recognized as intra EMC. This paper studies the mechanism of self turn-on phenomenon and discusses the suppression method.
{"title":"A study on gate voltage fluctuation of MOSFET induced by switching operation of adjacent MOSFET in high voltage power conversion circuit","authors":"T. Funaki","doi":"10.1109/EMCCOMPO.2013.6735183","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735183","url":null,"abstract":"The development of high voltage SiC power MOSFET has made the fast switching of high voltage possible. The high dv/dt caused by fast high voltage switching induces the difficulty of mal-operation of power MOSFET with the self turn-on phenomenon by the fluctuation of gate voltage. This phenomenon is recognized as intra EMC. This paper studies the mechanism of self turn-on phenomenon and discusses the suppression method.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122978592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735188
Shih-Yi Yuan, S. Liao
This paper proposes an automatic algorithm for block-box electromagnetic interference (EMI) modeling of microcontroller (μC). Due to intellectual property considerations, IC design companies seldom expose internal architecture details of their μC products to EMI modelers. Since the internal module behaviors are unknown, it makes EMI modeling very difficult. This method is based on the measurement of a pre-prepared testing board(s) to build a conducted EMI (cEMI) μC model. The concept is based on block-box impulse response (BBIR) function calculation. BBIR is based on solely measurement basis and treat the target as a block-box. Through block-box type deductions and measurements, BBIR model can be built. After the model is built, the cEMI behavior of a new testing board (or module) with the same μC are estimated. A case study is given for the proposed method. In this case study, the cEMI model is firstly built and, then, followed by a real measurement of the cEMI behaviors of the new testing board. The proposed model is verified by the comparison of the estimated data and the physical measurements. From the experiment results, it shows that the proposed power model does in good accordance with the cEMI behavior of the target μC both in time-domain and frequency-domain.
{"title":"Automatic conducted-EMI microcontroller model building","authors":"Shih-Yi Yuan, S. Liao","doi":"10.1109/EMCCOMPO.2013.6735188","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735188","url":null,"abstract":"This paper proposes an automatic algorithm for block-box electromagnetic interference (EMI) modeling of microcontroller (μC). Due to intellectual property considerations, IC design companies seldom expose internal architecture details of their μC products to EMI modelers. Since the internal module behaviors are unknown, it makes EMI modeling very difficult. This method is based on the measurement of a pre-prepared testing board(s) to build a conducted EMI (cEMI) μC model. The concept is based on block-box impulse response (BBIR) function calculation. BBIR is based on solely measurement basis and treat the target as a block-box. Through block-box type deductions and measurements, BBIR model can be built. After the model is built, the cEMI behavior of a new testing board (or module) with the same μC are estimated. A case study is given for the proposed method. In this case study, the cEMI model is firstly built and, then, followed by a real measurement of the cEMI behaviors of the new testing board. The proposed model is verified by the comparison of the estimated data and the physical measurements. From the experiment results, it shows that the proposed power model does in good accordance with the cEMI behavior of the target μC both in time-domain and frequency-domain.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121659130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735187
Masaaki Maeda, T. Matsushima, O. Wada
Simultaneous switching current of a CMOS circuit causes power and ground bounces. The voltage fluctuation is injected into the CMOS substrate, and it degrades the performance of the circuit operation. In this report, we focus on the fact that parasitic couplings in the CMOS substrate and parasitic inductance in the power and ground connection form a bridge circuit, and we demonstrate that the voltage bounce can be suppressed by controlling variable resistances that are inserted between the substrate resistive coupling and the conductor line for the DC supply. The effectiveness of this method is verified with a scaled quad flat package (QFP) and we reduced the measured voltage bounce about 40 dBμV.
{"title":"Impedance balance control for suppression of fluctuation on ground voltage in LSI package","authors":"Masaaki Maeda, T. Matsushima, O. Wada","doi":"10.1109/EMCCOMPO.2013.6735187","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735187","url":null,"abstract":"Simultaneous switching current of a CMOS circuit causes power and ground bounces. The voltage fluctuation is injected into the CMOS substrate, and it degrades the performance of the circuit operation. In this report, we focus on the fact that parasitic couplings in the CMOS substrate and parasitic inductance in the power and ground connection form a bridge circuit, and we demonstrate that the voltage bounce can be suppressed by controlling variable resistances that are inserted between the substrate resistive coupling and the conductor line for the DC supply. The effectiveness of this method is verified with a scaled quad flat package (QFP) and we reduced the measured voltage bounce about 40 dBμV.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115866911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735192
Jonghoon J. Kim, Heegon Kim, Sukjin Kim, Bumhee Bae, D. Jung, Sunkyu Kong, Joungho Kim, Junho Lee, Kunwoo Park
Driven by the abrupt miniaturization of mobile devices and demand for 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating multiple dies of various functions as a whole system. However, due to the instability in the TSV fabrication process, various types of disconnection defects can be resulted during fabrication steps, resulting in a severe decrease in the final chip yield as the number of TSVs and stacked dies increases. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure using capacitive coupling that can detect TSV disconnection defects on wafer-level. The proposed structure can detect the TSV disconnection by observing the change in the capacitance between adjacent TSVs, using only passive components such as metal pads and lines, without additional power consumption for the testing. Through time- and frequency-domain simulation results, such as transfer impedance and voltage waveforms, we verified that the proposed structure can successfully detect TSV defects, while overcoming the limitations of the conventional direct probing methods.
{"title":"Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling","authors":"Jonghoon J. Kim, Heegon Kim, Sukjin Kim, Bumhee Bae, D. Jung, Sunkyu Kong, Joungho Kim, Junho Lee, Kunwoo Park","doi":"10.1109/EMCCOMPO.2013.6735192","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735192","url":null,"abstract":"Driven by the abrupt miniaturization of mobile devices and demand for 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating multiple dies of various functions as a whole system. However, due to the instability in the TSV fabrication process, various types of disconnection defects can be resulted during fabrication steps, resulting in a severe decrease in the final chip yield as the number of TSVs and stacked dies increases. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure using capacitive coupling that can detect TSV disconnection defects on wafer-level. The proposed structure can detect the TSV disconnection by observing the change in the capacitance between adjacent TSVs, using only passive components such as metal pads and lines, without additional power consumption for the testing. Through time- and frequency-domain simulation results, such as transfer impedance and voltage waveforms, we verified that the proposed structure can successfully detect TSV defects, while overcoming the limitations of the conventional direct probing methods.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"62 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131521401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735175
T. Mandic, R. Gillon, A. Barić
This paper presents design optimization of closed version of an IC-Stripline. The geometrical parameters of the IC-Stripline are optimized in order to improve VSWR performance in the frequency range up to 6 GHz. Since the optimization performed directly in 3D EM simulator is computationally expensive, the response surface methodology (RSM) based on design of experiment (DOE) is used to develop surrogate models and to accelerate IC-Stripline design optimization. The design of experiment approach is used to systematically vary geometrical parameters of the IC-Stripline structure which are then simulated in a 3D electromagnetic simulator. The equivalent model circuit parameters are extracted according to the 3D EM simulation results. The response surface formed by the extracted parameter values is modelled using a higher order polynomial. The VSWR optimization of the IC-Stripline is performed by optimizing the equivalent circuit model having the parameters defined by the response surface models. The proposed design of the IC-Stripline shows the improvement in VSWR performance over the frequency range up to 6 GHz.
{"title":"IC-Stripline design optimization using response surface methodology","authors":"T. Mandic, R. Gillon, A. Barić","doi":"10.1109/EMCCOMPO.2013.6735175","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735175","url":null,"abstract":"This paper presents design optimization of closed version of an IC-Stripline. The geometrical parameters of the IC-Stripline are optimized in order to improve VSWR performance in the frequency range up to 6 GHz. Since the optimization performed directly in 3D EM simulator is computationally expensive, the response surface methodology (RSM) based on design of experiment (DOE) is used to develop surrogate models and to accelerate IC-Stripline design optimization. The design of experiment approach is used to systematically vary geometrical parameters of the IC-Stripline structure which are then simulated in a 3D electromagnetic simulator. The equivalent model circuit parameters are extracted according to the 3D EM simulation results. The response surface formed by the extracted parameter values is modelled using a higher order polynomial. The VSWR optimization of the IC-Stripline is performed by optimizing the equivalent circuit model having the parameters defined by the response surface models. The proposed design of the IC-Stripline shows the improvement in VSWR performance over the frequency range up to 6 GHz.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132551360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735165
S. O. Land, R. Perdriau, M. Ramdani, O. Maurice, M. Drissi
Printed Circuit Board (PCB) traces play a role in the immunity of electronic products. Contrary to Integrated Circuits (ICs), the layout of PCB traces can be changed rather late in a product's design. Therefore, it is interesting to equip the PCB designer with simple tools that predict the immunity of his PCB traces. In this article, we compare two simulations of field-to-long line coupling based on Taylor's model. Firstly, the line is meshed into electrically short Taylor cells and numerically simulated using Kron's method. Secondly, we use one modified Taylor cell, which does not need meshing and is a closed-form, analytical result. The two simulations turn out to be equally precise on a straight microstrip line, the meshed simulation being more flexible, the simulation using a modified Taylor cell being faster.
{"title":"Kron simulation of field-to-line coupling using a meshed and a modified Taylor cell","authors":"S. O. Land, R. Perdriau, M. Ramdani, O. Maurice, M. Drissi","doi":"10.1109/EMCCOMPO.2013.6735165","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735165","url":null,"abstract":"Printed Circuit Board (PCB) traces play a role in the immunity of electronic products. Contrary to Integrated Circuits (ICs), the layout of PCB traces can be changed rather late in a product's design. Therefore, it is interesting to equip the PCB designer with simple tools that predict the immunity of his PCB traces. In this article, we compare two simulations of field-to-long line coupling based on Taylor's model. Firstly, the line is meshed into electrically short Taylor cells and numerically simulated using Kron's method. Secondly, we use one modified Taylor cell, which does not need meshing and is a closed-form, analytical result. The two simulations turn out to be equally precise on a straight microstrip line, the meshed simulation being more flexible, the simulation using a modified Taylor cell being faster.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124530332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735163
Heegon Kim, Jonghyun Cho, D. Jung, Jonghoon J. Kim, Sumin Choi, Joungho Kim, Junho Lee, Kunwoo Park
In this paper, a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling was proposed and experimentally verified. By using the parasitic resistance and inductance of the coil-shaped on-interposer metal line, the proposed on-interposer passive equalizer achieves not only the wide-band equalization but also the compact size. Moreover, the symmetric structure of the proposed equalizer maintains the balance between the differential signals. The remarkable performance of the proposed on-interposer passive equalizer for differential signaling was successfully verified by a frequency- and time-domain measurement of up to 10 Gbps.
{"title":"Design and measurement of a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling","authors":"Heegon Kim, Jonghyun Cho, D. Jung, Jonghoon J. Kim, Sumin Choi, Joungho Kim, Junho Lee, Kunwoo Park","doi":"10.1109/EMCCOMPO.2013.6735163","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735163","url":null,"abstract":"In this paper, a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling was proposed and experimentally verified. By using the parasitic resistance and inductance of the coil-shaped on-interposer metal line, the proposed on-interposer passive equalizer achieves not only the wide-band equalization but also the compact size. Moreover, the symmetric structure of the proposed equalizer maintains the balance between the differential signals. The remarkable performance of the proposed on-interposer passive equalizer for differential signaling was successfully verified by a frequency- and time-domain measurement of up to 10 Gbps.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129108346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/EMCCOMPO.2013.6735208
Y. Kondo, K. Tsunada, N. Oka, Masato Izumichi
This paper provides an immunity simulation method for product-level automotive power modules that contain printed circuit boards (PCBs). A stress-strength model is adopted as an estimation method for the susceptibility. The stress is the value of the RF power injected into a victim circuit, and the strength is the acceptance stress criteria of the victim circuit. By using electromagnetic simulation, the stress of the victim circuit is calculated. The strength of the victim circuit is determined by the DPI test result. By comparing the stress and strength of the victim circuit, the susceptibility thresholds can be predicted. The results show good agreement with the experimental results in the DPI test for a power module containing a complex product-level PCB and exhibit a good correlation with the BCI test for the power module.
{"title":"Immunity simulation method for automotive power module using electromagnetic analysis","authors":"Y. Kondo, K. Tsunada, N. Oka, Masato Izumichi","doi":"10.1109/EMCCOMPO.2013.6735208","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2013.6735208","url":null,"abstract":"This paper provides an immunity simulation method for product-level automotive power modules that contain printed circuit boards (PCBs). A stress-strength model is adopted as an estimation method for the susceptibility. The stress is the value of the RF power injected into a victim circuit, and the strength is the acceptance stress criteria of the victim circuit. By using electromagnetic simulation, the stress of the victim circuit is calculated. The strength of the victim circuit is determined by the DPI test result. By comparing the stress and strength of the victim circuit, the susceptibility thresholds can be predicted. The results show good agreement with the experimental results in the DPI test for a power module containing a complex product-level PCB and exhibit a good correlation with the BCI test for the power module.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126773535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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