Pub Date : 1900-01-01DOI: 10.1109/SOI.2012.6404378
T. Nicoletti, S. Santos, J. Martino, M. Aoulaiche, A. Veloso, M. Jurczak, E. Simoen, C. Claeys
FBRAM on UTBOX SOI wafers, using the BJT with a positive back bias programming scheme, is studied versus the gate length. The optimized FBRAM parameters such as the sense margin and the retention time are shown as a function of the gate length. For longer L the back bias can be used to optimize the FBRAM performance, whereas for shorter L, hole generation amplification during the read operation by the bipolar junction transistor gain, inherent to SOI nMOSFET devices and used for the read is a limiting issue. Therefore, there is critical gate length to FBRAM scaling. To avoid FBRAM performance degradation, L should be longer than the critical length. Moreover, this work suggests that vertical devices, which allow longer L are more scalable.
{"title":"Gate length impact on UTBOX FBRAM devices","authors":"T. Nicoletti, S. Santos, J. Martino, M. Aoulaiche, A. Veloso, M. Jurczak, E. Simoen, C. Claeys","doi":"10.1109/SOI.2012.6404378","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404378","url":null,"abstract":"FBRAM on UTBOX SOI wafers, using the BJT with a positive back bias programming scheme, is studied versus the gate length. The optimized FBRAM parameters such as the sense margin and the retention time are shown as a function of the gate length. For longer L the back bias can be used to optimize the FBRAM performance, whereas for shorter L, hole generation amplification during the read operation by the bipolar junction transistor gain, inherent to SOI nMOSFET devices and used for the read is a limiting issue. Therefore, there is critical gate length to FBRAM scaling. To avoid FBRAM performance degradation, L should be longer than the critical length. Moreover, this work suggests that vertical devices, which allow longer L are more scalable.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122360903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOI.2012.6404375
R. Buhler, P. Agopian, E. Simoen, C. Claeys, J. Martino
MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is work we study the stress distribution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through electrical characterization of experimental devices and 3D process and device numerical simulation. Experimental results of standard and strained devices were used to validate the simulations. The bi+uni stress technique delivered enhanced maximum transconductance.
{"title":"Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions","authors":"R. Buhler, P. Agopian, E. Simoen, C. Claeys, J. Martino","doi":"10.1109/SOI.2012.6404375","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404375","url":null,"abstract":"MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is work we study the stress distribution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through electrical characterization of experimental devices and 3D process and device numerical simulation. Experimental results of standard and strained devices were used to validate the simulations. The bi+uni stress technique delivered enhanced maximum transconductance.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125946967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOI.2012.6404383
P. Agopian, M. D. V. Martino, J. Martino, R. Rooyackers, D. Leonelli, C. Claeys
This paper presents an experimental study of the pTFET analog performance as a function of the temperature. It was observed that the gm improves with the temperature while the gD degrades. The gD degradation was the predominant effect which causes an AV reduction with temperature increase. However, independent of the temperature, comparing the pTFET and the pFinFET with the similar structure and same bias conditions, the first one presents a better analog performance in the temperature studied. The pTFET shows to be a good option for analog applications.
{"title":"Experimental analog performance of pTFETs as a function of temperature","authors":"P. Agopian, M. D. V. Martino, J. Martino, R. Rooyackers, D. Leonelli, C. Claeys","doi":"10.1109/SOI.2012.6404383","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404383","url":null,"abstract":"This paper presents an experimental study of the pTFET analog performance as a function of the temperature. It was observed that the gm improves with the temperature while the gD degrades. The gD degradation was the predominant effect which causes an AV reduction with temperature increase. However, independent of the temperature, comparing the pTFET and the pFinFET with the similar structure and same bias conditions, the first one presents a better analog performance in the temperature studied. The pTFET shows to be a good option for analog applications.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOI.2012.6404394
M. Aoulaiche, T. Nicoletti, A. Veloso, P. Roussel, E. Simoen, C. Claeys, G. Groeseneken, M. Jurczak
The variability of 1T FBRAM performances is investigated. The VG read window and the state "1" distribution are correlated with the number of holes injected during the write "1" related to the electric field in the S/D junctions. Besides, the origin of wide retention time distribution has been correlated with the distribution of G-R center in the Si band gap. Single defect with the Si midgap energy level can generate a leakage path affecting strongly the cell retention time. This can explain also wide retention distribution. Thight control of such defects poses extreme challange for the manufacturing of FBRAM.
{"title":"Origin of wide retention distribution in 1T Floating Body RAM","authors":"M. Aoulaiche, T. Nicoletti, A. Veloso, P. Roussel, E. Simoen, C. Claeys, G. Groeseneken, M. Jurczak","doi":"10.1109/SOI.2012.6404394","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404394","url":null,"abstract":"The variability of 1T FBRAM performances is investigated. The VG read window and the state \"1\" distribution are correlated with the number of holes injected during the write \"1\" related to the electric field in the S/D junctions. Besides, the origin of wide retention time distribution has been correlated with the distribution of G-R center in the Si band gap. Single defect with the Si midgap energy level can generate a leakage path affecting strongly the cell retention time. This can explain also wide retention distribution. Thight control of such defects poses extreme challange for the manufacturing of FBRAM.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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