Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404362
S. Morvan, F. Andrieu, P. Nguyen, J. Hartmann, M. Cassé, C. Tabone, A. Toffoli, F. Allain, W. Schwarzenbach, G. Ghibaudo, B. Nguyen, N. Daval, M. Haond, T. Poiroux, O. Faynot
We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<;100>; or <;110>;). We evidence that pMOSFETs along <;110>; are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (-3GPa) and SiGe S/D improve performances (+133% mobility, +16% ION on 10μm wide devices). This makes the <;110>; orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.
{"title":"Comparison between <100> and <110> oriented channels in highly strained FDSOI pMOSFETs","authors":"S. Morvan, F. Andrieu, P. Nguyen, J. Hartmann, M. Cassé, C. Tabone, A. Toffoli, F. Allain, W. Schwarzenbach, G. Ghibaudo, B. Nguyen, N. Daval, M. Haond, T. Poiroux, O. Faynot","doi":"10.1109/SOI.2012.6404362","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404362","url":null,"abstract":"We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<;100>; or <;110>;). We evidence that pMOSFETs along <;110>; are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (-3GPa) and SiGe S/D improve performances (+133% mobility, +16% ION on 10μm wide devices). This makes the <;110>; orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128254396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404393
O. Thomas, B. Zimmer, B. Pelloux-Prayer, N. Planes, K. Akyel, L. Ciampolini, P. Flatresse, B. Nikolić
Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.
{"title":"6T SRAM design for wide voltage range in 28nm FDSOI","authors":"O. Thomas, B. Zimmer, B. Pelloux-Prayer, N. Planes, K. Akyel, L. Ciampolini, P. Flatresse, B. Nikolić","doi":"10.1109/SOI.2012.6404393","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404393","url":null,"abstract":"Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404395
D. Ioannou, Z. Chbili, A. Z. Badwan, Q. Li, Y. Yang, A. Salman
A new family of well behaved memory cells based on the SOIFED has been described and their operation explained. Their operation relies on modifying the conductivity of the SOI film locally by suitably biasing the gates. They are easier to fabricate and their performance is excellent.
{"title":"Physics and design of a SOI Field-Effect-Diode memory cell","authors":"D. Ioannou, Z. Chbili, A. Z. Badwan, Q. Li, Y. Yang, A. Salman","doi":"10.1109/SOI.2012.6404395","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404395","url":null,"abstract":"A new family of well behaved memory cells based on the SOIFED has been described and their operation explained. Their operation relies on modifying the conductivity of the SOI film locally by suitably biasing the gates. They are easier to fabricate and their performance is excellent.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404398
R. Escoffier, A. Torres, M. Fayolle-Lecocq, C. Buj-Dufournet, E. Morvan, M. Charles, M. Poisson
In order to develop high voltage high current and high temperature HEMT transistors, we have studied an isolated gate based on a thin Al2O3. TCAD simulations have been used to explain abnormal C(V) results depending on the density and localization of positive charges under the gate. We have found and explained the dependence between degradation of Al2O3 interface and electrical characteristics.
{"title":"GaN HEMTs on silicon for power devices","authors":"R. Escoffier, A. Torres, M. Fayolle-Lecocq, C. Buj-Dufournet, E. Morvan, M. Charles, M. Poisson","doi":"10.1109/SOI.2012.6404398","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404398","url":null,"abstract":"In order to develop high voltage high current and high temperature HEMT transistors, we have studied an isolated gate based on a thin Al2O3. TCAD simulations have been used to explain abnormal C(V) results depending on the density and localization of positive charges under the gate. We have found and explained the dependence between degradation of Al2O3 interface and electrical characteristics.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404360
P. Lindner, T. Glinsner, T. Uhrmann, V. Dragoi, T. Plach, T. Matthias, E. Pabo, M. Wimplinger
The continuation of Moore's law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Than Moore” with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into high-volume manufacturing (HVM) putting “More Than Moore” in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques - low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.
{"title":"Key enabling processes for more-than-moore technologies","authors":"P. Lindner, T. Glinsner, T. Uhrmann, V. Dragoi, T. Plach, T. Matthias, E. Pabo, M. Wimplinger","doi":"10.1109/SOI.2012.6404360","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404360","url":null,"abstract":"The continuation of Moore's law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Than Moore” with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into high-volume manufacturing (HVM) putting “More Than Moore” in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques - low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114210798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404371
K. Endo, S. Migita, Y. Ishikawa, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, W. Mizubayashi, Y. Morita, H. Ota, H. Yamauchi, M. Masahara
For the first time, we have successfully fabricated the Vth controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the Vth of the FinFET on the ETBOX is flexibly tuned from low Vth to high Vth with keeping low sub-threshold slope.
{"title":"Flexible Vth FinFETs with 9-nm-thick extremely-thin BOX","authors":"K. Endo, S. Migita, Y. Ishikawa, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, W. Mizubayashi, Y. Morita, H. Ota, H. Yamauchi, M. Masahara","doi":"10.1109/SOI.2012.6404371","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404371","url":null,"abstract":"For the first time, we have successfully fabricated the V<sub>th</sub> controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the V<sub>th</sub> of the FinFET on the ETBOX is flexibly tuned from low V<sub>th</sub> to high V<sub>th</sub> with keeping low sub-threshold slope.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122131756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404381
S. Makovejev, S. Olsen, M. Arshad, D. Flandre, J. Raskin, V. Kilchytska
Frequency dependent behaviour of MOSFETs arises from self-heating and source-to-drain coupling through the substrate. In this work the output conductance variation with frequency is experimentally investigated in FinFETs with various fin widths. We demonstrate that fin narrowing suppresses the output conductance degradation due to the substrate effect in the high-frequency range such that self-heating dominates the output conductance variation. The work thus emphasizes the importance of thermal management and device design in FinFETs.
{"title":"Improvement of high-frequency FinFET performance by fin width engineering","authors":"S. Makovejev, S. Olsen, M. Arshad, D. Flandre, J. Raskin, V. Kilchytska","doi":"10.1109/SOI.2012.6404381","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404381","url":null,"abstract":"Frequency dependent behaviour of MOSFETs arises from self-heating and source-to-drain coupling through the substrate. In this work the output conductance variation with frequency is experimentally investigated in FinFETs with various fin widths. We demonstrate that fin narrowing suppresses the output conductance degradation due to the substrate effect in the high-frequency range such that self-heating dominates the output conductance variation. The work thus emphasizes the importance of thermal management and device design in FinFETs.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115029572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404386
F. Sonnerat, R. Pilard, F. Gianesello, F. Le Pennec, C. Person, D. Gloria
This paper describes a tunable matching network, fully integrated in STMicroelectronics 130 nm CMOS SOI technology. It is able to correct, on the 2500-2690 MHz band, the antenna mismatch of a cellular phone due to the user interaction (for example the hand impact):any VSWR of 5:1 can be reduced to a value lower than 2:1.
{"title":"Innovative tunable antenna solution using CMOS SOI technology","authors":"F. Sonnerat, R. Pilard, F. Gianesello, F. Le Pennec, C. Person, D. Gloria","doi":"10.1109/SOI.2012.6404386","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404386","url":null,"abstract":"This paper describes a tunable matching network, fully integrated in STMicroelectronics 130 nm CMOS SOI technology. It is able to correct, on the 2500-2690 MHz band, the antenna mismatch of a cellular phone due to the user interaction (for example the hand impact):any VSWR of 5:1 can be reduced to a value lower than 2:1.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404387
A. Mattamana, K. Groves, P. Orlando, V. Patel, T. Quach, P. Watson, L. Johnson, P. Wyatt, C. Chen, C. Chen, R. Drangmeister, C. Keast
This paper reports on the successful demonstration of radio frequency (RF) components in support of an integrated wide band/high dynamic range X-band receiver in 180-nm fully-depleted (FD) SOI CMOS technology. The demonstrated microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier (LNA), Marchand balun, balanced amplifiers, double balanced mixer, non-reflective filter, and an IF amplifier. The X-band receiver front end module yielded a gain of 13.5-15 dB, 5.2-5.8 dB noise figure (NF), across the frequency band (3.7-4.3 GHz).
本文报道了在180nm全耗尽(FD) SOI CMOS技术中支持集成宽带/高动态范围x波段接收器的射频(RF)组件的成功演示。所演示的微波单片集成电路(MMIC)包括x波段低噪声放大器(LNA)、马尔尚平衡、平衡放大器、双平衡混频器、非反射滤波器和中频放大器。x波段接收器前端模块在整个频段(3.7-4.3 GHz)的增益为13.5-15 dB，噪声系数(NF)为5.2-5.8 dB。
{"title":"X-band receiver module in fully depleted silicon on insulator technology","authors":"A. Mattamana, K. Groves, P. Orlando, V. Patel, T. Quach, P. Watson, L. Johnson, P. Wyatt, C. Chen, C. Chen, R. Drangmeister, C. Keast","doi":"10.1109/SOI.2012.6404387","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404387","url":null,"abstract":"This paper reports on the successful demonstration of radio frequency (RF) components in support of an integrated wide band/high dynamic range X-band receiver in 180-nm fully-depleted (FD) SOI CMOS technology. The demonstrated microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier (LNA), Marchand balun, balanced amplifiers, double balanced mixer, non-reflective filter, and an IF amplifier. The X-band receiver front end module yielded a gain of 13.5-15 dB, 5.2-5.8 dB noise figure (NF), across the frequency band (3.7-4.3 GHz).","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121695910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404377
M. de Souza, V. Kilchtyska, D. Flandre, M. Pavanello
This work reports, for the first time, experimental results of asymmetric self-cascode FD SOI n and pMOSFETs operating at liquid helium temperature. The results show that the improved analog performance obtained by this architecture at room temperature is maintained even for such extreme low temperature, promoting the reduction of impact ionization and parasitic bipolar effects, which may even be suppressed, depending on the threshold voltages of the devices. Although the use of A-SC may cause a small (5-10% for nMOS devices) decrease of the unit-gain frequency at certain bias conditions, the output conductance reduction in A-SC results in the rise of the intrinsic voltage gain that has shown to increase by up to 32 dB and 30 dB for A-SC n and pMOSFETs, respectively, in comparison to ST at 4.2K. The gain improvement at 4.2K has shown to be larger than at 300K at the same current level.
{"title":"Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs","authors":"M. de Souza, V. Kilchtyska, D. Flandre, M. Pavanello","doi":"10.1109/SOI.2012.6404377","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404377","url":null,"abstract":"This work reports, for the first time, experimental results of asymmetric self-cascode FD SOI n and pMOSFETs operating at liquid helium temperature. The results show that the improved analog performance obtained by this architecture at room temperature is maintained even for such extreme low temperature, promoting the reduction of impact ionization and parasitic bipolar effects, which may even be suppressed, depending on the threshold voltages of the devices. Although the use of A-SC may cause a small (5-10% for nMOS devices) decrease of the unit-gain frequency at certain bias conditions, the output conductance reduction in A-SC results in the rise of the intrinsic voltage gain that has shown to increase by up to 32 dB and 30 dB for A-SC n and pMOSFETs, respectively, in comparison to ST at 4.2K. The gain improvement at 4.2K has shown to be larger than at 300K at the same current level.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131867134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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