Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404356
A. Brown, N. Daval, K. Bourdelle, B. Nguyen, A. Asenov
3D devices are prone to more complex sources of variability than conventional planar bulk and SOI MOSFETs. Corner simulations and statistical simulations are unique tools to understand the link between the device design and the circuit performance through accurate prediction of the variability. In this work we have demonstrated that SOI can efficiently help to reduce the process-induced FinFET variability, and hence improve the circuit performance. In particular, the better fin height control possible with SOI results in less variability in on-current. We have also established that SOI brings >;5% Isat improvement at identical Fin dimensions, thanks to the BOX isolation compared to the junction isolation depleting the bottom part of the bulk Fin.
{"title":"Simulation analysis of process-induced variability in nanoscale SOI and bulk FinFETs","authors":"A. Brown, N. Daval, K. Bourdelle, B. Nguyen, A. Asenov","doi":"10.1109/SOI.2012.6404356","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404356","url":null,"abstract":"3D devices are prone to more complex sources of variability than conventional planar bulk and SOI MOSFETs. Corner simulations and statistical simulations are unique tools to understand the link between the device design and the circuit performance through accurate prediction of the variability. In this work we have demonstrated that SOI can efficiently help to reduce the process-induced FinFET variability, and hence improve the circuit performance. In particular, the better fin height control possible with SOI results in less variability in on-current. We have also established that SOI brings >;5% Isat improvement at identical Fin dimensions, thanks to the BOX isolation compared to the junction isolation depleting the bottom part of the bulk Fin.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"30 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129399504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404365
S. Markov, A. Zain, B. Cheng, A. Asenov
Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems [1]. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), metal gate granularity (MGG) leading to work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI [2-4]. The different physical nature of these phenomena affects the spread of threshold voltage (Vth), on-current (Ion), and DIBL of the transistors in different ways, and is, for the first time, comprehensively studied here for three LOP-technology generations of n-channel UTB-FD-SOI devices with a physical gate length LG of 22, 16, and 11 nm.
{"title":"Statistical variability in scaled generations of n-channel UTB-FD-SOI MOSFETs under the influence of RDF, LER, OTF and MGG","authors":"S. Markov, A. Zain, B. Cheng, A. Asenov","doi":"10.1109/SOI.2012.6404365","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404365","url":null,"abstract":"Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems [1]. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), metal gate granularity (MGG) leading to work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI [2-4]. The different physical nature of these phenomena affects the spread of threshold voltage (Vth), on-current (Ion), and DIBL of the transistors in different ways, and is, for the first time, comprehensively studied here for three LOP-technology generations of n-channel UTB-FD-SOI devices with a physical gate length LG of 22, 16, and 11 nm.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115399867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404388
Jing Chen, Tao Yu, Jiexin Luo, Qingqing Wu, Z. Chai, Xi Wang
The influence of back-gate bias on DC and RF characteristics in C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) was investigated. The experimental result indicates that a positive substrate bias is very effective in RC and hysteresis reduction, and further improves the maximum fT from 16 to 53GHz. Analytical relationships are developed to quantify the impact of substrate bias on electrical characteristics, which further approved by calibrated Sentaurus simulations.
{"title":"Impact of back-gate bias on DC and RF characteristics in SiGe:C HBTs fabricated on thin-film SOI","authors":"Jing Chen, Tao Yu, Jiexin Luo, Qingqing Wu, Z. Chai, Xi Wang","doi":"10.1109/SOI.2012.6404388","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404388","url":null,"abstract":"The influence of back-gate bias on DC and RF characteristics in C-doped SiGe HBTs (SiGe:C HBTs) on thin-film silicon-on-insulator (SOI) was investigated. The experimental result indicates that a positive substrate bias is very effective in RC and hysteresis reduction, and further improves the maximum fT from 16 to 53GHz. Analytical relationships are developed to quantify the impact of substrate bias on electrical characteristics, which further approved by calibrated Sentaurus simulations.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127120070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404359
D. Patel
□ The fabless semiconductor industry has provided enourmous innovation and cost reduction over the past 21 years □ The growth in mobile computing and connectivity indicates that semiconductor opportunities will continue to increase □ Power efficiency is a key focus area for SoC designers as they deliver ICs into these market segments □ SOI technology and fully depleted devices have potential to provide increase performance at reduced power budgets.
{"title":"ARM physical IP overview","authors":"D. Patel","doi":"10.1109/SOI.2012.6404359","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404359","url":null,"abstract":"□ The fabless semiconductor industry has provided enourmous innovation and cost reduction over the past 21 years □ The growth in mobile computing and connectivity indicates that semiconductor opportunities will continue to increase □ Power efficiency is a key focus area for SoC designers as they deliver ICs into these market segments □ SOI technology and fully depleted devices have potential to provide increase performance at reduced power budgets.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126965151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404402
J. Muldavin, C. Bozler, D. Yost, C. Chen, P. Wyatt
Silicon on Insulator (SOI) Technologies offer many advantages for the fabrication and advanced packaging of MEMS and IC devices and systems. The buried oxide provides an excellent etch stop and the silicon layers on top can be selected for the exact thickness, crystal orientation, and purity for the required application. These properties are exploited for the fabrication and packaging of MEMS devices as well as for 3D integration of SOI CMOS and flexible electronics. Particular examples from work done at MIT Lincoln Laboratory over the last 10 years will be included.
{"title":"SOI for MEMS and advanced packaging","authors":"J. Muldavin, C. Bozler, D. Yost, C. Chen, P. Wyatt","doi":"10.1109/SOI.2012.6404402","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404402","url":null,"abstract":"Silicon on Insulator (SOI) Technologies offer many advantages for the fabrication and advanced packaging of MEMS and IC devices and systems. The buried oxide provides an excellent etch stop and the silicon layers on top can be selected for the exact thickness, crystal orientation, and purity for the required application. These properties are exploited for the fabrication and packaging of MEMS devices as well as for 3D integration of SOI CMOS and flexible electronics. Particular examples from work done at MIT Lincoln Laboratory over the last 10 years will be included.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121072978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404376
S. O'Uchi, K. Endo, M. Maezawa, T. Nakagawa, H. Ota, Y. Liu, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, W. Mizubayashi, S. Migita, Y. Morita, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara
Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I-V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
{"title":"Cryogenic operation of double-gate FinFET and demonstration of analog circuit at 4.2K","authors":"S. O'Uchi, K. Endo, M. Maezawa, T. Nakagawa, H. Ota, Y. Liu, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, W. Mizubayashi, S. Migita, Y. Morita, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara","doi":"10.1109/SOI.2012.6404376","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404376","url":null,"abstract":"Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I-V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114573727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404390
Namhoon Kim, C. Shin, D. Wu, Joong-Ho Kim, P. Wu
In this paper, the stacked silicon interconnect technology in FPGA system is introduced, which needs to be accurately modelled over high frequency by considering numerous design requirements. The stacked silicon interposer includes a lot of TSVs for high speed signals. Designs without the consideration of high frequency effects of TSV will degrade the rise/fall time of a signal, increase crosstalk and noise injection, and cause significant performance degradation on high speed channels. The routing metal loss in Under Bump Metallurgy (UBM) layer is also analyzed and simulated. Performance enhancement by using SOI wafer is shown and compared against conventional wafers.
{"title":"Performance analysis and optimization for silicon interposer with Through Silicon Via (TSV)","authors":"Namhoon Kim, C. Shin, D. Wu, Joong-Ho Kim, P. Wu","doi":"10.1109/SOI.2012.6404390","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404390","url":null,"abstract":"In this paper, the stacked silicon interconnect technology in FPGA system is introduced, which needs to be accurately modelled over high frequency by considering numerous design requirements. The stacked silicon interposer includes a lot of TSVs for high speed signals. Designs without the consideration of high frequency effects of TSV will degrade the rise/fall time of a signal, increase crosstalk and noise injection, and cause significant performance degradation on high speed channels. The routing metal loss in Under Bump Metallurgy (UBM) layer is also analyzed and simulated. Performance enhancement by using SOI wafer is shown and compared against conventional wafers.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404368
A. Perin, R. Giacomini
The best-explored integrated magnetic field sensors are built with planar IC technologies, which do not allow 3D sensing in standard fabrication processes due to their bi-dimensional nature. Unlike planar devices, FinFETs can be used to sense magnetic fields in any direction. This work proposes and evaluates the use of FinFETs as magnetic sensors. The sensibility of FinFET differential arrays to lateral and vertical magnetic fields is quantified. This work also proposes the L-shaped gate, to improve the sensor performance.
{"title":"Sensing magnetic fields in any direction using FinFETs and L-gate FinFETs","authors":"A. Perin, R. Giacomini","doi":"10.1109/SOI.2012.6404368","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404368","url":null,"abstract":"The best-explored integrated magnetic field sensors are built with planar IC technologies, which do not allow 3D sensing in standard fabrication processes due to their bi-dimensional nature. Unlike planar devices, FinFETs can be used to sense magnetic fields in any direction. This work proposes and evaluates the use of FinFETs as magnetic sensors. The sensibility of FinFET differential arrays to lateral and vertical magnetic fields is quantified. This work also proposes the L-shaped gate, to improve the sensor performance.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"776 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126769897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404403
W. Lepkowski, S. Wilk, M. R. Ghajar, T. Thornton
Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.
{"title":"High voltage SOI MESFETs at the 45nm technology node","authors":"W. Lepkowski, S. Wilk, M. R. Ghajar, T. Thornton","doi":"10.1109/SOI.2012.6404403","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404403","url":null,"abstract":"Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114225322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404374
N. Rezzak, E. Zhang, D. Ball, M. Alles, T. D. Loveless, peixiong zhao, K. Rodbell
TID-induced changes in 32 nm PD SOI devices depend on the device variant: low VT devices show minor increased in leakage, high VT devices show negligible change. Simulated sensitivity of TID to the gate work function of the high-k metal gate and associated doping changes confirm that the body doping remains high and generally mitigates TID sensitivity. Preliminary ring oscillator measurements show no measurable change in supply current or frequency with TID. Specially designed experimental 45 nm SOI FDSOI devices exhibit a pronounced TID-induced VT shift due to the coupling with the BOX layer.
在32 nm PD SOI器件中，tid引起的变化取决于器件的变化:低VT器件的泄漏量略有增加，高VT器件的变化可以忽略不计。模拟的TID对高k金属栅极栅功函数的灵敏度和相关的掺杂变化证实，体掺杂仍然很高，通常会减轻TID的灵敏度。初步环形振荡器测量显示没有可测量的变化，电源电流或频率与TID。特别设计的45 nm SOI FDSOI器件由于与BOX层的耦合而表现出明显的tid诱导VT位移。
{"title":"Total-ionizing-dose radiation response of 32 nm partially and 45 nm fully-depleted SOI devices","authors":"N. Rezzak, E. Zhang, D. Ball, M. Alles, T. D. Loveless, peixiong zhao, K. Rodbell","doi":"10.1109/SOI.2012.6404374","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404374","url":null,"abstract":"TID-induced changes in 32 nm PD SOI devices depend on the device variant: low VT devices show minor increased in leakage, high VT devices show negligible change. Simulated sensitivity of TID to the gate work function of the high-k metal gate and associated doping changes confirm that the body doping remains high and generally mitigates TID sensitivity. Preliminary ring oscillator measurements show no measurable change in supply current or frequency with TID. Specially designed experimental 45 nm SOI FDSOI devices exhibit a pronounced TID-induced VT shift due to the coupling with the BOX layer.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114639178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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