Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404389
Y. Moghe, A. Terry, D. Luzon
In this paper we describe a dual-channel, monolithic, capacitive digital isolator on 0.5μm SOS, with a measured single-channel maximum speed of 640Mbps at 3.3V supply -more than 2X better than all previously reported commercial and academic literature. We report 1.8V-compatible operation for the first time, achieving a top speed of 260Mbps; which exceeds the 3.3V performance of all previously reported designs. Current draw (85μA/Mbps at 3.3V) and galvanic isolation level (2.5kV RMS) are competitive with commercial offerings.
{"title":"Monolithic 2.5kV RMS, 1.8V–3.3V dual-channel 640Mbps digital isolator in 0.5μm SOS","authors":"Y. Moghe, A. Terry, D. Luzon","doi":"10.1109/SOI.2012.6404389","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404389","url":null,"abstract":"In this paper we describe a dual-channel, monolithic, capacitive digital isolator on 0.5μm SOS, with a measured single-channel maximum speed of 640Mbps at 3.3V supply -more than 2X better than all previously reported commercial and academic literature. We report 1.8V-compatible operation for the first time, achieving a top speed of 260Mbps; which exceeds the 3.3V performance of all previously reported designs. Current draw (85μA/Mbps at 3.3V) and galvanic isolation level (2.5kV RMS) are competitive with commercial offerings.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404366
Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.
{"title":"Experimental study of tri-gate SOI-FinFET flash memory","authors":"Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara","doi":"10.1109/SOI.2012.6404366","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404366","url":null,"abstract":"It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124936697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404384
R. Trevisoli, R. Doria, M. de Souza, I. Ferain, S. Das, M. Pavanello
This work presented an evaluation of the zero temperature coefficient bias in Junctionless Nanowire Transistors. Contrarily to results of previous works, this paper shows that JNTs can present a ZTC point, which depends on the series resistance and its dependence on the temperature.
{"title":"The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors","authors":"R. Trevisoli, R. Doria, M. de Souza, I. Ferain, S. Das, M. Pavanello","doi":"10.1109/SOI.2012.6404384","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404384","url":null,"abstract":"This work presented an evaluation of the zero temperature coefficient bias in Junctionless Nanowire Transistors. Contrarily to results of previous works, this paper shows that JNTs can present a ZTC point, which depends on the series resistance and its dependence on the temperature.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404399
S. Spector, R. Swint, C. Chen, J. Plant, T. Lyszczarz, P. Juodawlkis
Optical amplifiers are demonstrated by direct bonding III-V gain layers to SOI waveguides which include 2-D and 3-D adiabatic tapers. The 3-D tapers have a low loss of 0.1 dB per mode conversion, the lowest demonstrated for coupling between SOI waveguides of this type. The 2-D tapers are used to control interaction with the III-V gain region. An integrated amplifier delivered 14 dB intra chip gain using the new adiabatic tapered waveguides.
{"title":"Mode engineering for hybrid SOI/III-V optical devices","authors":"S. Spector, R. Swint, C. Chen, J. Plant, T. Lyszczarz, P. Juodawlkis","doi":"10.1109/SOI.2012.6404399","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404399","url":null,"abstract":"Optical amplifiers are demonstrated by direct bonding III-V gain layers to SOI waveguides which include 2-D and 3-D adiabatic tapers. The 3-D tapers have a low loss of 0.1 dB per mode conversion, the lowest demonstrated for coupling between SOI waveguides of this type. The 2-D tapers are used to control interaction with the III-V gain region. An integrated amplifier delivered 14 dB intra chip gain using the new adiabatic tapered waveguides.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123901217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404382
H. Takei, K. Yoshinaga, Y. Sano, S. Matsuyama, K. Yamauchi
The processing accuracy was improved by balancing out the wafer temperature using the cooling system and regulating the rf power by constantly measuring the electrode potential during processing.
利用冷却系统平衡晶圆温度，在加工过程中通过不断测量电极电位来调节射频功率，提高了加工精度。
{"title":"Improving the accuracy of numerically controlled sacrificial plasma oxidation using array of electrodes to improve the thickness uniformity of SOI","authors":"H. Takei, K. Yoshinaga, Y. Sano, S. Matsuyama, K. Yamauchi","doi":"10.1109/SOI.2012.6404382","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404382","url":null,"abstract":"The processing accuracy was improved by balancing out the wafer temperature using the cooling system and regulating the rf power by constantly measuring the electrode potential during processing.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124647664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404354
K. Ikeda, Y. Moriyama, M. Ono, Y. Kamimuta, T. Irisawa, Y. Kamata, A. Sakai, T. Tezuka
For the first time, fabrication of TBB-GOI MOSFETs and substantial Vth shifts within 1V back biasing have been demonstrated. The Vth control by extremely low back-gate biases was achieved by using the EOT-scaled BOX structure of ~12nm. This sub-1V back-gate biasing scheme can reduce the power consumption in LSIs without optional voltage supply or charge pump circuits which have large impact to reducing chip size and process cost.
{"title":"First demonstration of threshold voltage control by sub-1V back-gate biasing for thin body and buried-oxide (TBB) Ge-on-insulator (GOI) MOSFETs for low-power operation","authors":"K. Ikeda, Y. Moriyama, M. Ono, Y. Kamimuta, T. Irisawa, Y. Kamata, A. Sakai, T. Tezuka","doi":"10.1109/SOI.2012.6404354","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404354","url":null,"abstract":"For the first time, fabrication of TBB-GOI MOSFETs and substantial Vth shifts within 1V back biasing have been demonstrated. The Vth control by extremely low back-gate biases was achieved by using the EOT-scaled BOX structure of ~12nm. This sub-1V back-gate biasing scheme can reduce the power consumption in LSIs without optional voltage supply or charge pump circuits which have large impact to reducing chip size and process cost.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128636613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404404
K. Ben Ali, C. Roda Neve, A. Gharsallah, J. Raskin
In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.
在本文中，我们旨在比较在SOITEC提供的标准或富陷阱的ir -SOI UNIBOND晶圆上制造的无源和有源完全耗尽(FD) SOI mosfet的静态和射频性能。
{"title":"RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer","authors":"K. Ben Ali, C. Roda Neve, A. Gharsallah, J. Raskin","doi":"10.1109/SOI.2012.6404404","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404404","url":null,"abstract":"In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125736207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404392
N. Rodriguez, C. Navarro, F. Gámiz, F. Andrieu, O. Faynot, S. Cristoloveanu
The A2RAM memory cell has been fabricated and its operation demonstrated experimentally for the first time. The retrograde P-N channel doping allows the separation of electrons and holes in very thin films. We have documented attractive performance in terms of current margin, retention time, variability and cell disturbance immunity without any additional source/drain implantation optimization compared to logic transistor integration.
{"title":"Experimental demonstration of A2RAM memory cell on SOI","authors":"N. Rodriguez, C. Navarro, F. Gámiz, F. Andrieu, O. Faynot, S. Cristoloveanu","doi":"10.1109/SOI.2012.6404392","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404392","url":null,"abstract":"The A2RAM memory cell has been fabricated and its operation demonstrated experimentally for the first time. The retrograde P-N channel doping allows the separation of electrons and holes in very thin films. We have documented attractive performance in terms of current margin, retention time, variability and cell disturbance immunity without any additional source/drain implantation optimization compared to logic transistor integration.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123588379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404353
T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Ishihara, M. Hata, T. Tezuka
We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (Wfin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that Wfin scaling effectively improved cut-off properties at Nd up to 5 × 1018 cm-3 and the electron mobility in the narrowest channel (Wfin = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% Ion enhancement without Ioff degradation.
{"title":"High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications","authors":"T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Ishihara, M. Hata, T. Tezuka","doi":"10.1109/SOI.2012.6404353","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404353","url":null,"abstract":"We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (W<sub>fin</sub>) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that W<sub>fin</sub> scaling effectively improved cut-off properties at N<sub>d</sub> up to 5 × 10<sup>18</sup> cm<sup>-3</sup> and the electron mobility in the narrowest channel (W<sub>fin</sub> = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% I<sub>on</sub> enhancement without I<sub>off</sub> degradation.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129844005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404361
M. Haond
The race towards further density increase in CMOS circuit integration is entering a new era where choices are needed for the device shrink. Beyond 20nm, a consensus says that MOSFETs will go fully depleted. They can either be 2D or 3D, i.e. 2D fully depleted silicon films on Oxide (FDSOI) or 3D with fully depleted silicon fins. We believe that FDSOI films allow continuing smoothly Moore's Law without introducing drastic design disruptive steps. We have developed FDSOI Process and Design Platforms that are in the shrink trend from previous generations. Moreover, since FDSOI devices are compatible with the Bulk design rules and constraints, it becomes possible, within the same technology node, to hit the performance boost usually targeted with the next one. This has become of utmost importance today where the introduction of a new node gets complex and costly because of the delay to get appropriate advanced Lithography tools. In this presentation, we review the challenges for the 20nm FDSOI nodes by looking at performance, power and process complexity.
{"title":"20 nm FDSOI process and design platforms for high performance/ low power systems on chip","authors":"M. Haond","doi":"10.1109/SOI.2012.6404361","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404361","url":null,"abstract":"The race towards further density increase in CMOS circuit integration is entering a new era where choices are needed for the device shrink. Beyond 20nm, a consensus says that MOSFETs will go fully depleted. They can either be 2D or 3D, i.e. 2D fully depleted silicon films on Oxide (FDSOI) or 3D with fully depleted silicon fins. We believe that FDSOI films allow continuing smoothly Moore's Law without introducing drastic design disruptive steps. We have developed FDSOI Process and Design Platforms that are in the shrink trend from previous generations. Moreover, since FDSOI devices are compatible with the Bulk design rules and constraints, it becomes possible, within the same technology node, to hit the performance boost usually targeted with the next one. This has become of utmost importance today where the introduction of a new node gets complex and costly because of the delay to get appropriate advanced Lithography tools. In this presentation, we review the challenges for the 20nm FDSOI nodes by looking at performance, power and process complexity.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133288444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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