Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404403
W. Lepkowski, S. Wilk, M. R. Ghajar, T. Thornton
Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.
{"title":"High voltage SOI MESFETs at the 45nm technology node","authors":"W. Lepkowski, S. Wilk, M. R. Ghajar, T. Thornton","doi":"10.1109/SOI.2012.6404403","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404403","url":null,"abstract":"Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114225322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404368
A. Perin, R. Giacomini
The best-explored integrated magnetic field sensors are built with planar IC technologies, which do not allow 3D sensing in standard fabrication processes due to their bi-dimensional nature. Unlike planar devices, FinFETs can be used to sense magnetic fields in any direction. This work proposes and evaluates the use of FinFETs as magnetic sensors. The sensibility of FinFET differential arrays to lateral and vertical magnetic fields is quantified. This work also proposes the L-shaped gate, to improve the sensor performance.
{"title":"Sensing magnetic fields in any direction using FinFETs and L-gate FinFETs","authors":"A. Perin, R. Giacomini","doi":"10.1109/SOI.2012.6404368","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404368","url":null,"abstract":"The best-explored integrated magnetic field sensors are built with planar IC technologies, which do not allow 3D sensing in standard fabrication processes due to their bi-dimensional nature. Unlike planar devices, FinFETs can be used to sense magnetic fields in any direction. This work proposes and evaluates the use of FinFETs as magnetic sensors. The sensibility of FinFET differential arrays to lateral and vertical magnetic fields is quantified. This work also proposes the L-shaped gate, to improve the sensor performance.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"776 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126769897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404358
J. Wang
Energy efficiency, performance and cost are major challenges facing the electronic, solar energy, and lighting industries. We will look at how fundamental innovations in engineered substrates from Soitec can solve complex technology challenges and enable paradigm shifts in support of customers' success.
{"title":"Simply fundamental innovation for complex technology challenges — Case of smarttools","authors":"J. Wang","doi":"10.1109/SOI.2012.6404358","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404358","url":null,"abstract":"Energy efficiency, performance and cost are major challenges facing the electronic, solar energy, and lighting industries. We will look at how fundamental innovations in engineered substrates from Soitec can solve complex technology challenges and enable paradigm shifts in support of customers' success.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132326776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404351
K. Torki
□ CMP created in 1981 □ Offering industrial quality process lines (University process lines cannot offer a stable yield) □ Design-kits linking CAD and processes, to facilitate the design. □ Customer base development + Universities / Research Labs + Industry + 1000 Institutions in 70 countries □ Non-profit, Non-sponsored.
{"title":"28nm FDSOI offer for academia and industry","authors":"K. Torki","doi":"10.1109/SOI.2012.6404351","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404351","url":null,"abstract":"□ CMP created in 1981 □ Offering industrial quality process lines (University process lines cannot offer a stable yield) □ Design-kits linking CAD and processes, to facilitate the design. □ Customer base development + Universities / Research Labs + Industry + 1000 Institutions in 70 countries □ Non-profit, Non-sponsored.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131015195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404397
F. Allibert, K. Cheng, M. Vinet, W. Schwarzenbach, A. Khakifirooz, L. Ecarnot, B. Nguyen, B. Doris
We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.
{"title":"Evaluation of sSOI wafers for 22nm node and beyond","authors":"F. Allibert, K. Cheng, M. Vinet, W. Schwarzenbach, A. Khakifirooz, L. Ecarnot, B. Nguyen, B. Doris","doi":"10.1109/SOI.2012.6404397","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404397","url":null,"abstract":"We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134455754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404363
L. Grenouillet, P. Khare, J. Gimbert, M. Hargrove, M. Jaud, Q. Liu, Y. Le Tiec, R. Wacquez, N. Loubet, K. Cheng, S. Holmes, S. Liu, T. Hook, S. Teehan, J. Guilford, S. Schmitz, P. Kulkarni, J. Kuss, M. Terrizzi, S. Luning, B. Doris, M. Vinet
Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.
{"title":"Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide","authors":"L. Grenouillet, P. Khare, J. Gimbert, M. Hargrove, M. Jaud, Q. Liu, Y. Le Tiec, R. Wacquez, N. Loubet, K. Cheng, S. Holmes, S. Liu, T. Hook, S. Teehan, J. Guilford, S. Schmitz, P. Kulkarni, J. Kuss, M. Terrizzi, S. Luning, B. Doris, M. Vinet","doi":"10.1109/SOI.2012.6404363","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404363","url":null,"abstract":"Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134479924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404369
N. Xu, C. Shin, F. Andrieu, B. Ho, W. Xiong, O. Weber, T. Poiroux, B. Nguyen, Munkang Choi, V. Moroz, O. Faynot, T. Liu
Strain-induced mobility enhancement in thin-body MOSFETs is studied and the impact of silicon body thickness scaling on piezoresistance coefficients is analyzed to facilitate stress engineering for these advanced transistor structures. Various stressors are benchmarked in terms of their effectiveness to enhance nanometer-gate-length thin-body MOSFET performance.
{"title":"Effectiveness of strained-Si technology for thin-body MOSFETs","authors":"N. Xu, C. Shin, F. Andrieu, B. Ho, W. Xiong, O. Weber, T. Poiroux, B. Nguyen, Munkang Choi, V. Moroz, O. Faynot, T. Liu","doi":"10.1109/SOI.2012.6404369","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404369","url":null,"abstract":"Strain-induced mobility enhancement in thin-body MOSFETs is studied and the impact of silicon body thickness scaling on piezoresistance coefficients is analyzed to facilitate stress engineering for these advanced transistor structures. Various stressors are benchmarked in terms of their effectiveness to enhance nanometer-gate-length thin-body MOSFET performance.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404391
S. Cristoloveanu, M. Bawedin, J. Wan, S. Chang, C. Navarro, A. Zaslavsky, C. Le Royer, F. Andrieu, N. Rodriguez, F. Gámiz
While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that are usually regarded as parasitic phenomena.
{"title":"Innovative capacitorless SOI DRAMs","authors":"S. Cristoloveanu, M. Bawedin, J. Wan, S. Chang, C. Navarro, A. Zaslavsky, C. Le Royer, F. Andrieu, N. Rodriguez, F. Gámiz","doi":"10.1109/SOI.2012.6404391","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404391","url":null,"abstract":"While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that are usually regarded as parasitic phenomena.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SOI.2012.6404364
M. Horstmann, J. Hoentschel, J. Schaeffer
A foundry's mission is to deliver competitive device performance and flexibility to support a variety of SoC offerings. The restrictive lithography and process requirements at the 20nm technology limit harvesting the density and scaling benefits of the gate first approach and drive the concept change to gate last processing. This technology pushes conventional scaling to its challenging limits. Beyond 20nm new device concepts need to be employed where FinFETs and ET-SOI devices serving well candidates for new advanced CMOS technologies.
{"title":"Taking the next step on advanced HKMG SOI technologies — From 32nm PD SOI volume production to 28nm FD SOI and beyond","authors":"M. Horstmann, J. Hoentschel, J. Schaeffer","doi":"10.1109/SOI.2012.6404364","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404364","url":null,"abstract":"A foundry's mission is to deliver competitive device performance and flexibility to support a variety of SoC offerings. The restrictive lithography and process requirements at the 20nm technology limit harvesting the density and scaling benefits of the gate first approach and drive the concept change to gate last processing. This technology pushes conventional scaling to its challenging limits. Beyond 20nm new device concepts need to be employed where FinFETs and ET-SOI devices serving well candidates for new advanced CMOS technologies.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130839488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOI.2012.6404372
C. Claeys, M. Aoulaiche, E. Simoen, A. Griffoni, D. Kobayashi, N. Mahatme, R. Reed, peixiong zhao, P. Agopian, J. Martino
The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied [2]. Although manufacturing issues have delayed their introduction in production lines, FinFET and MuGFET structures are presently being used for 22 nm technologies. The use of SOI devices leads to an improved radiation performance concerning single event upsets and latch-up [3], but can become worse for micro-dose effects and from a total ionizing dose point of view because of the radiation-induced interface states and trapped charge in the buried oxide [4].
{"title":"Radiation hardness aspects of advanced FinFET and UTBOX devices","authors":"C. Claeys, M. Aoulaiche, E. Simoen, A. Griffoni, D. Kobayashi, N. Mahatme, R. Reed, peixiong zhao, P. Agopian, J. Martino","doi":"10.1109/SOI.2012.6404372","DOIUrl":"https://doi.org/10.1109/SOI.2012.6404372","url":null,"abstract":"The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied [2]. Although manufacturing issues have delayed their introduction in production lines, FinFET and MuGFET structures are presently being used for 22 nm technologies. The use of SOI devices leads to an improved radiation performance concerning single event upsets and latch-up [3], but can become worse for micro-dose effects and from a total ionizing dose point of view because of the radiation-induced interface states and trapped charge in the buried oxide [4].","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"95 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113960761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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