Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549384
Siong Kiong Teng, N. Soin
In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate's enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of the clock tree. The effective splitting of the clock gate to the lower level of the clock tree will improve the clock gate skew and thus improve the setup margin.
{"title":"Regional clock gate splitting algorithm for clock tree synthesis","authors":"Siong Kiong Teng, N. Soin","doi":"10.1109/SMELEC.2010.5549384","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549384","url":null,"abstract":"In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate's enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of the clock tree. The effective splitting of the clock gate to the lower level of the clock tree will improve the clock gate skew and thus improve the setup margin.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549568
Aidhia Rahmi, A. Umar, M. M. Salleh, B. Majlis, M. Yahya
This paper reports the synthesis and characterization of CdTe system in the ternary surfactant mixture. The quantum dots was prepared by quick injection of tri-n-octylphosphine telluride (TOPTe) into reactor that contains a hot mixed cadmium acetate hydrate, 1-octadecene, n-octadecyl phosphoric acid (ODPA), octadecylamine (ODA) and oleic acid (OA). We found that the surfactant of ODPA, OA and ODA were very important for the enhancement at the Photoluminescence (PL) properties CdTe quantum dots.
{"title":"Enhanced-photoluminescence properties of CdTe quantum dots prepared from the ternary surfactant mixture system","authors":"Aidhia Rahmi, A. Umar, M. M. Salleh, B. Majlis, M. Yahya","doi":"10.1109/SMELEC.2010.5549568","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549568","url":null,"abstract":"This paper reports the synthesis and characterization of CdTe system in the ternary surfactant mixture. The quantum dots was prepared by quick injection of tri-n-octylphosphine telluride (TOPTe) into reactor that contains a hot mixed cadmium acetate hydrate, 1-octadecene, n-octadecyl phosphoric acid (ODPA), octadecylamine (ODA) and oleic acid (OA). We found that the surfactant of ODPA, OA and ODA were very important for the enhancement at the Photoluminescence (PL) properties CdTe quantum dots.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549552
S. Hatta, N. Soin, J. F. Zhang
This paper presents the effects of process variation on the Negative Bias Temperature Instabilities (NBTI) of a 90nm PMOSFET. The process parameters which are varied in this work are the stress temperature and the hydrogen diffusivity. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and the drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At elevated temperatures, the PMOS transistor shows a higher interface trap concentration and a considerable drift in the threshold voltage along with significant degradation in the drain current, when a large negative bias is applied.
{"title":"The effect of process variation on NBTI degradation in 90nm PMOS","authors":"S. Hatta, N. Soin, J. F. Zhang","doi":"10.1109/SMELEC.2010.5549552","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549552","url":null,"abstract":"This paper presents the effects of process variation on the Negative Bias Temperature Instabilities (NBTI) of a 90nm PMOSFET. The process parameters which are varied in this work are the stress temperature and the hydrogen diffusivity. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and the drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At elevated temperatures, the PMOS transistor shows a higher interface trap concentration and a considerable drift in the threshold voltage along with significant degradation in the drain current, when a large negative bias is applied.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114279765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549438
M. Salina, M. Z. Sahdan, R. Ahmad, M. Rusop
Sol-gel method with spin coating technique has been used to deposit the MgxZnx−1O (0.0
采用溶胶-凝胶法制备了MgxZnx−10o (0.0
{"title":"Study on the effect of metal contact (Pt, Pd and Au) to the electrical and physical properties of MgxZnx−1O thin film for FET applications","authors":"M. Salina, M. Z. Sahdan, R. Ahmad, M. Rusop","doi":"10.1109/SMELEC.2010.5549438","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549438","url":null,"abstract":"Sol-gel method with spin coating technique has been used to deposit the MgxZnx−1O (0.0<x<0.3) thin film. By using silicon as a substrate, this thin film being deposited and being annealed at 550°C in an hour. This is done to investigate the consequences of a different dopant concentration with different metal contact to the electrical and physical properties of the thin film. The IV characteristic has been investigated using IV probe measurement system and the physical properties being analyzed by using FESEM and AFM machine. The result shows that the higher percentage of dopant gave bigger size to the grain. The conductivity of the thin film also decreased and gave a different reading for different metal contact.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126662935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549475
Milad Abtin, P. Keshavarzi, K. Jaferzadeh, A. Naderi
The minimum feature size of the transistors will be decreases in the future years as predicted by the international technology roadmap for semiconductors. Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime when considering the low scale effects is important for decreasing the scale. Solving and simulating the equations of these devices are so complicated and time consuming. In this paper we use RBF network for simulating the I-V characteristics of common symmetric multi gate FinFETs by using some BSIM-CMG data as a database for training. The results show a good agreement between RBF network and BSIM-CMG. The maximum error between BSIM-CMG and RBF is only 1%. The RBF is used for simulating or predicting I-V curve for different inputs without solving the complicated equations.
{"title":"Modeling double gate FinFETs by using artificial neural network","authors":"Milad Abtin, P. Keshavarzi, K. Jaferzadeh, A. Naderi","doi":"10.1109/SMELEC.2010.5549475","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549475","url":null,"abstract":"The minimum feature size of the transistors will be decreases in the future years as predicted by the international technology roadmap for semiconductors. Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime when considering the low scale effects is important for decreasing the scale. Solving and simulating the equations of these devices are so complicated and time consuming. In this paper we use RBF network for simulating the I-V characteristics of common symmetric multi gate FinFETs by using some BSIM-CMG data as a database for training. The results show a good agreement between RBF network and BSIM-CMG. The maximum error between BSIM-CMG and RBF is only 1%. The RBF is used for simulating or predicting I-V curve for different inputs without solving the complicated equations.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121590782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549365
A. A. Hamzah, K. Kharuddin, J. Yunas, C. Dee, B. Majlis
A hybrid solar - PZT microgenerator is designed using an n-doped single crystal p-type <100> silicon membrane as the solar cell and PZT layer deposited on the backside of the membrane as the mechanical energy harvester. The cell utilized a 40 µm thick membrane with an aluminum fin attached on its surface as the harvester for mechanical energies wind and raindrop. The solar cell has a dimension of 15 mm × 15 mm. Simulation was done using ATLAS software from SILVACO to obtain VOC, ISC, maximum power, and other characteristics for the solar cell. VOC and JSC of the cell are 0.41V and 1.363 µA/µm respectively. Under AM 1.5 condition, the maximum power density for the cell is 0.01913 W/cm2 and the efficiency is 19.13%. Simulation results suggest that the solar cell could be feasibly integrated into the hybrid microgenerator cell.
{"title":"Simulation study of solar energy conversion for hybrid microgenerator cell","authors":"A. A. Hamzah, K. Kharuddin, J. Yunas, C. Dee, B. Majlis","doi":"10.1109/SMELEC.2010.5549365","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549365","url":null,"abstract":"A hybrid solar - PZT microgenerator is designed using an n-doped single crystal p-type <100> silicon membrane as the solar cell and PZT layer deposited on the backside of the membrane as the mechanical energy harvester. The cell utilized a 40 µm thick membrane with an aluminum fin attached on its surface as the harvester for mechanical energies wind and raindrop. The solar cell has a dimension of 15 mm × 15 mm. Simulation was done using ATLAS software from SILVACO to obtain VOC, ISC, maximum power, and other characteristics for the solar cell. VOC and JSC of the cell are 0.41V and 1.363 µA/µm respectively. Under AM 1.5 condition, the maximum power density for the cell is 0.01913 W/cm2 and the efficiency is 19.13%. Simulation results suggest that the solar cell could be feasibly integrated into the hybrid microgenerator cell.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549492
P. Malik, R. Chaujar, Mridula Gupta, R. Gupta
In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.
{"title":"Evaluation of multi-layered gate design on GME-TRC MOSFET for wireless applications","authors":"P. Malik, R. Chaujar, Mridula Gupta, R. Gupta","doi":"10.1109/SMELEC.2010.5549492","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549492","url":null,"abstract":"In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549520
A. Hanim, H. Hazura, B. Mardiana, P. Menon
The paper reports on the free carrier absorption loss associated with silicon phase modulator. Two structures are compared: p-i-n and n-p-n structure. The simulations are realized utilizing the 2-D semiconductor simulation package SILVACO. Simulations predict that both structures operate more efficiently at 1.3 µm in terms of free carrier absorption loss. At 1.3 µm, the calculated free carrier absorption loss for p-i-n structure is 0.1149 dB, while n-p-n structure suffers 0.3956 dB of loss. Structure-wise, n-p-n silicon phase modulator experience more free carrier absorption loss compared to p-i-n structure due to extra doping contact.
{"title":"Free carrier absorption loss on p-i-n and n-p-n silicon phase modulator at λ=1.3µm and λ=1.55µm","authors":"A. Hanim, H. Hazura, B. Mardiana, P. Menon","doi":"10.1109/SMELEC.2010.5549520","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549520","url":null,"abstract":"The paper reports on the free carrier absorption loss associated with silicon phase modulator. Two structures are compared: p-i-n and n-p-n structure. The simulations are realized utilizing the 2-D semiconductor simulation package SILVACO. Simulations predict that both structures operate more efficiently at 1.3 µm in terms of free carrier absorption loss. At 1.3 µm, the calculated free carrier absorption loss for p-i-n structure is 0.1149 dB, while n-p-n structure suffers 0.3956 dB of loss. Structure-wise, n-p-n silicon phase modulator experience more free carrier absorption loss compared to p-i-n structure due to extra doping contact.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116363693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549542
B. K. Yap, S. Koh, S. Tiong, C. N. Ong
It is not an easy task to probe the mobility of nanoscale thin layers without using expensive and sophisticated equipments such as Time-of-flight photocurrent charge carrier mobility measurement. We present here a powerful yet cost-effective technique, namely the Space-Charge-Limited Dark Injection (SCL DI) Transient Measurement that allows us to confirm an ohmic injecting interface, to determine the mobility values of the bulk materials and to study the injection efficiency of the interfaces of the semiconductor materials.
{"title":"Space-Charge-Limited Dark Injection (SCL DI) transient measurements","authors":"B. K. Yap, S. Koh, S. Tiong, C. N. Ong","doi":"10.1109/SMELEC.2010.5549542","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549542","url":null,"abstract":"It is not an easy task to probe the mobility of nanoscale thin layers without using expensive and sophisticated equipments such as Time-of-flight photocurrent charge carrier mobility measurement. We present here a powerful yet cost-effective technique, namely the Space-Charge-Limited Dark Injection (SCL DI) Transient Measurement that allows us to confirm an ohmic injecting interface, to determine the mobility values of the bulk materials and to study the injection efficiency of the interfaces of the semiconductor materials.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125231987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549356
M. A. Chik, Ve Chun Yung, P. Balakrishna, U. Hashim, I. Ahmad, Bashir Mohamad
This research is to study the opportunity to achieve optimum productivity yield in 0.16µm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.
{"title":"A study for optimum productivity yield in 0.16µm mixed of wafer fabrication facility","authors":"M. A. Chik, Ve Chun Yung, P. Balakrishna, U. Hashim, I. Ahmad, Bashir Mohamad","doi":"10.1109/SMELEC.2010.5549356","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549356","url":null,"abstract":"This research is to study the opportunity to achieve optimum productivity yield in 0.16µm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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