Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549479
M. Riyadi, J. E. Suseno, Z. Napiah, A. Hamid, I. Saad, R. Ismail
The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.
{"title":"Investigation of short channel immunity of fully depleted double gate MOS with vertical structure","authors":"M. Riyadi, J. E. Suseno, Z. Napiah, A. Hamid, I. Saad, R. Ismail","doi":"10.1109/SMELEC.2010.5549479","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549479","url":null,"abstract":"The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128639129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549519
H. Hazura, A. Hanim, B. Mardiana, P. Menon
This paper highlights the study of carrier depletion effect on silicon waveguide with p-i-n diode and NPN structure. The device performance is predicted by using 2D Silvaco CAD software under different applied voltages. Device performances in terms of modulation efficiency will be discussed.
{"title":"An analysis of silicon waveguide phase modulation efficiency based on carrier depletion effect","authors":"H. Hazura, A. Hanim, B. Mardiana, P. Menon","doi":"10.1109/SMELEC.2010.5549519","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549519","url":null,"abstract":"This paper highlights the study of carrier depletion effect on silicon waveguide with p-i-n diode and NPN structure. The device performance is predicted by using 2D Silvaco CAD software under different applied voltages. Device performances in terms of modulation efficiency will be discussed.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129018983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549572
M. Sarah, M. Musa, A. Suriani, N. Jumali, Z. Shaameri, A. S. Hamzah, M. Rusop
Spin coating method is used to deposit nanocomposite CNT/MEH-PPV thin film on a glass substrate. The MEH-PPV which is in powder form was weighted and then dissolved into THF. Then, a certain amount of CNTs were added to the MEH-PPV solution. It is then stirred for 3 hours and sonicated for 1 hour to ensure that CNTs is well dispersed in the MEH-PPV solution. The addition of CNTs in the MEH-PPV solution yields a nanocomposite CNT/MEH-PPV solution. The characterization done was to evaluate the conductance as well as the absorption. The conductance and absorption of the nanocomposite showed an increment in value due to the existence of the CNTs.
{"title":"Study on existence of CNT in nanocomposite CNT/MEH-PPV thin film","authors":"M. Sarah, M. Musa, A. Suriani, N. Jumali, Z. Shaameri, A. S. Hamzah, M. Rusop","doi":"10.1109/SMELEC.2010.5549572","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549572","url":null,"abstract":"Spin coating method is used to deposit nanocomposite CNT/MEH-PPV thin film on a glass substrate. The MEH-PPV which is in powder form was weighted and then dissolved into THF. Then, a certain amount of CNTs were added to the MEH-PPV solution. It is then stirred for 3 hours and sonicated for 1 hour to ensure that CNTs is well dispersed in the MEH-PPV solution. The addition of CNTs in the MEH-PPV solution yields a nanocomposite CNT/MEH-PPV solution. The characterization done was to evaluate the conductance as well as the absorption. The conductance and absorption of the nanocomposite showed an increment in value due to the existence of the CNTs.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"61 34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134024653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549565
Sri Nengsih, A. Umar, M. Salleh, M. Yahaya
This paper reports the study of the localized surface plasmon resonance (LSPR) characteristic of the gold nanoparticle-cytochrome c hybrid thin film to detect the presence of nitric oxide (NO) gas. For the fabrications of gold nanoparticles ensemble on the surface, the seed mediated growth method was used. The cytochrome C (cyt c) thin film on gold nanoparticles was prepared using the spin coating technique. Detection of gas was based on the change in the LSPR of gold nanoparticle modified cytocrome C film upon exposure to the gas sample. It was found that the SPR peak of absorbance spectrum of gold nanoparticle-cyt c film was decreased when the NO gas flowed into the sensor chamber. The mechanism for detection of NO's gas will be discussed in this paper.
{"title":"Localized surface plasmon resonance of gold nanoparticle-cytocrome C to detect the presence of nitric oxide gas","authors":"Sri Nengsih, A. Umar, M. Salleh, M. Yahaya","doi":"10.1109/SMELEC.2010.5549565","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549565","url":null,"abstract":"This paper reports the study of the localized surface plasmon resonance (LSPR) characteristic of the gold nanoparticle-cytochrome c hybrid thin film to detect the presence of nitric oxide (NO) gas. For the fabrications of gold nanoparticles ensemble on the surface, the seed mediated growth method was used. The cytochrome C (cyt c) thin film on gold nanoparticles was prepared using the spin coating technique. Detection of gas was based on the change in the LSPR of gold nanoparticle modified cytocrome C film upon exposure to the gas sample. It was found that the SPR peak of absorbance spectrum of gold nanoparticle-cyt c film was decreased when the NO gas flowed into the sensor chamber. The mechanism for detection of NO's gas will be discussed in this paper.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129696850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549367
K. Hasikin, N. Soin, F. Ibrahim
This paper presents a micro-diaphragm performance analysis for optical sensor for human pulse pressure detection. The effect of diaphragm radius and diaphragm thickness on the static and frequency responses were investigated. It can be concluded that the polyimide micro-diaphragm with a radius of 90µm and thickness of 4µm has achieved the optimum performance in term of the sensitivity, flexural rigidity and resonance frequency.
{"title":"Micro-diaphragm performance analysis for polyimide diaphragm","authors":"K. Hasikin, N. Soin, F. Ibrahim","doi":"10.1109/SMELEC.2010.5549367","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549367","url":null,"abstract":"This paper presents a micro-diaphragm performance analysis for optical sensor for human pulse pressure detection. The effect of diaphragm radius and diaphragm thickness on the static and frequency responses were investigated. It can be concluded that the polyimide micro-diaphragm with a radius of 90µm and thickness of 4µm has achieved the optimum performance in term of the sensitivity, flexural rigidity and resonance frequency.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549462
Wan Zurina Samad, M. Salleh, A. Shafiee, M. Yarmo
FTO thin films were successfully prepared by inkjet printing technique. FTO precursor was prepared by reacting SnCl4.5H2O and NH4F at 60°C in a sealed container. The number of layers was set up from two to five layers on the glass substrate and was deposited at room temperature around 25 to 27° C, 40° C and 60° C to determine the optimum properties for thin films performance. Morphology analysis study using VP-SEM shows the existence of fine grains with the size ranging 20 to 30 nm and the existence of crystal shape with the increases of deposition temperature. Fluorine concentration in the thin films determined from XPS analysis shows the ratio of[F]/[Sn] at 0.02 with the Sn d5/2 Sn 4+, O1s as O2-, and F1s as Sn-F bond peaks at binding energy 486.6 eV, 530.5 eV and 684.4 eV. The optical transmittance analysis showed the deposition temperature improved the optical transmittance; 60% T at ambient to 80% T at 60° C. The optimum optical transmittance was 91% T for the thin film deposited at 40° C. The sheet resistances were 16 Ω/□, 21 Ω/□ 23 Ω/□ for the thin film deposited at 40° C, ambient temperature and 60° C.
采用喷墨打印技术成功制备了FTO薄膜。采用SnCl4.5H2O和NH4F在60℃密闭容器中反应制备FTO前驱体。在玻璃基板上设置两层至五层的层数，并在室温下分别在25至27°C, 40°C和60°C沉积，以确定薄膜的最佳性能。利用VP-SEM进行形貌分析研究表明，随着沉积温度的升高，合金中存在20 ~ 30 nm大小的细小晶粒，并存在晶体形状。薄膜中氟浓度的XPS分析表明[F]/[Sn]比值为0.02,Sn d /2 Sn 4+， O1s为O2-， F1s为Sn-F键，结合能分别为486.6 eV, 530.5 eV和684.4 eV。光透过率分析表明，沉积温度提高了光透过率;60℃环境温度下60% T ~ 80% T, 40℃沉积薄膜的最佳透过率为91% T, 40℃、环境温度和60℃沉积薄膜的片电阻分别为16 Ω/□，21 Ω/□23 Ω/□。
{"title":"Transparent conducting thin films of fluoro doped tin oxide (FTO) deposited using inkjet printing technique","authors":"Wan Zurina Samad, M. Salleh, A. Shafiee, M. Yarmo","doi":"10.1109/SMELEC.2010.5549462","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549462","url":null,"abstract":"FTO thin films were successfully prepared by inkjet printing technique. FTO precursor was prepared by reacting SnCl<inf>4</inf>.5H<inf>2</inf>O and NH<inf>4</inf>F at 60°C in a sealed container. The number of layers was set up from two to five layers on the glass substrate and was deposited at room temperature around 25 to 27° C, 40° C and 60° C to determine the optimum properties for thin films performance. Morphology analysis study using VP-SEM shows the existence of fine grains with the size ranging 20 to 30 nm and the existence of crystal shape with the increases of deposition temperature. Fluorine concentration in the thin films determined from XPS analysis shows the ratio of[F]/[Sn] at 0.02 with the Sn d<inf>5/2</inf> Sn 4+, O<inf>1s</inf> as O<sup>2-</sup>, and F1s as Sn-F bond peaks at binding energy 486.6 eV, 530.5 eV and 684.4 eV. The optical transmittance analysis showed the deposition temperature improved the optical transmittance; 60% T at ambient to 80% T at 60° C. The optimum optical transmittance was 91% T for the thin film deposited at 40° C. The sheet resistances were 16 Ω/□, 21 Ω/□ 23 Ω/□ for the thin film deposited at 40° C, ambient temperature and 60° C.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122554991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549382
C. Senthilpari, S. Kavitha, Jude Joseph
This paper is mainly focused on designs of full-adder using by Shannon theorem based on pass transistor approach. The proposed Shannon theorem adder, SERF, CMOS 10T and mirror adder circuits are implemented in non-restoring array divider circuit. The divider circuits is schematized by using DSCH2 CAD tools and their layouts are simulated by using Microwind 3 VLSI layout CAD tool. The parameter analyses are analyzed by using BSIM 4 analyzer. The analysis includes power dissipation, propagation delay, chip area, power delay product (PDP), Energy Per Instruction (EPI), latency and throughput. These analyses are compared with reported author results, which shows better improvement in terms of low power, lower area, lower propagation delay and high throughput.
{"title":"Lower delay and area efficient non-restoring array divider by using Shannon based adder technique","authors":"C. Senthilpari, S. Kavitha, Jude Joseph","doi":"10.1109/SMELEC.2010.5549382","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549382","url":null,"abstract":"This paper is mainly focused on designs of full-adder using by Shannon theorem based on pass transistor approach. The proposed Shannon theorem adder, SERF, CMOS 10T and mirror adder circuits are implemented in non-restoring array divider circuit. The divider circuits is schematized by using DSCH2 CAD tools and their layouts are simulated by using Microwind 3 VLSI layout CAD tool. The parameter analyses are analyzed by using BSIM 4 analyzer. The analysis includes power dissipation, propagation delay, chip area, power delay product (PDP), Energy Per Instruction (EPI), latency and throughput. These analyses are compared with reported author results, which shows better improvement in terms of low power, lower area, lower propagation delay and high throughput.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124264843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549350
K. Omar, N. Soin, W. Mahadi, Hassan Malik
This paper presents a lithium-ion battery recharging circuit with an improved charger system topology for portable devices and handheld gadgets. The proposed charger topology uses an operational amplifier with NMOS input for a smooth transition between current control loop and voltage control loop and to control a power pass element device. Using the above-mentioned abilities, a complete charging process, consisting of three sub-processes; automatically trickle charge, constant current and constant voltage mode are implemented. In the proposed new charger system topology, the charging behaviors of the Li-ion battery can achieve a better charging performance and terminated automatically when fully charged. Simulation results show that the power pass element channel width is 40,000 µm which is less 60% from others design, is able to carry out the output voltage of 4.2 V, the maximum charging current reaches 1 A and the trickle charge is 10% of constant current. The new charger topology has been implemented using 0.18µm CMOS process. Experimental result shows that the new charger design topology agrees with the charging behaviors from simulation results.
{"title":"A new charger system approach: The current and voltage control loops","authors":"K. Omar, N. Soin, W. Mahadi, Hassan Malik","doi":"10.1109/SMELEC.2010.5549350","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549350","url":null,"abstract":"This paper presents a lithium-ion battery recharging circuit with an improved charger system topology for portable devices and handheld gadgets. The proposed charger topology uses an operational amplifier with NMOS input for a smooth transition between current control loop and voltage control loop and to control a power pass element device. Using the above-mentioned abilities, a complete charging process, consisting of three sub-processes; automatically trickle charge, constant current and constant voltage mode are implemented. In the proposed new charger system topology, the charging behaviors of the Li-ion battery can achieve a better charging performance and terminated automatically when fully charged. Simulation results show that the power pass element channel width is 40,000 µm which is less 60% from others design, is able to carry out the output voltage of 4.2 V, the maximum charging current reaches 1 A and the trickle charge is 10% of constant current. The new charger topology has been implemented using 0.18µm CMOS process. Experimental result shows that the new charger design topology agrees with the charging behaviors from simulation results.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549504
K. Zain
The electronic industry is the leading sector in Malaysia's manufacturing sector, contributing significantly to the country's manufacturing output 29.3%, export 55.9% and employment of 28.8%. In 70's Malaysia is well known for the backend manufacturing. In 2000 Malaysia established it's semiconductor fabrication facilities to fill in one of the major gaps in supply chain that generates RM0.5Billion/year from a single facility. This significant source of revenue gives major impact to the overall semiconductor eco-system and local economy. Semiconductor fabrication requires huge equipment investment using various types of chemicals, gasses, materials, software systems, automation, jigs and fixtures, consumables and parts in clean room environment. The process to fabricate a chip on wafer will take thirty to one hundred days depending on the complexity of the design. This demands a very highly skilled workforce to operate the processes, equipments, manufacturing and facilities. Semiconductor fabrication facility has a very deep anchor to the value chain surrounding economy and will be discussed in detail the presentation.
{"title":"Semiconductor fabrication eco-systems and supply chain in Malaysia","authors":"K. Zain","doi":"10.1109/SMELEC.2010.5549504","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549504","url":null,"abstract":"The electronic industry is the leading sector in Malaysia's manufacturing sector, contributing significantly to the country's manufacturing output 29.3%, export 55.9% and employment of 28.8%. In 70's Malaysia is well known for the backend manufacturing. In 2000 Malaysia established it's semiconductor fabrication facilities to fill in one of the major gaps in supply chain that generates RM0.5Billion/year from a single facility. This significant source of revenue gives major impact to the overall semiconductor eco-system and local economy. Semiconductor fabrication requires huge equipment investment using various types of chemicals, gasses, materials, software systems, automation, jigs and fixtures, consumables and parts in clean room environment. The process to fabricate a chip on wafer will take thirty to one hundred days depending on the complexity of the design. This demands a very highly skilled workforce to operate the processes, equipments, manufacturing and facilities. Semiconductor fabrication facility has a very deep anchor to the value chain surrounding economy and will be discussed in detail the presentation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121665048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549510
B. Mardiana, H. Hazura, A. Hanim, P. Menon, H. Abdullah
This paper highlights the study of the carrier injection mode and the carrier depletion mode of the phase modulator. The phase modulator device has been integrated in the silicon rib waveguide by using the p-i-n diode structure. The electrical device performance is predicted by using the 2-D semiconductor package SILVACO (CAD) software under DC operation. Summarily, the phase modulator device has less sensitivity to the effective refractive index changes when operating in reverse biased or depletion mode compared to the forward biased or injection mode.
{"title":"Operation mode of phase modulation based on carrier dispersion effect in p-i-n diode of silicon rib waveguide","authors":"B. Mardiana, H. Hazura, A. Hanim, P. Menon, H. Abdullah","doi":"10.1109/SMELEC.2010.5549510","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549510","url":null,"abstract":"This paper highlights the study of the carrier injection mode and the carrier depletion mode of the phase modulator. The phase modulator device has been integrated in the silicon rib waveguide by using the p-i-n diode structure. The electrical device performance is predicted by using the 2-D semiconductor package SILVACO (CAD) software under DC operation. Summarily, the phase modulator device has less sensitivity to the effective refractive index changes when operating in reverse biased or depletion mode compared to the forward biased or injection mode.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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