Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549383
P. Fahsyar, N. Soin
This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.
{"title":"CMOS implementation of envelope detector circuit in 0.18µm Process","authors":"P. Fahsyar, N. Soin","doi":"10.1109/SMELEC.2010.5549383","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549383","url":null,"abstract":"This paper presents an envelope detector circuit design for RFID applications implemented in 0.18µm CMOS technology. Towards the design compatibility with standard digital CMOS process, the doubler cell, diode connected PMOS and low transconductance transistor are chosen to place in the rectifier section and to replace the conventional diode as well as the resistor. The proposed envelope detector circuit was simulated with a 150mV – 250mV input signal. With 0.2 modulation index at 900MHz carrier frequency, the power dissipation is found to be 18.8µW at 27°C.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124772580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549373
J. Alvankarian, B. Majlis
An elastomeric microfluidic structure was developed by polymerization of a liquid photopolymer using UV lithography process. Integration of different components of a microfluidic device including microchannel, micromixer, and microchamber, on one layer and by using one photomask is practiced. More complicated geometries and 2-layer chip was examined in this research and gives promising results. This process enables well control over the thicknesses of the layers, and dimensions of the components considering. The proposed simple process benefits from low cost in development time and expenses of the materials.
{"title":"Low cost prototyping of microfluidic structure","authors":"J. Alvankarian, B. Majlis","doi":"10.1109/SMELEC.2010.5549373","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549373","url":null,"abstract":"An elastomeric microfluidic structure was developed by polymerization of a liquid photopolymer using UV lithography process. Integration of different components of a microfluidic device including microchannel, micromixer, and microchamber, on one layer and by using one photomask is practiced. More complicated geometries and 2-layer chip was examined in this research and gives promising results. This process enables well control over the thicknesses of the layers, and dimensions of the components considering. The proposed simple process benefits from low cost in development time and expenses of the materials.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125306815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549354
B. K. Yap, S. Koh, S. Tiong, C. N. Ong
This work presents thermal stability studies of PLEDs involving the comparison of electrical performance before and after thermal treatment. Two cycles of continuous thermal stress test from room temperature to 100 deg Celsius did not significantly affect the total photoluminescence intensity from the light-emitting polymer in the PLED suggesting that the layer of light-emitting polymer is intact. However, the rapid degradation of the electrical performance of the PLED right after the first cycle of thermal stress test suggests that the electrodes have degraded hence hindering charge injection into the polymeric layer.
{"title":"Thermal stress test for PLED","authors":"B. K. Yap, S. Koh, S. Tiong, C. N. Ong","doi":"10.1109/SMELEC.2010.5549354","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549354","url":null,"abstract":"This work presents thermal stability studies of PLEDs involving the comparison of electrical performance before and after thermal treatment. Two cycles of continuous thermal stress test from room temperature to 100 deg Celsius did not significantly affect the total photoluminescence intensity from the light-emitting polymer in the PLED suggesting that the layer of light-emitting polymer is intact. However, the rapid degradation of the electrical performance of the PLED right after the first cycle of thermal stress test suggests that the electrodes have degraded hence hindering charge injection into the polymeric layer.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549499
I. Voiculescu
This presentation is an overview of standard Integrated Circuits technology that enables the integration of the chemical sensors with the necessary driving and signal conditioning circuitry on the same chip. A variety of Complementary Metal Oxide Semiconductor (CMOS)-based chemical sensors found in the literature and the microprocessing technologic steps necessary for the integration of microelectromechanical systems (MEMS) sensors in CMOS technology are explained in this presentation. CMOS technology has become the mainstream semiconductor technology over the last decade due to its high volume production capability and its circuit advantages. Silicon is a readily available material that is relatively inexpensive. In addition, circuits fabricated in CMOS are low cost. An important advantage of CMOS technology is the possibility of integrating electronic circuitry with the MEMS sensor. Although CMOS processes were originally not intended for MEMS devices, the CMOS technology in combination with additional pre or post fabrication micromachining steps allows for integration of MEMS sensors and CMOS circuitry on the same chip. The monolithic integration of CMOS MEMS chemical sensors is a promising approach that has been motivated by the rapid development in integrated-circuit and MEMS technology. The aim in utilizing CMOS technology for realizing chemical sensors is to create more intelligent, more autonomous, more integrated and more reliable chemical sensor systems at low costs in a generic approach. The integration of electronics with chemical sensors in one single chip improves the sensor signals in terms of robustness and signal-to-noise ratio. On-chip integration also improves the microsystem functionality, interconnection and facilitates a more efficient packaging. At high volumes of production, the monolithic solution presents economical advantages, and it is especially attractive for portable and high sensitivity systems. The main disadvantages of the monolithic CMOS–MEMS integration include the restriction to CMOS-compatible materials and the limited choice of micromachining processes. However, the use of CMOS–MEMS offers, on the other hand, unprecedented advantages over hybrid designs, especially with regard to signal quality, device performance, increased functionality and available standard packaging solutions. These advantages clearly outweigh the drawbacks and limitations. A large number of MEMS gas sensors fabricated in CMOS technology were recently researched and developed. Several important CMOS-MEMS gas sensors will be presented.
{"title":"Chemical sensors fabricated in CMOS-MEMS technology","authors":"I. Voiculescu","doi":"10.1109/SMELEC.2010.5549499","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549499","url":null,"abstract":"This presentation is an overview of standard Integrated Circuits technology that enables the integration of the chemical sensors with the necessary driving and signal conditioning circuitry on the same chip. A variety of Complementary Metal Oxide Semiconductor (CMOS)-based chemical sensors found in the literature and the microprocessing technologic steps necessary for the integration of microelectromechanical systems (MEMS) sensors in CMOS technology are explained in this presentation. CMOS technology has become the mainstream semiconductor technology over the last decade due to its high volume production capability and its circuit advantages. Silicon is a readily available material that is relatively inexpensive. In addition, circuits fabricated in CMOS are low cost. An important advantage of CMOS technology is the possibility of integrating electronic circuitry with the MEMS sensor. Although CMOS processes were originally not intended for MEMS devices, the CMOS technology in combination with additional pre or post fabrication micromachining steps allows for integration of MEMS sensors and CMOS circuitry on the same chip. The monolithic integration of CMOS MEMS chemical sensors is a promising approach that has been motivated by the rapid development in integrated-circuit and MEMS technology. The aim in utilizing CMOS technology for realizing chemical sensors is to create more intelligent, more autonomous, more integrated and more reliable chemical sensor systems at low costs in a generic approach. The integration of electronics with chemical sensors in one single chip improves the sensor signals in terms of robustness and signal-to-noise ratio. On-chip integration also improves the microsystem functionality, interconnection and facilitates a more efficient packaging. At high volumes of production, the monolithic solution presents economical advantages, and it is especially attractive for portable and high sensitivity systems. The main disadvantages of the monolithic CMOS–MEMS integration include the restriction to CMOS-compatible materials and the limited choice of micromachining processes. However, the use of CMOS–MEMS offers, on the other hand, unprecedented advantages over hybrid designs, especially with regard to signal quality, device performance, increased functionality and available standard packaging solutions. These advantages clearly outweigh the drawbacks and limitations. A large number of MEMS gas sensors fabricated in CMOS technology were recently researched and developed. Several important CMOS-MEMS gas sensors will be presented.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121220124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549488
F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim
Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to −0.1501V and +0.150047V respectively.
{"title":"Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method","authors":"F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim","doi":"10.1109/SMELEC.2010.5549488","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549488","url":null,"abstract":"Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to −0.1501V and +0.150047V respectively.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121357465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549526
A. Ismardi, T. Y. Tiong, C. Dee, A. A. Hamzah, B. Majlis
This paper reports on synthesis and characterizations of Sn doped ZnO nanowires. Sn doped ZnO nanowires was successfully been grown using carbothermal reduction method. Morphological and structures were characterized using FESEM, revealed that nanowires grown on random direction with diameter around 30 – 60 nm. EDX analysis was used to confirm composition element, Sn element was found in the nanowires in less than 1% of total composition. XRD was applied to examine structure quality of Sn doped ZnO nanowires, XRD spectra shown the structure have high crystallinity and it is wurtzite structure. No contrast different were found between pure and Sn doped ZnO nanowires. I-V measurement shown that using Sn as dopant may decrease the resistance of ZnO nanowires.
{"title":"Synthesis and characterization of sn doped ZnO nanowires","authors":"A. Ismardi, T. Y. Tiong, C. Dee, A. A. Hamzah, B. Majlis","doi":"10.1109/SMELEC.2010.5549526","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549526","url":null,"abstract":"This paper reports on synthesis and characterizations of Sn doped ZnO nanowires. Sn doped ZnO nanowires was successfully been grown using carbothermal reduction method. Morphological and structures were characterized using FESEM, revealed that nanowires grown on random direction with diameter around 30 – 60 nm. EDX analysis was used to confirm composition element, Sn element was found in the nanowires in less than 1% of total composition. XRD was applied to examine structure quality of Sn doped ZnO nanowires, XRD spectra shown the structure have high crystallinity and it is wurtzite structure. No contrast different were found between pure and Sn doped ZnO nanowires. I-V measurement shown that using Sn as dopant may decrease the resistance of ZnO nanowires.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133741698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549582
M. Ahmadi, Z. Johari, N. A. Amin, S. Mousavi, R. Ismail
Fermi dirac integral is applied to study the parabolic band structure of Carbon Nanotube (CNT) which is in the range of minimum band energy. In this letter electronic transport property of one dimensional carbon nanotube with parabolic band structures near the charge neutrality point is investigated. The temperature dependent conductance model which shows minimum conductance near the charge neutrality point and decreases by decreasing the temperature is presented. CNTs with micrometer length exhibit nondegenerate behavior on fundamental band structure similar to the conventional long channel devices.
{"title":"Carbon nanotube conductance model in parabolic band structure","authors":"M. Ahmadi, Z. Johari, N. A. Amin, S. Mousavi, R. Ismail","doi":"10.1109/SMELEC.2010.5549582","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549582","url":null,"abstract":"Fermi dirac integral is applied to study the parabolic band structure of Carbon Nanotube (CNT) which is in the range of minimum band energy. In this letter electronic transport property of one dimensional carbon nanotube with parabolic band structures near the charge neutrality point is investigated. The temperature dependent conductance model which shows minimum conductance near the charge neutrality point and decreases by decreasing the temperature is presented. CNTs with micrometer length exhibit nondegenerate behavior on fundamental band structure similar to the conventional long channel devices.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"19 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131082657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549417
Ma Lei, Ding Ying-tao, Wang Xing-hua
In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with current-mode single-ended amplifier, this OTA reduce parasitic taking by gain-boost amplifier to achieve high-gain and high-speed. Besides, a dual phase SC-CMFB circuit is introduced, and some methods are concerned to improve the performance. Then, by optimization the layout design, OTA's mismatch was reduced. This design was using SMIC 0.35um CMOS process and simulation both schematic and layout in Cadence. The result of the simulation shows that the OTA has a gain up to 105dB, a unity gain bandwidth of about 937MHz for a 2pF load, a settling time of about 4.4ns, a Common-Mode Range is 0.6V∼3.3V, a output swing is 0.6V∼3.1V, with the power supply of 3.3V, the dissipation is 39mW. This amplifier was used in a 10bit 100MHz pipelined ADC.
{"title":"A folded cascode OTA using current-mode gain-boost amplifier","authors":"Ma Lei, Ding Ying-tao, Wang Xing-hua","doi":"10.1109/SMELEC.2010.5549417","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549417","url":null,"abstract":"In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with current-mode single-ended amplifier, this OTA reduce parasitic taking by gain-boost amplifier to achieve high-gain and high-speed. Besides, a dual phase SC-CMFB circuit is introduced, and some methods are concerned to improve the performance. Then, by optimization the layout design, OTA's mismatch was reduced. This design was using SMIC 0.35um CMOS process and simulation both schematic and layout in Cadence. The result of the simulation shows that the OTA has a gain up to 105dB, a unity gain bandwidth of about 937MHz for a 2pF load, a settling time of about 4.4ns, a Common-Mode Range is 0.6V∼3.3V, a output swing is 0.6V∼3.1V, with the power supply of 3.3V, the dissipation is 39mW. This amplifier was used in a 10bit 100MHz pipelined ADC.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123188338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549479
M. Riyadi, J. E. Suseno, Z. Napiah, A. Hamid, I. Saad, R. Ismail
The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.
{"title":"Investigation of short channel immunity of fully depleted double gate MOS with vertical structure","authors":"M. Riyadi, J. E. Suseno, Z. Napiah, A. Hamid, I. Saad, R. Ismail","doi":"10.1109/SMELEC.2010.5549479","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549479","url":null,"abstract":"The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128639129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-28DOI: 10.1109/SMELEC.2010.5549491
N. I. Shuhaimi, M. Mohamad, W. M. Jubadi, Ruzaini Tugiman, N. Zinal, Rosnah Mohd Zin
The performance of the PIN diode is very much depends on the chip geometry and the semiconductor material used, especially in the intrinsic region. The biasing voltage applied to the PIN diode determines the amount of holes and electrons injected into the intrinsic region and the values of its resistivity. This will give effect to the I-V performance of the PIN diode. This research studied the effects of width (and subsequently area) variations of intrinsic region of Silicon PIN diode on its I-V performance. The two dimensional structures and recipes of PIN diode are designed and simulated using Sentaurus TCAD tools. The thickness of PIN diode is kept at 40 µm while only the width is varied accordingly. Three variations of width have been chosen which are 90 µm, 80 µm, and 70 µm in order to study the impacts of width variation has on the I-V performance. Based on the simulation results, it is found that the current level is proportional to the PIN structure width.
{"title":"Comparison on I-V performances of Silicon PIN diode towards width variations","authors":"N. I. Shuhaimi, M. Mohamad, W. M. Jubadi, Ruzaini Tugiman, N. Zinal, Rosnah Mohd Zin","doi":"10.1109/SMELEC.2010.5549491","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549491","url":null,"abstract":"The performance of the PIN diode is very much depends on the chip geometry and the semiconductor material used, especially in the intrinsic region. The biasing voltage applied to the PIN diode determines the amount of holes and electrons injected into the intrinsic region and the values of its resistivity. This will give effect to the I-V performance of the PIN diode. This research studied the effects of width (and subsequently area) variations of intrinsic region of Silicon PIN diode on its I-V performance. The two dimensional structures and recipes of PIN diode are designed and simulated using Sentaurus TCAD tools. The thickness of PIN diode is kept at 40 µm while only the width is varied accordingly. Three variations of width have been chosen which are 90 µm, 80 µm, and 70 µm in order to study the impacts of width variation has on the I-V performance. Based on the simulation results, it is found that the current level is proportional to the PIN structure width.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125198345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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