Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047163
Min-Cheng Chen, Chia-Yi Lin, K.-H. Li, Lain‐Jong Li, Chang-Hsiao Chen, C. Chuang, Ming-Dao Lee, Yi-Ju Chen, Y. Hou, Chang-Hsien Lin, Chun-Chi Chen, Bo-Wei Wu, Cheng-San Wu, I. Yang, Yao-Jen Lee, W. Yeh, Tahui Wang, Fu-Liang Yang, C. Hu
Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
{"title":"Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs","authors":"Min-Cheng Chen, Chia-Yi Lin, K.-H. Li, Lain‐Jong Li, Chang-Hsiao Chen, C. Chuang, Ming-Dao Lee, Yi-Ju Chen, Y. Hou, Chang-Hsien Lin, Chun-Chi Chen, Bo-Wei Wu, Cheng-San Wu, I. Yang, Yao-Jen Lee, W. Yeh, Tahui Wang, Fu-Liang Yang, C. Hu","doi":"10.1109/IEDM.2014.7047163","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047163","url":null,"abstract":"Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134432674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047021
Jiaju Ma, Donald B. Hondongwa, E. Fossum
The Quanta Image Sensor (QIS) concept and recent work on its associated jot device are discussed. A bipolar jot and a pump-gate jot are described. Both have been modelled in TCAD. As simulated, the pump-gate jot has a full well of 200e- and conversion gain of 480uV/e-.
{"title":"Jot devices and the Quanta Image Sensor","authors":"Jiaju Ma, Donald B. Hondongwa, E. Fossum","doi":"10.1109/IEDM.2014.7047021","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047021","url":null,"abstract":"The Quanta Image Sensor (QIS) concept and recent work on its associated jot device are discussed. A bipolar jot and a pump-gate jot are described. Both have been modelled in TCAD. As simulated, the pump-gate jot has a full well of 200e- and conversion gain of 480uV/e-.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133395177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047012
M. Haras, V. Lacatena, F. Morini, J. Robillard, S. Monfray, T. Skotnicki, E. Dubois
Good electrical performance of Silicon enables high harvested power density allowing Silicon to compete with conventional thermoelectric materials such as Bi2Te3 or Sb2Te3. High value of thermal conductivity eliminating the use of Silicon in thermoelectricity is no longer an unbeatable drawback since the possibility of reduction has been established and confirmed. Thermal conductivity reduction by a factor 3 over bulk value is reported in 70nm thick Silicon. The Silicon thermal conductivity can be reduced even 100× over bulk when using dedicated patterning which can block the propagation of phonons responsible for heat transport [3]. This reduction will have significant influence in launching industrialization of CMOS compatible thermogenerators.
{"title":"Fabrication of integrated micrometer platform for thermoelectric measurements","authors":"M. Haras, V. Lacatena, F. Morini, J. Robillard, S. Monfray, T. Skotnicki, E. Dubois","doi":"10.1109/IEDM.2014.7047012","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047012","url":null,"abstract":"Good electrical performance of Silicon enables high harvested power density allowing Silicon to compete with conventional thermoelectric materials such as Bi2Te3 or Sb2Te3. High value of thermal conductivity eliminating the use of Silicon in thermoelectricity is no longer an unbeatable drawback since the possibility of reduction has been established and confirmed. Thermal conductivity reduction by a factor 3 over bulk value is reported in 70nm thick Silicon. The Silicon thermal conductivity can be reduced even 100× over bulk when using dedicated patterning which can block the propagation of phonons responsible for heat transport [3]. This reduction will have significant influence in launching industrialization of CMOS compatible thermogenerators.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132890682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047063
Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang
3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) Vth adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for Vth adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high Ion/Ioff ratio (>105), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such Vth adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.
{"title":"Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit","authors":"Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang","doi":"10.1109/IEDM.2014.7047063","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047063","url":null,"abstract":"3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) V<sub>th</sub> adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for V<sub>th</sub> adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high I<sub>on</sub>/I<sub>off</sub> ratio (>10<sup>5</sup>), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such V<sub>th</sub> adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"3 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046989
Xiang Li, Jiahao Kang, Xuejun Xie, W. Liu, D. Sarkar, Junfa Mao, K. Banerjee
Graphene is very attractive for densely integrated and flexible high-frequency/RF IC applications due to its extraordinary electrical, thermal, and mechanical properties. This work presents the design, fabrication, and characterization of graphene on-chip inductors. The skin effect in graphene inductors is investigated experimentally for the first time based on a circuit model proposed and fitted from fabricated ¾-, 2-, and 3-turn spiral inductors. The operation frequencies are in 40-60 GHz range and Q-factors are around 3. Design and fabrication optimizations are performed to guide future studies.
{"title":"Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect","authors":"Xiang Li, Jiahao Kang, Xuejun Xie, W. Liu, D. Sarkar, Junfa Mao, K. Banerjee","doi":"10.1109/IEDM.2014.7046989","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046989","url":null,"abstract":"Graphene is very attractive for densely integrated and flexible high-frequency/RF IC applications due to its extraordinary electrical, thermal, and mechanical properties. This work presents the design, fabrication, and characterization of graphene on-chip inductors. The skin effect in graphene inductors is investigated experimentally for the first time based on a circuit model proposed and fitted from fabricated ¾-, 2-, and 3-turn spiral inductors. The operation frequencies are in 40-60 GHz range and Q-factors are around 3. Design and fabrication optimizations are performed to guide future studies.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047106
Y. Sun, A. Majumdar, C. Cheng, R. Martin, R. Bruce, J. Yau, D. Farmer, Y. Zhu, M. Hopstaken, M. Frank, T. Ando, K. Lee, J. Rozen, A. Basu, K. Shiu, P. Kerber, D. Park, V. Narayanan, R. Mo, D. Sadana, E. Leobandung
We demonstrate high-performance self-aligned In0.53Ga0.47As-channel MOSFETs with effective channel length LEFF down to 20 nm, peak transconductance GMSAT over 2200 μS/μm at LEFF = 30 nm and supply voltage VDD = 0.5 V, thin inversion oxide thickness TINV = 1.8 nm, and low series resistance REXT = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for LEFF ≤ 30 nm and are among the best In0.53Ga0.47As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm2/Vs has progressively smaller impact as LEFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.
{"title":"High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 µS/µm at VDD = 0.5 V","authors":"Y. Sun, A. Majumdar, C. Cheng, R. Martin, R. Bruce, J. Yau, D. Farmer, Y. Zhu, M. Hopstaken, M. Frank, T. Ando, K. Lee, J. Rozen, A. Basu, K. Shiu, P. Kerber, D. Park, V. Narayanan, R. Mo, D. Sadana, E. Leobandung","doi":"10.1109/IEDM.2014.7047106","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047106","url":null,"abstract":"We demonstrate high-performance self-aligned In<sub>0.53</sub>Ga<sub>0.47</sub>As-channel MOSFETs with effective channel length L<sub>EFF</sub> down to 20 nm, peak transconductance G<sub>MSAT</sub> over 2200 μS/μm at L<sub>EFF</sub> = 30 nm and supply voltage V<sub>DD</sub> = 0.5 V, thin inversion oxide thickness T<sub>INV</sub> = 1.8 nm, and low series resistance R<sub>EXT</sub> = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L<sub>EFF</sub> ≤ 30 nm and are among the best In<sub>0.53</sub>Ga<sub>0.47</sub>As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm<sup>2</sup>/Vs has progressively smaller impact as L<sub>EFF</sub> is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116727709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047058
T.-T Chen, C.-H Wen, J.C.-M. Huang, Y.-C Peng, S. Liu, S.-H Su, L.-H Cheng, H. Lai, Tingmao Liao, F. Lai, C.-W Cheng, C.K. Yang, J. Yang, Y. Hsieh, E. Salm, B. Reddy, F. Tsui, Y. Liu, R. Bashir, M. Chen
A 0.18μm SOI-CMOS bioelectrical sensing technology is introduced. An SOC chip integrates biosensor pixel arrays, controllers and amplifiers is used to demonstrate the performance of this technology. The pixel size in the pixel arrays is 10μm × 10μm, including biosensor, temperature sensor and heaters. The chip demonstrates detections of hydrogen ion concentration, enzymatic reactions and DNA hybridization with PCR. Experimental results show close to Nernst limit of 59mV/pH in ion concentration detection, sub-millimolar resolutions with 99.9% linearity in urea, and 400mV surface potential change in DNA hybridization. The SOC chip has an addressable temperature control for each pixel with embedded thermal sensors. A thermal time constant of 35msec/K and sub-degree localized temperature control are achieved. Order of magnitude improvements over previously reported are seen in both detectable minimum sample liquid volume and thermal time constant for PCR. This is a good demonstration of semiconductor technology for multi-biomarkers detection for medical applications.
{"title":"A semiconductor bio-electrical platform with addressable thermal control circuits for accelerated bioassay development","authors":"T.-T Chen, C.-H Wen, J.C.-M. Huang, Y.-C Peng, S. Liu, S.-H Su, L.-H Cheng, H. Lai, Tingmao Liao, F. Lai, C.-W Cheng, C.K. Yang, J. Yang, Y. Hsieh, E. Salm, B. Reddy, F. Tsui, Y. Liu, R. Bashir, M. Chen","doi":"10.1109/IEDM.2014.7047058","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047058","url":null,"abstract":"A 0.18μm SOI-CMOS bioelectrical sensing technology is introduced. An SOC chip integrates biosensor pixel arrays, controllers and amplifiers is used to demonstrate the performance of this technology. The pixel size in the pixel arrays is 10μm × 10μm, including biosensor, temperature sensor and heaters. The chip demonstrates detections of hydrogen ion concentration, enzymatic reactions and DNA hybridization with PCR. Experimental results show close to Nernst limit of 59mV/pH in ion concentration detection, sub-millimolar resolutions with 99.9% linearity in urea, and 400mV surface potential change in DNA hybridization. The SOC chip has an addressable temperature control for each pixel with embedded thermal sensors. A thermal time constant of 35msec/K and sub-degree localized temperature control are achieved. Order of magnitude improvements over previously reported are seen in both detectable minimum sample liquid volume and thermal time constant for PCR. This is a good demonstration of semiconductor technology for multi-biomarkers detection for medical applications.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130745682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047152
H. Tsai, H. Miyazoe, Josephine B. Chang, J. Pitera, Chi-Chun Liu, M. Brink, I. Lauer, Joy Y. Cheng, S. Engelmann, J. Rozen, J. Bucchignano, D. Klaus, S. Dawes, L. Gignac, C. Breslin, E. Joseph, D. Sanders, M. Colburn, M. Guillorn
In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.
{"title":"Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme","authors":"H. Tsai, H. Miyazoe, Josephine B. Chang, J. Pitera, Chi-Chun Liu, M. Brink, I. Lauer, Joy Y. Cheng, S. Engelmann, J. Rozen, J. Bucchignano, D. Klaus, S. Dawes, L. Gignac, C. Breslin, E. Joseph, D. Sanders, M. Colburn, M. Guillorn","doi":"10.1109/IEDM.2014.7047152","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047152","url":null,"abstract":"In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128738277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047009
D. Gardner, C. Holzwarth, Y. Liu, S. Clendenning, W. Jin, B. Moon, C. Pint, Z. Chen, E. Hannah, R. Chen, C. Wang, C. Chen, E. Makila, J. Gustafson
Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, and wearables with capacitors being ideal for devices requiring higher powers, low voltages, or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using porous Si nanostructures with very high surface-to-volume ratios and an electrolyte. Stability is achieved through ALD TiN or CVD carbon coatings. The use of Si processing methods creates the potential for on-chip energy storage.
{"title":"Integrated on-chip energy storage using porous-silicon electrochemical capacitors","authors":"D. Gardner, C. Holzwarth, Y. Liu, S. Clendenning, W. Jin, B. Moon, C. Pint, Z. Chen, E. Hannah, R. Chen, C. Wang, C. Chen, E. Makila, J. Gustafson","doi":"10.1109/IEDM.2014.7047009","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047009","url":null,"abstract":"Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, and wearables with capacitors being ideal for devices requiring higher powers, low voltages, or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using porous Si nanostructures with very high surface-to-volume ratios and an electrolyte. Stability is achieved through ALD TiN or CVD carbon coatings. The use of Si processing methods creates the potential for on-chip energy storage.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047128
K. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi
A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.
{"title":"Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology","authors":"K. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/IEDM.2014.7047128","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047128","url":null,"abstract":"A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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