Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047024
S. Tedde, Patric Buchele, R. Fischer, F. Steinbacher, O. Schmidt
Organic semiconductors provide exiting new opportunities for the realization of flat panel image sensors as they can be processed from the solution phase on large areas at low cost. In particular the high charge separation efficiency obtained in a bulk heterojunction (BHJ) enables the realization of organic photodiodes (OPDs). The spectral sensitivity of OPDs can be tailored to cover wavelengths ranging from the visible to the near infrared region. These sensitivities match perfectly to a variety of X-ray scintillators enabling a further improvement in the sensitivity range. In combination with an amorphous silicon (a-Si) thin film transistor (TFT) backplane technology, visible, near infrared (NIR) and X-ray image sensors have been realized. Thin film OPDs have been used in combination with a cesium iodide (CsI) scintillator in a traditional stacked geometry, proofing state-of-the art performance. Even more, it is possible to blend X-ray absorbing particles directly into the organic semiconductor thereby enabling quasi-direct X-ray converters with the promise to achieve a modulation transfer function (MTF) that is as high as in direct converting materials such as amorphous Selenium.
{"title":"Imaging with organic and hybrid photodetectors","authors":"S. Tedde, Patric Buchele, R. Fischer, F. Steinbacher, O. Schmidt","doi":"10.1109/IEDM.2014.7047024","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047024","url":null,"abstract":"Organic semiconductors provide exiting new opportunities for the realization of flat panel image sensors as they can be processed from the solution phase on large areas at low cost. In particular the high charge separation efficiency obtained in a bulk heterojunction (BHJ) enables the realization of organic photodiodes (OPDs). The spectral sensitivity of OPDs can be tailored to cover wavelengths ranging from the visible to the near infrared region. These sensitivities match perfectly to a variety of X-ray scintillators enabling a further improvement in the sensitivity range. In combination with an amorphous silicon (a-Si) thin film transistor (TFT) backplane technology, visible, near infrared (NIR) and X-ray image sensors have been realized. Thin film OPDs have been used in combination with a cesium iodide (CsI) scintillator in a traditional stacked geometry, proofing state-of-the art performance. Even more, it is possible to blend X-ray absorbing particles directly into the organic semiconductor thereby enabling quasi-direct X-ray converters with the promise to achieve a modulation transfer function (MTF) that is as high as in direct converting materials such as amorphous Selenium.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047009
D. Gardner, C. Holzwarth, Y. Liu, S. Clendenning, W. Jin, B. Moon, C. Pint, Z. Chen, E. Hannah, R. Chen, C. Wang, C. Chen, E. Makila, J. Gustafson
Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, and wearables with capacitors being ideal for devices requiring higher powers, low voltages, or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using porous Si nanostructures with very high surface-to-volume ratios and an electrolyte. Stability is achieved through ALD TiN or CVD carbon coatings. The use of Si processing methods creates the potential for on-chip energy storage.
{"title":"Integrated on-chip energy storage using porous-silicon electrochemical capacitors","authors":"D. Gardner, C. Holzwarth, Y. Liu, S. Clendenning, W. Jin, B. Moon, C. Pint, Z. Chen, E. Hannah, R. Chen, C. Wang, C. Chen, E. Makila, J. Gustafson","doi":"10.1109/IEDM.2014.7047009","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047009","url":null,"abstract":"Integrated on-chip energy storage is increasingly important in the fields of internet of things, energy harvesting, and wearables with capacitors being ideal for devices requiring higher powers, low voltages, or many thousands of cycles. This work demonstrates electrochemical capacitors fabricated using porous Si nanostructures with very high surface-to-volume ratios and an electrolyte. Stability is achieved through ALD TiN or CVD carbon coatings. The use of Si processing methods creates the potential for on-chip energy storage.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047128
K. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi
A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.
{"title":"Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology","authors":"K. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/IEDM.2014.7047128","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047128","url":null,"abstract":"A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047152
H. Tsai, H. Miyazoe, Josephine B. Chang, J. Pitera, Chi-Chun Liu, M. Brink, I. Lauer, Joy Y. Cheng, S. Engelmann, J. Rozen, J. Bucchignano, D. Klaus, S. Dawes, L. Gignac, C. Breslin, E. Joseph, D. Sanders, M. Colburn, M. Guillorn
In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.
{"title":"Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme","authors":"H. Tsai, H. Miyazoe, Josephine B. Chang, J. Pitera, Chi-Chun Liu, M. Brink, I. Lauer, Joy Y. Cheng, S. Engelmann, J. Rozen, J. Bucchignano, D. Klaus, S. Dawes, L. Gignac, C. Breslin, E. Joseph, D. Sanders, M. Colburn, M. Guillorn","doi":"10.1109/IEDM.2014.7047152","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047152","url":null,"abstract":"In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128738277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047058
T.-T Chen, C.-H Wen, J.C.-M. Huang, Y.-C Peng, S. Liu, S.-H Su, L.-H Cheng, H. Lai, Tingmao Liao, F. Lai, C.-W Cheng, C.K. Yang, J. Yang, Y. Hsieh, E. Salm, B. Reddy, F. Tsui, Y. Liu, R. Bashir, M. Chen
A 0.18μm SOI-CMOS bioelectrical sensing technology is introduced. An SOC chip integrates biosensor pixel arrays, controllers and amplifiers is used to demonstrate the performance of this technology. The pixel size in the pixel arrays is 10μm × 10μm, including biosensor, temperature sensor and heaters. The chip demonstrates detections of hydrogen ion concentration, enzymatic reactions and DNA hybridization with PCR. Experimental results show close to Nernst limit of 59mV/pH in ion concentration detection, sub-millimolar resolutions with 99.9% linearity in urea, and 400mV surface potential change in DNA hybridization. The SOC chip has an addressable temperature control for each pixel with embedded thermal sensors. A thermal time constant of 35msec/K and sub-degree localized temperature control are achieved. Order of magnitude improvements over previously reported are seen in both detectable minimum sample liquid volume and thermal time constant for PCR. This is a good demonstration of semiconductor technology for multi-biomarkers detection for medical applications.
{"title":"A semiconductor bio-electrical platform with addressable thermal control circuits for accelerated bioassay development","authors":"T.-T Chen, C.-H Wen, J.C.-M. Huang, Y.-C Peng, S. Liu, S.-H Su, L.-H Cheng, H. Lai, Tingmao Liao, F. Lai, C.-W Cheng, C.K. Yang, J. Yang, Y. Hsieh, E. Salm, B. Reddy, F. Tsui, Y. Liu, R. Bashir, M. Chen","doi":"10.1109/IEDM.2014.7047058","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047058","url":null,"abstract":"A 0.18μm SOI-CMOS bioelectrical sensing technology is introduced. An SOC chip integrates biosensor pixel arrays, controllers and amplifiers is used to demonstrate the performance of this technology. The pixel size in the pixel arrays is 10μm × 10μm, including biosensor, temperature sensor and heaters. The chip demonstrates detections of hydrogen ion concentration, enzymatic reactions and DNA hybridization with PCR. Experimental results show close to Nernst limit of 59mV/pH in ion concentration detection, sub-millimolar resolutions with 99.9% linearity in urea, and 400mV surface potential change in DNA hybridization. The SOC chip has an addressable temperature control for each pixel with embedded thermal sensors. A thermal time constant of 35msec/K and sub-degree localized temperature control are achieved. Order of magnitude improvements over previously reported are seen in both detectable minimum sample liquid volume and thermal time constant for PCR. This is a good demonstration of semiconductor technology for multi-biomarkers detection for medical applications.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130745682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046989
Xiang Li, Jiahao Kang, Xuejun Xie, W. Liu, D. Sarkar, Junfa Mao, K. Banerjee
Graphene is very attractive for densely integrated and flexible high-frequency/RF IC applications due to its extraordinary electrical, thermal, and mechanical properties. This work presents the design, fabrication, and characterization of graphene on-chip inductors. The skin effect in graphene inductors is investigated experimentally for the first time based on a circuit model proposed and fitted from fabricated ¾-, 2-, and 3-turn spiral inductors. The operation frequencies are in 40-60 GHz range and Q-factors are around 3. Design and fabrication optimizations are performed to guide future studies.
{"title":"Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect","authors":"Xiang Li, Jiahao Kang, Xuejun Xie, W. Liu, D. Sarkar, Junfa Mao, K. Banerjee","doi":"10.1109/IEDM.2014.7046989","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046989","url":null,"abstract":"Graphene is very attractive for densely integrated and flexible high-frequency/RF IC applications due to its extraordinary electrical, thermal, and mechanical properties. This work presents the design, fabrication, and characterization of graphene on-chip inductors. The skin effect in graphene inductors is investigated experimentally for the first time based on a circuit model proposed and fitted from fabricated ¾-, 2-, and 3-turn spiral inductors. The operation frequencies are in 40-60 GHz range and Q-factors are around 3. Design and fabrication optimizations are performed to guide future studies.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047051
S. Ambrogio, S. Balatti, V. McCaffrey, D. Wang, D. Ielmini
Resistive switching memory (RRAM) is one of the most promising emerging device technology for future storage and computing memories. As other emerging memories based on materials storage at the nanoscale, RRAM is affected by switching and read fluctuations. We addressed current fluctuation in RRAM at both cell and array levels. First, we present an analytical model for 1/f and random telegraph noise (RTN) in single (intrinsic) cells, allowing to predict time-dependent broadening of read current Iread distributions. Then we address tail cells with statistically-high noise in large arrays, revealing time-decaying random walk (RW) and intermittent RTN phenomena for the first time. A statistical noise model capable of explaining the current distribution broadening in RRAM arrays is finally developed and discussed.
{"title":"Impact of low-frequency noise on read distributions of resistive switching memory (RRAM)","authors":"S. Ambrogio, S. Balatti, V. McCaffrey, D. Wang, D. Ielmini","doi":"10.1109/IEDM.2014.7047051","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047051","url":null,"abstract":"Resistive switching memory (RRAM) is one of the most promising emerging device technology for future storage and computing memories. As other emerging memories based on materials storage at the nanoscale, RRAM is affected by switching and read fluctuations. We addressed current fluctuation in RRAM at both cell and array levels. First, we present an analytical model for 1/f and random telegraph noise (RTN) in single (intrinsic) cells, allowing to predict time-dependent broadening of read current Iread distributions. Then we address tail cells with statistically-high noise in large arrays, revealing time-decaying random walk (RW) and intermittent RTN phenomena for the first time. A statistical noise model capable of explaining the current distribution broadening in RRAM arrays is finally developed and discussed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"573 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047063
Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang
3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) Vth adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for Vth adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high Ion/Ioff ratio (>105), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such Vth adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.
{"title":"Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit","authors":"Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang","doi":"10.1109/IEDM.2014.7047063","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047063","url":null,"abstract":"3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) V<sub>th</sub> adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for V<sub>th</sub> adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high I<sub>on</sub>/I<sub>off</sub> ratio (>10<sup>5</sup>), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such V<sub>th</sub> adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"3 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047061
P. Hashemi, K. Balakrishnan, S. Engelmann, J. Ott, A. Khakifirooz, A. Baraskar, M. Hopstaken, J. Newbury, Kevin K. H. Chan, E. Leobandung, R. Mo, Dae-gyu Park
For the first time, we report fabrication and characterization of high-performance s-Si1-xGex-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization of s-SiGe fins with WFIN =3.3nm and devices with LG=16nm, in a CMOS compatible process. Using a Si-cap-free passivation, we report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1013cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. We also report the highest performance reported to date among sub-20nm-LG pMOS FinFETs at VDD=0.5V. In addition, hole transport as well as electrostatics, performance and leakage characteristics of SGOI FinFETs for various dimensions are comprehensively studied in this work.
{"title":"First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications","authors":"P. Hashemi, K. Balakrishnan, S. Engelmann, J. Ott, A. Khakifirooz, A. Baraskar, M. Hopstaken, J. Newbury, Kevin K. H. Chan, E. Leobandung, R. Mo, Dae-gyu Park","doi":"10.1109/IEDM.2014.7047061","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047061","url":null,"abstract":"For the first time, we report fabrication and characterization of high-performance s-Si<sub>1-x</sub>Ge<sub>x</sub>-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization of s-SiGe fins with W<sub>FIN</sub> =3.3nm and devices with L<sub>G</sub>=16nm, in a CMOS compatible process. Using a Si-cap-free passivation, we report SS=68mV/dec and μ<sub>eff</sub>=390±12 cm<sup>2</sup>/Vs at N<sub>inv</sub>=10<sup>13</sup>cm<sup>-2</sup>, outperforming the state-of-the-art relaxed Ge FinFETs. We also report the highest performance reported to date among sub-20nm-L<sub>G</sub> pMOS FinFETs at V<sub>DD</sub>=0.5V. In addition, hole transport as well as electrostatics, performance and leakage characteristics of SGOI FinFETs for various dimensions are comprehensively studied in this work.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"126 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132846244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047119
W. Liao, C. H. Chang, S. W. Huang, T. H. Liu, H. P. Hu, H. L. Lin, C. Tsai, C. Tsai, H. Chu, C. Pai, W. Chiang, S. Hou, S. Jeng, Doug C. H. Yu
A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (Vcc) of 1.8V, and a leakage current (ILK) below 1 fA/μm2 under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm2, respectively, with their corresponding ILK below 0.48, 0.19 and 0.09 fAmp/μm2. Process reliability related defect density (D0) of the interposer HK-MiM is as low as 0.095% cm-2 as judged by a 10 years lifetime breakdown voltage (Vbd) criterion at Vcc=3.2V. This low D0 ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm2 within the Si interposer. Moreover, the Vbd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., ILK & Vbd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.
{"title":"A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration","authors":"W. Liao, C. H. Chang, S. W. Huang, T. H. Liu, H. P. Hu, H. L. Lin, C. Tsai, C. Tsai, H. Chu, C. Pai, W. Chiang, S. Hou, S. Jeng, Doug C. H. Yu","doi":"10.1109/IEDM.2014.7047119","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047119","url":null,"abstract":"A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V<sub>cc</sub>) of 1.8V, and a leakage current (I<sub>LK</sub>) below 1 fA/μm<sup>2</sup> under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm<sup>2</sup>, respectively, with their corresponding I<sub>LK</sub> below 0.48, 0.19 and 0.09 fAmp/μm<sup>2</sup>. Process reliability related defect density (D<sub>0</sub>) of the interposer HK-MiM is as low as 0.095% cm<sup>-2</sup> as judged by a 10 years lifetime breakdown voltage (V<sub>bd</sub>) criterion at V<sub>cc</sub>=3.2V. This low D<sub>0</sub> ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm<sup>2</sup> within the Si interposer. Moreover, the V<sub>bd</sub> tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I<sub>LK</sub> & V<sub>bd</sub> tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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