Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047085
H. Lue, R. Lo, C. Hsieh, P. Du, Chih-Ping Chen, T. Hsu, Kuo-Ping Chang, Y. Shih, Chih-Yuan Lu
Erase saturation issue is a fundamental challenge for SONOS-type charge-trapping NAND Flash devices. Nowadays the most popular way to solve this issue is to pursue either curvature-induced field enhancement effect in the nano-wire SONOS device, or HK/MG to suppress the gate injection. However, both approaches have its drawback and reliability challenges. In this work, we propose a completely different approach that utilizes a double-trapping (or double storage) layer in a barrier engineered (BE) SONOS device to overcome the erase saturation ideally. A second nitride trapping layer (N3) is stacked on top of the first blocking oxide (O3) and 1st trapping layer (N2) of the original BE-SONOS device. Both theoretical model and experimental measured results indicate that when N3 stores sufficient electron charge it can greatly suppress gate injection, allowing continuous hole injection into N2 that gives a very deep erased Vt ~ -6V. A fully-integrated 3D Vertical Gate (VG) NAND Flash test chip using this novel device has been fabricated which demonstrates excellent MLC operation window and reliability. The flat and planar topology of this double-trapping BE-SONOS device enables minimal design rule of 3D NAND Flash array and possesses superb read disturb immunity.
{"title":"A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials","authors":"H. Lue, R. Lo, C. Hsieh, P. Du, Chih-Ping Chen, T. Hsu, Kuo-Ping Chang, Y. Shih, Chih-Yuan Lu","doi":"10.1109/IEDM.2014.7047085","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047085","url":null,"abstract":"Erase saturation issue is a fundamental challenge for SONOS-type charge-trapping NAND Flash devices. Nowadays the most popular way to solve this issue is to pursue either curvature-induced field enhancement effect in the nano-wire SONOS device, or HK/MG to suppress the gate injection. However, both approaches have its drawback and reliability challenges. In this work, we propose a completely different approach that utilizes a double-trapping (or double storage) layer in a barrier engineered (BE) SONOS device to overcome the erase saturation ideally. A second nitride trapping layer (N3) is stacked on top of the first blocking oxide (O3) and 1st trapping layer (N2) of the original BE-SONOS device. Both theoretical model and experimental measured results indicate that when N3 stores sufficient electron charge it can greatly suppress gate injection, allowing continuous hole injection into N2 that gives a very deep erased Vt ~ -6V. A fully-integrated 3D Vertical Gate (VG) NAND Flash test chip using this novel device has been fabricated which demonstrates excellent MLC operation window and reliability. The flat and planar topology of this double-trapping BE-SONOS device enables minimal design rule of 3D NAND Flash array and possesses superb read disturb immunity.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046969
T. Heidel, P. Gradzki
Wide bandgap power semiconductor devices offer substantial energy efficiency opportunities in a wide range of applications. However, to date, relatively high cost has impeded the widespread adoption of these devices in many high volume applications. Recent progress in high quality bulk GaN substrates offers a new potential pathway to the development of novel vertical power semiconductor devices in gallium nitride. If successfully developed, these devices could offer a pathway to functional cost parity with silicon-based power devices at higher power levels. The Advanced Research Projects Agency-Energy (ARPA-E)'s recently launched SWITCHES program is targeting the development of bulk GaN, 1200 V, 100 A transistors and diodes. In this paper, we give an overview of the technical approaches within the program and discuss some of the major anticipated challenges.
{"title":"Power devices on bulk gallium nitride substrates: An overview of ARPA-E's SWITCHES program","authors":"T. Heidel, P. Gradzki","doi":"10.1109/IEDM.2014.7046969","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046969","url":null,"abstract":"Wide bandgap power semiconductor devices offer substantial energy efficiency opportunities in a wide range of applications. However, to date, relatively high cost has impeded the widespread adoption of these devices in many high volume applications. Recent progress in high quality bulk GaN substrates offers a new potential pathway to the development of novel vertical power semiconductor devices in gallium nitride. If successfully developed, these devices could offer a pathway to functional cost parity with silicon-based power devices at higher power levels. The Advanced Research Projects Agency-Energy (ARPA-E)'s recently launched SWITCHES program is targeting the development of bulk GaN, 1200 V, 100 A transistors and diodes. In this paper, we give an overview of the technical approaches within the program and discuss some of the major anticipated challenges.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123187251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047029
Asamira Suzuki, Song-Hyok Choe, Yasuhiro Yamada, S. Nagai, M. Hiraiwa, N. Otsuka, D. Ueda
In this paper, we present a normally-off GaN-based transistor with extremely low on-state resistance fabricated by using Ge-doped n++GaN layer for ohmic contact. We developed a new GaN regrowth technique using Ge, which achieved extremely high doping level of 1 × 1020 cm-3, and thereby the lowest specific contact resistance of 1.5 × 10-6 Ω·cm2. Selectively deposited NiO gate using Atomic Layer Deposition (ALD) technique contributed to shorten the spacing between source and drain, making normally-off characteristics even with the 30% Al mole fraction of AlGaN. The fabricated device showed the record-breaking Ron of 0.95 Ω·mm with maximum drain current (Id,MAX) and transconductance (gm) of 1.1 A/mm and 490 mS/mm, respectively. It is noted that the obtained Vth was 0.55 V. An on/off current ratio of 5 × 106 is also achieved.
{"title":"Extremely low on-resistance enhancement-mode GaN-based HFET using Ge-doped regrowth technique","authors":"Asamira Suzuki, Song-Hyok Choe, Yasuhiro Yamada, S. Nagai, M. Hiraiwa, N. Otsuka, D. Ueda","doi":"10.1109/IEDM.2014.7047029","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047029","url":null,"abstract":"In this paper, we present a normally-off GaN-based transistor with extremely low on-state resistance fabricated by using Ge-doped n<sup>++</sup>GaN layer for ohmic contact. We developed a new GaN regrowth technique using Ge, which achieved extremely high doping level of 1 × 10<sup>20</sup> cm<sup>-3</sup>, and thereby the lowest specific contact resistance of 1.5 × 10<sup>-6</sup> Ω·cm<sup>2</sup>. Selectively deposited NiO gate using Atomic Layer Deposition (ALD) technique contributed to shorten the spacing between source and drain, making normally-off characteristics even with the 30% Al mole fraction of AlGaN. The fabricated device showed the record-breaking R<sub>on</sub> of 0.95 Ω·mm with maximum drain current (I<sup>d,MAX</sup>) and transconductance (g<sub>m</sub>) of 1.1 A/mm and 490 mS/mm, respectively. It is noted that the obtained V<sub>th</sub> was 0.55 V. An on/off current ratio of 5 × 10<sup>6</sup> is also achieved.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130180841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047004
V. Moroz, Lee Smith, Joanne Huang, Munkang Choi, T. Ma, Jie Liu, Yunqiang Zhang, Xi-Wei Lin, J. Kawa, Y. Saad
We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.
{"title":"Modeling and optimization of group IV and III–V FinFETs and nano-wires","authors":"V. Moroz, Lee Smith, Joanne Huang, Munkang Choi, T. Ma, Jie Liu, Yunqiang Zhang, Xi-Wei Lin, J. Kawa, Y. Saad","doi":"10.1109/IEDM.2014.7047004","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047004","url":null,"abstract":"We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046980
M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto
We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D converters (ADCs). Photodiode (PD) and inverter layers were directly bonded with the damascened Au electrodes to provide each pixel with in-pixel A/D conversion. We designed ADC with a pulse frequency output and fabricated a prototype sensor with 64 pixels. The developed sensor successfully captured video images and confirmed excellent linearity with a wide dynamic range of more than 80 dB, which showed feasibility of pixel-level 3D integration for high-performance CMOS image sensors.
{"title":"Three-dimensional integrated CMOS image sensors with pixel-parallel A/D converters fabricated by direct bonding of SOI layers","authors":"M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/IEDM.2014.7046980","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046980","url":null,"abstract":"We report the first demonstration of three-dimensional (3D) integrated CMOS image sensors with pixel-parallel A/D converters (ADCs). Photodiode (PD) and inverter layers were directly bonded with the damascened Au electrodes to provide each pixel with in-pixel A/D conversion. We designed ADC with a pulse frequency output and fabricated a prototype sensor with 64 pixels. The developed sensor successfully captured video images and confirmed excellent linearity with a wide dynamic range of more than 80 dB, which showed feasibility of pixel-level 3D integration for high-performance CMOS image sensors.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131841483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047131
M. Boniardi, Andrea Redaelli, C. Cupeta, F. Pellizzer, L. Crespi, Giuseppe D'Arrigo, A. L. Lacaita, G. Servalli
We reported here a comparative study of PCM cell architectures. The developed architectures are considered in a program/read efficiency framework and in an integration context. The Self-Heating approach is slightly more efficient, owing to heat generation happening directly within GST, but shows hazardous technology implementation with Ge2Sb2Te5, due to high aspect ratios. The heater-based Wall architecture represents the best and easiest solution for PCM from the technology standpoint: it features relaxed aspect ratios and benefits from lots of geometry-based knobs for optimization with slightly higher process complexity and slightly lower efficiency. Strengths and drawbacks of the different architectures are schematically reported in Fig. 14.
{"title":"Optimization metrics for Phase Change Memory (PCM) cell architectures","authors":"M. Boniardi, Andrea Redaelli, C. Cupeta, F. Pellizzer, L. Crespi, Giuseppe D'Arrigo, A. L. Lacaita, G. Servalli","doi":"10.1109/IEDM.2014.7047131","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047131","url":null,"abstract":"We reported here a comparative study of PCM cell architectures. The developed architectures are considered in a program/read efficiency framework and in an integration context. The Self-Heating approach is slightly more efficient, owing to heat generation happening directly within GST, but shows hazardous technology implementation with Ge2Sb2Te5, due to high aspect ratios. The heater-based Wall architecture represents the best and easiest solution for PCM from the technology standpoint: it features relaxed aspect ratios and benefits from lots of geometry-based knobs for optimization with slightly higher process complexity and slightly lower efficiency. Strengths and drawbacks of the different architectures are schematically reported in Fig. 14.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127572234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047162
W. Vandenberghe, M. Fischetti
Monolayer hexagonal tin (stannanane) is a topological insulator and upon functionalization with halogens, such as iodine, a gap exceeding 300 meV is obtained. In a stannanane ribbon the topologically protected edge states lead to very high conductivities and mobilities; moreover the conductivity is strongly dependent on the Fermi level. We show how this property can be exploited to make a topological-insulator field-effect transistor (TIFET). We simulate the input and output characteristics of the TIFET using a drift-diffusion-like approximation and obtain promising transistor characteristics with a high on-current which exceeds the off-current by over three orders of magnitude.
{"title":"Realizing a topological-insulator field-effect transistor using iodostannanane","authors":"W. Vandenberghe, M. Fischetti","doi":"10.1109/IEDM.2014.7047162","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047162","url":null,"abstract":"Monolayer hexagonal tin (stannanane) is a topological insulator and upon functionalization with halogens, such as iodine, a gap exceeding 300 meV is obtained. In a stannanane ribbon the topologically protected edge states lead to very high conductivities and mobilities; moreover the conductivity is strongly dependent on the Fermi level. We show how this property can be exploited to make a topological-insulator field-effect transistor (TIFET). We simulate the input and output characteristics of the TIFET using a drift-diffusion-like approximation and obtain promising transistor characteristics with a high on-current which exceeds the off-current by over three orders of magnitude.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"924 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127842779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047077
C. Raynaud
The focus of this paper is to highlight the challenges related to the increasing number of modes (GSM, WCDMA, LTE..) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multi-mode multi-band RF Front End modules.
{"title":"Technology pathfinders for low cost and highly integrated RF Front End modules","authors":"C. Raynaud","doi":"10.1109/IEDM.2014.7047077","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047077","url":null,"abstract":"The focus of this paper is to highlight the challenges related to the increasing number of modes (GSM, WCDMA, LTE..) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multi-mode multi-band RF Front End modules.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047125
D. Sekar, B. Bateman, U. Raghuram, S. Bowyer, Y. Bai, M. Calarrudo, P. Swab, J. Wu, S. Nguyen, N. Mishra, R. Meyer, M. Kellam, B. Haukness, C. Chevallier, H. Wu, H. Qian, F. Kreupl, G. Bronner
Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.
{"title":"Technology and circuit optimization of resistive RAM for low-power, reproducible operation","authors":"D. Sekar, B. Bateman, U. Raghuram, S. Bowyer, Y. Bai, M. Calarrudo, P. Swab, J. Wu, S. Nguyen, N. Mishra, R. Meyer, M. Kellam, B. Haukness, C. Chevallier, H. Wu, H. Qian, F. Kreupl, G. Bronner","doi":"10.1109/IEDM.2014.7047125","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047125","url":null,"abstract":"Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114877754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047000
Leqi Zhang, B. Govoreanu, A. Redolfi, D. Crotti, H. Hody, V. Paraschiv, S. Cosemans, C. Adelmann, T. Witters, S. Clima, Yangyin Chen, P. Hendrickx, D. Wouters, G. Groeseneken, M. Jurczak
An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.
{"title":"High-drive current (>1MA/cm2) and highly nonlinear (>103) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance","authors":"Leqi Zhang, B. Govoreanu, A. Redolfi, D. Crotti, H. Hody, V. Paraschiv, S. Cosemans, C. Adelmann, T. Witters, S. Clima, Yangyin Chen, P. Hendrickx, D. Wouters, G. Groeseneken, M. Jurczak","doi":"10.1109/IEDM.2014.7047000","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047000","url":null,"abstract":"An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117152167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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