As an example of the state-of-the-art of commercial MSI digital GaAs integrated circuits in high-volume production, a 16/8-bit MUX/DEMUX (multiplexer/demultiplexer) pair designed with a GaAs standard cell approach is presented. These designs feature ECL (emitter-coupled logic) compatibility and can support data rates up to 2 Gb/s. In addition to a review of the design aspects of these devices, the development of a high-speed production test system is presented.<>
{"title":"Design and test of a 2Gb/s GaAs 16/8 bit MUX/DEMUX pair","authors":"B. Cheney, P. Hamilton","doi":"10.1109/CICC.1988.20885","DOIUrl":"https://doi.org/10.1109/CICC.1988.20885","url":null,"abstract":"As an example of the state-of-the-art of commercial MSI digital GaAs integrated circuits in high-volume production, a 16/8-bit MUX/DEMUX (multiplexer/demultiplexer) pair designed with a GaAs standard cell approach is presented. These designs feature ECL (emitter-coupled logic) compatibility and can support data rates up to 2 Gb/s. In addition to a review of the design aspects of these devices, the development of a high-speed production test system is presented.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128097025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors explore in detail the possible approaches to the design of fully differential amplifiers needed to enhance performance in switched-capacitor circuits. This research has been focused on the behavior of the common-mode feedback circuits. Several structures are evaluated and compared. A strategy is presented that allows the design of differential amplifiers from any given set of specifications. As an illustration a 1-MHz differential amplifier has been designed.<>
{"title":"Design techniques for fully differential amplifiers","authors":"J. Haspeslagh, W. Sansen","doi":"10.1109/CICC.1988.20850","DOIUrl":"https://doi.org/10.1109/CICC.1988.20850","url":null,"abstract":"The authors explore in detail the possible approaches to the design of fully differential amplifiers needed to enhance performance in switched-capacitor circuits. This research has been focused on the behavior of the common-mode feedback circuits. Several structures are evaluated and compared. A strategy is presented that allows the design of differential amplifiers from any given set of specifications. As an illustration a 1-MHz differential amplifier has been designed.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115947598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 16-bit oversampling D/A (digital-to-analog) converter has been designed using a fourth-order all-digital noise-shaping loop followed by a 3-bit D/A converter. The 3-bit D/A converter, which uses a novel form of dynamic element matching achieves high accuracy and long-term stability without requiring precision matching of components. The harmonic distortion of the untrimmed monolithic CMOS prototype D/A converter is less than -90 dB. This converter achieves performance comparable to that of a 1-bit noise-shaping D/A that operates at nearly four times its clock rate.<>
{"title":"A 16-bit 4'th order noise-shaping D/A converter","authors":"L. Carley, John Kenney","doi":"10.1109/CICC.1988.20911","DOIUrl":"https://doi.org/10.1109/CICC.1988.20911","url":null,"abstract":"A 16-bit oversampling D/A (digital-to-analog) converter has been designed using a fourth-order all-digital noise-shaping loop followed by a 3-bit D/A converter. The 3-bit D/A converter, which uses a novel form of dynamic element matching achieves high accuracy and long-term stability without requiring precision matching of components. The harmonic distortion of the untrimmed monolithic CMOS prototype D/A converter is less than -90 dB. This converter achieves performance comparable to that of a 1-bit noise-shaping D/A that operates at nearly four times its clock rate.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An overview is presented of the user-to-network interface under development by study groups within the CCITT for use within the integrated services digital network (ISDN). Results are also presented of an international standardization effort.<>
{"title":"Overview of ISDN user-network interface","authors":"D.P.G. Schenkel","doi":"10.1109/CICC.1988.20905","DOIUrl":"https://doi.org/10.1109/CICC.1988.20905","url":null,"abstract":"An overview is presented of the user-to-network interface under development by study groups within the CCITT for use within the integrated services digital network (ISDN). Results are also presented of an international standardization effort.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134158937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SPAID is a design tool that maps digital-signal-processing (DSP) algorithms into multibus VLSI architectures. Explicit algorithm and VLSI performance constraints on throughput, latency, silicon area and power dissipation are obeyed. SPAID synthesizes a multibus multioperator (MBMO) data path with the minimum number of buses, operators and registers that satisfies the performance constaints. Design examples show that SPAID's performance compare favorably with existing synthesis systems for high-throughput distributed architectures.<>
{"title":"SPAID: an architectural synthesis tool for DSP custom applications","authors":"B. Haroun, M. Elmasry","doi":"10.1109/CICC.1988.20866","DOIUrl":"https://doi.org/10.1109/CICC.1988.20866","url":null,"abstract":"SPAID is a design tool that maps digital-signal-processing (DSP) algorithms into multibus VLSI architectures. Explicit algorithm and VLSI performance constraints on throughput, latency, silicon area and power dissipation are obeyed. SPAID synthesizes a multibus multioperator (MBMO) data path with the minimum number of buses, operators and registers that satisfies the performance constaints. Design examples show that SPAID's performance compare favorably with existing synthesis systems for high-throughput distributed architectures.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Murakami, T. Imai, K. Inoue, K. Hattori, Y. Matsuura, M. Hayashi, K. Miki, Y. Torimaru
The authors describe the design and fabrication results for a 185 K*6-bit field memory which is suitable for storing TV signals. This device offers an efficient and economical architecture for storing one field of NTSC signals on a single chip. It permits 3-fsc sampling and 6-bit quantization and contains all address-generating and refresh control circuits. Continuous read and write operation with a 60-ns cycle time, refresh-free operation, and 0.5-H jump function enhance the system performance. Standard cell design methodology is adopted to comply quickly with customer's requests.<>
{"title":"A 185 K*6 field memory for TV/VTR pictures","authors":"Y. Murakami, T. Imai, K. Inoue, K. Hattori, Y. Matsuura, M. Hayashi, K. Miki, Y. Torimaru","doi":"10.1109/CICC.1988.20798","DOIUrl":"https://doi.org/10.1109/CICC.1988.20798","url":null,"abstract":"The authors describe the design and fabrication results for a 185 K*6-bit field memory which is suitable for storing TV signals. This device offers an efficient and economical architecture for storing one field of NTSC signals on a single chip. It permits 3-fsc sampling and 6-bit quantization and contains all address-generating and refresh control circuits. Continuous read and write operation with a 60-ns cycle time, refresh-free operation, and 0.5-H jump function enhance the system performance. Standard cell design methodology is adopted to comply quickly with customer's requests.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132939816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Alexander, R. Kirk, R. Lathrop, R. Hall, G. Duffy
FUNSTRUX is a prototype tool for exploring the automatic creation of behavioral-level simulation models from netlists. FUNSTRUX uses a process called functional abstractions, in which each circuit component is replaced with its behavioral model, expressed in a temporal (time-based) algebra produced directly from its simulation code. The algebraic equations modeling each circuit component are then substituted into each other according to the circuit netlist, and simplified according to the rules of temporal algebra to create a model for the circuit. This model is then transformed into computer program code. Because FUNSTRUX works only from the circuit netlist and component models according to mathematical and logical principles, the abstracted models are accurate in both the function and time domains. When compared with component-level simulations, the models produced by FUNSTRUX have identical behavior for the same simulation input patterns, but simulate faster.<>
{"title":"Automatic generation of behavioral simulation models using functional abstraction","authors":"K. Alexander, R. Kirk, R. Lathrop, R. Hall, G. Duffy","doi":"10.1109/CICC.1988.20791","DOIUrl":"https://doi.org/10.1109/CICC.1988.20791","url":null,"abstract":"FUNSTRUX is a prototype tool for exploring the automatic creation of behavioral-level simulation models from netlists. FUNSTRUX uses a process called functional abstractions, in which each circuit component is replaced with its behavioral model, expressed in a temporal (time-based) algebra produced directly from its simulation code. The algebraic equations modeling each circuit component are then substituted into each other according to the circuit netlist, and simplified according to the rules of temporal algebra to create a model for the circuit. This model is then transformed into computer program code. Because FUNSTRUX works only from the circuit netlist and component models according to mathematical and logical principles, the abstracted models are accurate in both the function and time domains. When compared with component-level simulations, the models produced by FUNSTRUX have identical behavior for the same simulation input patterns, but simulate faster.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A marginal test of DRAMs (dynamic random-access memories) by masked alpha -radiation has been performed at all operation conditions. The averaged soft error rates (SERs) of individual circuits have been determined. Differences in SERs are used to analyze design margins and process tolerances. Measurements on a 256K DRAM show that asymmetric sense amplifiers caused by process tolerances can be discovered.<>
{"title":"Marginal test of DRAMs by masked alpha -radiation","authors":"D. Gleis, K. Hoffmann","doi":"10.1109/CICC.1988.20948","DOIUrl":"https://doi.org/10.1109/CICC.1988.20948","url":null,"abstract":"A marginal test of DRAMs (dynamic random-access memories) by masked alpha -radiation has been performed at all operation conditions. The averaged soft error rates (SERs) of individual circuits have been determined. Differences in SERs are used to analyze design margins and process tolerances. Measurements on a 256K DRAM show that asymmetric sense amplifiers caused by process tolerances can be discovered.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A modeling interface tool has been developed for the ADVICE circuit simulator. This tool allows model developers to provide model information in an ADVICE-like syntax and Fortran/C subroutines. The tool transforms information into ADVICE-acceptable format and links the user-supplied subroutines together with the partially prelinked ADVICE module to create a customized version of ADVICE. Then the new model can be accessed in the same way as that of the built-in models and tested in the context of circuit simulations. Problems in the model can be identified and resolved in a timely manner. Since the ADVICE internal status is made readily available, the user-supplied subroutines can interact effectively with the program. The tool helps not only to speed up model development and implementation, but also to broaden the scope of modeling for circuit simulators. It has been used to define semiconductor device models and macro models of medium-scale integrated components.<>
{"title":"ADMIT-ADVICE modeling interface tool","authors":"S. Liu, K. Hsu, P. Subramaniam","doi":"10.1109/CICC.1988.20813","DOIUrl":"https://doi.org/10.1109/CICC.1988.20813","url":null,"abstract":"A modeling interface tool has been developed for the ADVICE circuit simulator. This tool allows model developers to provide model information in an ADVICE-like syntax and Fortran/C subroutines. The tool transforms information into ADVICE-acceptable format and links the user-supplied subroutines together with the partially prelinked ADVICE module to create a customized version of ADVICE. Then the new model can be accessed in the same way as that of the built-in models and tested in the context of circuit simulations. Problems in the model can be identified and resolved in a timely manner. Since the ADVICE internal status is made readily available, the user-supplied subroutines can interact effectively with the program. The tool helps not only to speed up model development and implementation, but also to broaden the scope of modeling for circuit simulators. It has been used to define semiconductor device models and macro models of medium-scale integrated components.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An environment for SPICE called NECTAR has been developed which overcomes convergence and user-interface problems with SPICE by simulating the actions taken by an expert. NECTAR recognizes patterns which cause nonconvergence and provides ways to sidestep the problem. It identifies errors in the SPICE input file and automatically corrects them. It can be used as a circuit-design aid and improves the user interface for SPICE simulations. NECTAR derives its power from knowledge acquired from expert SPICE users and circuit designers.<>
{"title":"A knowledge-based SPICE environment for improved convergence and user friendliness","authors":"T.M. Kelessoglu, D. Pederson","doi":"10.1109/CICC.1988.20789","DOIUrl":"https://doi.org/10.1109/CICC.1988.20789","url":null,"abstract":"An environment for SPICE called NECTAR has been developed which overcomes convergence and user-interface problems with SPICE by simulating the actions taken by an expert. NECTAR recognizes patterns which cause nonconvergence and provides ways to sidestep the problem. It identifies errors in the SPICE input file and automatically corrects them. It can be used as a circuit-design aid and improves the user interface for SPICE simulations. NECTAR derives its power from knowledge acquired from expert SPICE users and circuit designers.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114760622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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