A 2500-gate programmable logic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standard third-party software tools. Global routing and subdivisable macrocells provide gate utilization factors equivalent to gate arrays.<>
{"title":"A 2500 gate programmable logic device with subdivisable macrocells","authors":"K. Gudger, G. S. Gongwer","doi":"10.1109/CICC.1988.20871","DOIUrl":"https://doi.org/10.1109/CICC.1988.20871","url":null,"abstract":"A 2500-gate programmable logic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standard third-party software tools. Global routing and subdivisable macrocells provide gate utilization factors equivalent to gate arrays.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the modeling and analysis procedures used to generate system-level wiring rules and net delay equations for IBM's 1.0- mu n CMOS standard-cell design system VLSI products. Business rationale, circuit and package models, and analysis methods are reviewed, as is a sample of the result in a midrange processor environment. High-performance single and multichip packages are used in the analysis, as are high-reliability under- and over-voltage specifications. These choices target the analysis for high-cost, high-performance applications.<>
描述了用于生成IBM 1.0 μ n CMOS标准单元设计系统VLSI产品的系统级布线规则和净延迟方程的建模和分析过程。业务原理，电路和封装模型，和分析方法进行了审查，作为一个样本的结果在中档处理器环境。分析中使用了高性能的单芯片和多芯片封装，以及高可靠性的欠压和过压规格。这些选择针对高成本，高性能应用程序的分析。
{"title":"Analysis and guidelines for high-speed VLSI system interconnections","authors":"C. B. Reynolds","doi":"10.1109/CICC.1988.20922","DOIUrl":"https://doi.org/10.1109/CICC.1988.20922","url":null,"abstract":"A description is given of the modeling and analysis procedures used to generate system-level wiring rules and net delay equations for IBM's 1.0- mu n CMOS standard-cell design system VLSI products. Business rationale, circuit and package models, and analysis methods are reviewed, as is a sample of the result in a midrange processor environment. High-performance single and multichip packages are used in the analysis, as are high-reliability under- and over-voltage specifications. These choices target the analysis for high-cost, high-performance applications.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116319428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tutorial overview is provided of high-performance integrated-circuit packaging. The approach is to (1) present the current trends in circuit performance, (2) discuss their impact on current packaging methods, and (3) present packaging concepts that are being offered as potential solutions. Particular emphasis is placed on design guidelines and material requirements.<>
{"title":"High performance integrated circuit packaging","authors":"B. C. Johnson","doi":"10.1109/CICC.1988.20918","DOIUrl":"https://doi.org/10.1109/CICC.1988.20918","url":null,"abstract":"A tutorial overview is provided of high-performance integrated-circuit packaging. The approach is to (1) present the current trends in circuit performance, (2) discuss their impact on current packaging methods, and (3) present packaging concepts that are being offered as potential solutions. Particular emphasis is placed on design guidelines and material requirements.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121895287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed from a cumbersome refresh control without access-time degradation. The TReD cell size is about 1/2.5 of a 4-transistor SRAM (static RAM) cell, so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM cell, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments.<>
{"title":"Transparent-refresh DRAM (TReD) using dual-port DRAM cell","authors":"T. Sakurai, K. Nogami, K. Sawada, T. Iizuka","doi":"10.1109/CICC.1988.20796","DOIUrl":"https://doi.org/10.1109/CICC.1988.20796","url":null,"abstract":"A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed from a cumbersome refresh control without access-time degradation. The TReD cell size is about 1/2.5 of a 4-transistor SRAM (static RAM) cell, so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM cell, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A monolithic 12-bit, 667-ns, two-step flash analog-to-digital converter has been implemented in standard 3- mu m CMOS technology. A 12-bit accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter's gain and offset errors.<>
一个单片12位，667-ns，两步闪存模数转换器已实现在标准的3 μ m CMOS技术。讨论了一个包含开关电容积分器和66个采样保持放大器的12位精确参考组。自校准技术用于校正转换器的增益和偏移误差
{"title":"A 667 ns, 12-bit two-step flash ADC","authors":"D. Kerth, N.S. Sooch, E. Swanson","doi":"10.1109/CICC.1988.20893","DOIUrl":"https://doi.org/10.1109/CICC.1988.20893","url":null,"abstract":"A monolithic 12-bit, 667-ns, two-step flash analog-to-digital converter has been implemented in standard 3- mu m CMOS technology. A 12-bit accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter's gain and offset errors.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel bipolar gate array family is described. The family consists of four arrays and two macro libraries. With ECL (emitter-coupled logic), complexity ranges from 1500 to 10 000 equivalent gates, and with CML (current-mode logic), complexity covers 2250 to 15000 equivalent gates. Both CML and ECL macros can be mixed on any customer-defined chip. This novel duality allows tradeoffs between performance, power, and complexity on the same chip. The I/Os are designed to serve both ECL and TTL interfaces.<>
{"title":"SH 100E 10000 gate ECL/15000 gate CML gate array family with ECL/TTL I/O compatibility","authors":"M. Franz, K. Delker, T. C. Whang, W. Wilhelm","doi":"10.1109/CICC.1988.20897","DOIUrl":"https://doi.org/10.1109/CICC.1988.20897","url":null,"abstract":"A novel bipolar gate array family is described. The family consists of four arrays and two macro libraries. With ECL (emitter-coupled logic), complexity ranges from 1500 to 10 000 equivalent gates, and with CML (current-mode logic), complexity covers 2250 to 15000 equivalent gates. Both CML and ECL macros can be mixed on any customer-defined chip. This novel duality allows tradeoffs between performance, power, and complexity on the same chip. The I/Os are designed to serve both ECL and TTL interfaces.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126295465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An algorithm is found for the time-domain analysis, of large-scale mixed analog/digital analysis of large-scale mixed analog/digital circuits. First, a set of basic IC functional blocks with their macromodels are defined. Then the concept of generalized node and the method of deriving generalized node equations of circuits are given. Finally, a selective trace iterative method used at the generalized node level to solve the generalized node equations is discussed. Four examples and their simulated results obtained using MIXMOD, which was developed with the authors' algorithm, are given.<>
{"title":"Simulation of mixed analog/digital circuits in time-domain by PWL macromodel approach","authors":"X. Wang, J. Hu","doi":"10.1109/CICC.1988.20811","DOIUrl":"https://doi.org/10.1109/CICC.1988.20811","url":null,"abstract":"An algorithm is found for the time-domain analysis, of large-scale mixed analog/digital analysis of large-scale mixed analog/digital circuits. First, a set of basic IC functional blocks with their macromodels are defined. Then the concept of generalized node and the method of deriving generalized node equations of circuits are given. Finally, a selective trace iterative method used at the generalized node level to solve the generalized node equations is discussed. Four examples and their simulated results obtained using MIXMOD, which was developed with the authors' algorithm, are given.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116212203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 13000 gate ECL TTL (emitter-coupled logic/transistor-transistor logic) bipolar logic array featuring 100-ps/gate delay has been developed. A revolutionary design technique was used to significantly reduce the worst-case power consumptions to less than 10 W. A bipolar channelless architecture helps minimize interconnect delay, but still maintains cell utilization to well over 95% without the use of quad-level metal.<>
{"title":"A 13000 gate 3 layer metal bipolar gate array","authors":"B. Coy, A. Mai, R. Yuen","doi":"10.1109/CICC.1988.20896","DOIUrl":"https://doi.org/10.1109/CICC.1988.20896","url":null,"abstract":"A 13000 gate ECL TTL (emitter-coupled logic/transistor-transistor logic) bipolar logic array featuring 100-ps/gate delay has been developed. A revolutionary design technique was used to significantly reduce the worst-case power consumptions to less than 10 W. A bipolar channelless architecture helps minimize interconnect delay, but still maintains cell utilization to well over 95% without the use of quad-level metal.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121185549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Callias, F. H. Salchli, D. Girard, M. Perrin, P. Aubert
A system of four integrated circuits developed for a programmable hearing aid is presented. The implementation of critical parts like the switched-capacitor filter bank, the low-noise preamplifiers, and the power supply are explained. The power is provided by a 1.3-V battery. The process used is the 3- mu m SACMOS from Faselec.<>
介绍了一种由四个集成电路组成的可编程助听器系统。对开关电容滤波器组、低噪声前置放大器和电源等关键部件的实现进行了说明。电源由1.3 v电池提供。所使用的工艺是来自Faselec.>的3 μ m SACMOS
{"title":"A set of 4 IC's in CMOS technology for a programmable hearing aid","authors":"F. Callias, F. H. Salchli, D. Girard, M. Perrin, P. Aubert","doi":"10.1109/CICC.1988.20854","DOIUrl":"https://doi.org/10.1109/CICC.1988.20854","url":null,"abstract":"A system of four integrated circuits developed for a programmable hearing aid is presented. The implementation of critical parts like the switched-capacitor filter bank, the low-noise preamplifiers, and the power supply are explained. The power is provided by a 1.3-V battery. The process used is the 3- mu m SACMOS from Faselec.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128032110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Friedman, D.M. Brinthaupt, D.-P. Chen, T.W. Deppa, J. Elward, E. Fields, J. Scott, T. R. Viswanathan
A dual-channel Sigma Delta voiceband codec meeting AT&T/CCITT specifications is described. The active area per channel is 13 mm/sup 2/ in a 1.5- mu m CMOS process. It has only one power supply, and the maximum power dissipation is 90 mW per channel. The crosstalk between channels is less than 71 dB.<>
描述了一种满足AT&T/CCITT规格的双通道Sigma Delta语音带编解码器。在1.5 μ m CMOS工艺中，每个通道的有源面积为13mm /sup 2/。它只有一个电源，每通道最大功耗为90mw。通道间串扰小于71 dB。
{"title":"A dual-channel Sigma Delta voiceband PCM codec","authors":"V. Friedman, D.M. Brinthaupt, D.-P. Chen, T.W. Deppa, J. Elward, E. Fields, J. Scott, T. R. Viswanathan","doi":"10.1109/CICC.1988.20908","DOIUrl":"https://doi.org/10.1109/CICC.1988.20908","url":null,"abstract":"A dual-channel Sigma Delta voiceband codec meeting AT&T/CCITT specifications is described. The active area per channel is 13 mm/sup 2/ in a 1.5- mu m CMOS process. It has only one power supply, and the maximum power dissipation is 90 mW per channel. The crosstalk between channels is less than 71 dB.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121645521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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