Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521769
Teng Seng Kiong, I. Ruzaini, S. Hian
Semiconductor chip packages is getting more challenging nowadays with increase of I/O and lead counts, especially for thin and large body packages such as LQFP (Low Profile Quad Flat Packages) and TQFP (Thin Quad Flat Packages). Material selection for such package especially for automotive product is a key for qualification success and long term package reliability to meet industry requirement. This paper presents mold compound selection and development works done with several mold compound candidates from different mold compound suppliers, which include screening of candidates based on assembly output response, package reliability stress study as well as molding parameters optimization and establishment for selected mold compound for CMOS90 176 lead LQFP 24×24mm package. Mold compound properties of each compound candidate were studied.
{"title":"Mold compound selection study for CMOS90 176 lead LQFP 24×24mm package","authors":"Teng Seng Kiong, I. Ruzaini, S. Hian","doi":"10.1109/IEMT.2012.6521769","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521769","url":null,"abstract":"Semiconductor chip packages is getting more challenging nowadays with increase of I/O and lead counts, especially for thin and large body packages such as LQFP (Low Profile Quad Flat Packages) and TQFP (Thin Quad Flat Packages). Material selection for such package especially for automotive product is a key for qualification success and long term package reliability to meet industry requirement. This paper presents mold compound selection and development works done with several mold compound candidates from different mold compound suppliers, which include screening of candidates based on assembly output response, package reliability stress study as well as molding parameters optimization and establishment for selected mold compound for CMOS90 176 lead LQFP 24×24mm package. Mold compound properties of each compound candidate were studied.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115006371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521816
Euclea Cheah Wuan Ning
Quite number of material was affected with sticky issue in an excursion which contributed to 0.10% yield drop. This excursion was caused by the presence of a strong bond between the UV tape and the device which made the device inseparable for tape and reel process. The study involves analysis of the root cause of the bonding layer as well as the measures taken to deal with the affected material and improvement actions done to qualify a new UV tape which does not have sticky issue. An alternate process was qualified to clear the affected material after thorough quality analysis was made. The yield and DPPM comparison of the UV tapes are taken into consideration to gauge the performance of the new UV tape while saving realized through qualification of the alternate process for sticky devices were discussed.
{"title":"Improvement journey of strip test sticky issue","authors":"Euclea Cheah Wuan Ning","doi":"10.1109/IEMT.2012.6521816","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521816","url":null,"abstract":"Quite number of material was affected with sticky issue in an excursion which contributed to 0.10% yield drop. This excursion was caused by the presence of a strong bond between the UV tape and the device which made the device inseparable for tape and reel process. The study involves analysis of the root cause of the bonding layer as well as the measures taken to deal with the affected material and improvement actions done to qualify a new UV tape which does not have sticky issue. An alternate process was qualified to clear the affected material after thorough quality analysis was made. The yield and DPPM comparison of the UV tapes are taken into consideration to gauge the performance of the new UV tape while saving realized through qualification of the alternate process for sticky devices were discussed.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134130564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521785
Tan Boo Wei, Wu Bin, E. Erfe
In recent years, MEMs IC (Micro-Electro-Mechanical Systems) has gained its growth momentum in the growing smart phone and other consumer electronic market. In addition to consumer electronic market, MEMs IC also has its application in industrial, medical, environmental and other specific application. With the high volume, lower cost demand for MEMs IC for consumer electronics, MEMs packaging trend has evolved towards using the existing matured lower cost packaging method including QFN (Quad Flat No-lead Package). In general, MEMS packaging is more challenging than normal IC packaging due to these devices generally required more stringent evaluation of suitable packaging material properties and manufacturing methodology.This paper introduces the package and process development of a Gyroscope MEMS on QFN packaging solution. The discussions include issues and challenges encountered during the package and process development, associated solutions in packaging material selection, and manufacturing techniques.
{"title":"MEMS in QFN","authors":"Tan Boo Wei, Wu Bin, E. Erfe","doi":"10.1109/IEMT.2012.6521785","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521785","url":null,"abstract":"In recent years, MEMs IC (Micro-Electro-Mechanical Systems) has gained its growth momentum in the growing smart phone and other consumer electronic market. In addition to consumer electronic market, MEMs IC also has its application in industrial, medical, environmental and other specific application. With the high volume, lower cost demand for MEMs IC for consumer electronics, MEMs packaging trend has evolved towards using the existing matured lower cost packaging method including QFN (Quad Flat No-lead Package). In general, MEMS packaging is more challenging than normal IC packaging due to these devices generally required more stringent evaluation of suitable packaging material properties and manufacturing methodology.This paper introduces the package and process development of a Gyroscope MEMS on QFN packaging solution. The discussions include issues and challenges encountered during the package and process development, associated solutions in packaging material selection, and manufacturing techniques.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129446583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521754
Y. Chek, T. C. Liew
They are various type of automated test equipment (ATE) in the market targeted for testing different types of devices. For example, high voltage and high current ATE for power management devices. A mix signal ATE for devices required analog and digital testing with relatively lower power demand compared to power management devices. What if the device required high power and mix signal testing together? The paper proposed a method to overcome the ATE capability constraint by using a floating power supply hardware module to step up the ATE supply voltage.
{"title":"Building a bipolar floating power supply module","authors":"Y. Chek, T. C. Liew","doi":"10.1109/IEMT.2012.6521754","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521754","url":null,"abstract":"They are various type of automated test equipment (ATE) in the market targeted for testing different types of devices. For example, high voltage and high current ATE for power management devices. A mix signal ATE for devices required analog and digital testing with relatively lower power demand compared to power management devices. What if the device required high power and mix signal testing together? The paper proposed a method to overcome the ATE capability constraint by using a floating power supply hardware module to step up the ATE supply voltage.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"80 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120991804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521767
F. Tan
Often times IC test solutions are constrained by the capability of the choice or targeted tester technology in terms of parametric or functional test specifications. This choice or targeted tester technology is usually the main or majority tester platform that is being used in a given organization. This paper will focus on a methodology to extend the capability of a said tester for a higher precision parametric measurement. It will not cover enhancement for functional test capability. In this paper, the use of circuit designs and programming solutions is detailed to create a novel test solution, by way of creative use of programmable-gain instrumentation amplifier in test board design, allowing IC test solution to extend beyond the specification of a targeted tester technology, ie extending the higher precision measurement capability onto the test board. This paper will also touch on the bonus financial benefit of such a test solution, in which cost savings can be achieved via targeted test board design changes together with its complementing programming solutions for use on existing tester solution instead of asset capitalization of new tester technology to enable the same IC test requirements.
{"title":"Extending tester capability by use of programmable-gain instrumentation amplifier as an IC test solution","authors":"F. Tan","doi":"10.1109/IEMT.2012.6521767","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521767","url":null,"abstract":"Often times IC test solutions are constrained by the capability of the choice or targeted tester technology in terms of parametric or functional test specifications. This choice or targeted tester technology is usually the main or majority tester platform that is being used in a given organization. This paper will focus on a methodology to extend the capability of a said tester for a higher precision parametric measurement. It will not cover enhancement for functional test capability. In this paper, the use of circuit designs and programming solutions is detailed to create a novel test solution, by way of creative use of programmable-gain instrumentation amplifier in test board design, allowing IC test solution to extend beyond the specification of a targeted tester technology, ie extending the higher precision measurement capability onto the test board. This paper will also touch on the bonus financial benefit of such a test solution, in which cost savings can be achieved via targeted test board design changes together with its complementing programming solutions for use on existing tester solution instead of asset capitalization of new tester technology to enable the same IC test requirements.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122627184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521800
S. Murali, J. Yeung, R. Perez
The new alloyed copper (Cu) wire exhibited homogeneous free air ball (FAB) formation and better electrochemical corrosion resistance than that of bare Cu wire. It also has comparable electrochemical corrosion resistance as palladium (Pd) coated Cu wire. The softness of the alloyed Cu wire and its FAB are uncompromised though the alloy composition is of 1N purity. This is attributed to the innovative process design to make the alloyed Cu wire properties close to bare Cu wire. The tensile behavior of alloyed Cu wire and grain structure of wire/FAB is also close to that of bare Cu wire for comparable and easy application. The looping performance is also observed to be similar to bare Cu wire and is within the defined dimensional tolerances required by the semiconductor packaging industries. In addition, it has a wider 2nd bond process window compared to bare Cu wire. On thermal ageing at 175°C for 2000hrs, the alloyed Cu wire bond showed no ball lift failure, wire break at neck or near to neck region, as expected. The rate of growth of intermetallics at the interface of alloyed Cu wire bond is slower than bare Cu wire bond and certain intermetallic phase is absent. The reaction rate calculated from Arrhenius plot showed lower value for an alloyed Cu wire bond than a bare Cu wire bond, which indicates slower interfacial diffusion with alloyed Cu wire bond. BHAST testing of molded device using green mold compound and bonded with alloyed Cu wire showed no failure until 168hrs at 130°C under +20V biased voltage.
{"title":"Alloyed copper bonding wire with homogeneous microstructure","authors":"S. Murali, J. Yeung, R. Perez","doi":"10.1109/IEMT.2012.6521800","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521800","url":null,"abstract":"The new alloyed copper (Cu) wire exhibited homogeneous free air ball (FAB) formation and better electrochemical corrosion resistance than that of bare Cu wire. It also has comparable electrochemical corrosion resistance as palladium (Pd) coated Cu wire. The softness of the alloyed Cu wire and its FAB are uncompromised though the alloy composition is of 1N purity. This is attributed to the innovative process design to make the alloyed Cu wire properties close to bare Cu wire. The tensile behavior of alloyed Cu wire and grain structure of wire/FAB is also close to that of bare Cu wire for comparable and easy application. The looping performance is also observed to be similar to bare Cu wire and is within the defined dimensional tolerances required by the semiconductor packaging industries. In addition, it has a wider 2nd bond process window compared to bare Cu wire. On thermal ageing at 175°C for 2000hrs, the alloyed Cu wire bond showed no ball lift failure, wire break at neck or near to neck region, as expected. The rate of growth of intermetallics at the interface of alloyed Cu wire bond is slower than bare Cu wire bond and certain intermetallic phase is absent. The reaction rate calculated from Arrhenius plot showed lower value for an alloyed Cu wire bond than a bare Cu wire bond, which indicates slower interfacial diffusion with alloyed Cu wire bond. BHAST testing of molded device using green mold compound and bonded with alloyed Cu wire showed no failure until 168hrs at 130°C under +20V biased voltage.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130933169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521836
M. Bixenman, J. Chan, T. C. Loy
Quality and reliability is a function of the manufacturing design that achieves repeatability and reproducibility. Designing advanced packages and assemblies is more difficult due to lead-free wetting and higher process temperature requirements. The associated manufacturing changes along with component miniaturization and board density increases complexity. From a cleaning perspective, many designers have poor insight into factors that assure a cleanable design. Solder paste selection, reflow conditions, component placement, component clearance (standoff), cleaning agent and cleaning equipment are important factors. Collaboration between process engineers, assembly designers, solder materials, cleaning agent and cleaning equipment experts can improve integration of the circuit design and assembly. Package design plays an important role when cleaning is required. Density of components, component layout, thermal heat requirements, and standoff height/clearance are key considerations. From a cleanability perspective, package on package, flip chip, bottom termination component (BTC) selection, solder mask definition, placement and layout influence the clearance gaps. The purpose of this research is to use a BTC test vehicle for studying factors related to the cleaning process. The designed experiment will present findings for removing flux residues under bottom termination components.
{"title":"Removal of flux residues from highly dense assemblies","authors":"M. Bixenman, J. Chan, T. C. Loy","doi":"10.1109/IEMT.2012.6521836","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521836","url":null,"abstract":"Quality and reliability is a function of the manufacturing design that achieves repeatability and reproducibility. Designing advanced packages and assemblies is more difficult due to lead-free wetting and higher process temperature requirements. The associated manufacturing changes along with component miniaturization and board density increases complexity. From a cleaning perspective, many designers have poor insight into factors that assure a cleanable design. Solder paste selection, reflow conditions, component placement, component clearance (standoff), cleaning agent and cleaning equipment are important factors. Collaboration between process engineers, assembly designers, solder materials, cleaning agent and cleaning equipment experts can improve integration of the circuit design and assembly. Package design plays an important role when cleaning is required. Density of components, component layout, thermal heat requirements, and standoff height/clearance are key considerations. From a cleanability perspective, package on package, flip chip, bottom termination component (BTC) selection, solder mask definition, placement and layout influence the clearance gaps. The purpose of this research is to use a BTC test vehicle for studying factors related to the cleaning process. The designed experiment will present findings for removing flux residues under bottom termination components.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114691384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521826
H. Kalami, M. Vahdati
In this paper a system is introduced which makes 3D parts and patterns. These patterns are made up of metal droplets. The raw material is in the shape of wire. Molten droplets are generated in the droplet generator nozzle and deposit on a substrate having proper deposition rate, temperature and volume. By settlement of droplets on certain places beside and over each other in several layers, arbitrary 3D object is constructed. 60%Sn/ 40%Pb alloy is used as raw material in the experiments and it is possible to use different wires with various diameters and materials with a little change in the apparatus. Here the design essence of the constructed droplet based manufacturing machine is investigated. Furthermore the dependency of drop volume to apparatus factors is presented. Knowing the drop size is essential in making samples. Drop size is dependent to nozzle diameter, nozzle temperature and wire-feed velocity. Temperature and deposition rate of droplets are controlled in the system. Some droplets and simple parts that are produced by this apparatus are presented too.
{"title":"Design and construction of a droplet based manufacturing machine","authors":"H. Kalami, M. Vahdati","doi":"10.1109/IEMT.2012.6521826","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521826","url":null,"abstract":"In this paper a system is introduced which makes 3D parts and patterns. These patterns are made up of metal droplets. The raw material is in the shape of wire. Molten droplets are generated in the droplet generator nozzle and deposit on a substrate having proper deposition rate, temperature and volume. By settlement of droplets on certain places beside and over each other in several layers, arbitrary 3D object is constructed. 60%Sn/ 40%Pb alloy is used as raw material in the experiments and it is possible to use different wires with various diameters and materials with a little change in the apparatus. Here the design essence of the constructed droplet based manufacturing machine is investigated. Furthermore the dependency of drop volume to apparatus factors is presented. Knowing the drop size is essential in making samples. Drop size is dependent to nozzle diameter, nozzle temperature and wire-feed velocity. Temperature and deposition rate of droplets are controlled in the system. Some droplets and simple parts that are produced by this apparatus are presented too.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123837790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521788
E. Chung, E. Erfe
One of the most recent developments in die attach adhesive technology comes in the form of Wafer Backside Coating (WBC) materials. These new materials overcome the perennial manufacturability issues with traditional dispense paste such as inconsistent fillet height and width, die tilt, insufficient coverage, etc. But unlike traditional dispense pastes, these WBC materials need to be stencil printed at the back of a wafer, b-staged cured and then mounted onto a wafer mounting tape. However, mounted stencil printed wafers have a limited storage life because the adhesion between the stencil printed material and the mounting tape tends to increase with time. The problem is more evident with wafers that have been sawn into very small die size since there would always be some excess dice left on the wafer tape after every production run. These remnant dice need to be stored in dry cabinets until the next production run is scheduled. The storage time could take months, depending on the device forecast. As a consequence, stencil printed wafers that exceed the storage life are scrapped. This paper presents the work done on material characterisation and process characterisation in order to define the maximum allowable storage life of stencil printed wafers with the objective of minimizing wastage. Material tests such as DSC, TGA, peel test were performed in parallel with process characterisation to relate die attach process responses with the degree of cure, adhesion strength between stencil print material and wafer mounting tape, as well as thermal stability of the Wafer Backside Coating material (or adhesive). MSL1 was performed to assess the package reliability with the extended storage life of stencil printed wafer on wafer mounting tape.
{"title":"Extending the storage life of stencil printed wafers for small die size on wafer mounting tape","authors":"E. Chung, E. Erfe","doi":"10.1109/IEMT.2012.6521788","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521788","url":null,"abstract":"One of the most recent developments in die attach adhesive technology comes in the form of Wafer Backside Coating (WBC) materials. These new materials overcome the perennial manufacturability issues with traditional dispense paste such as inconsistent fillet height and width, die tilt, insufficient coverage, etc. But unlike traditional dispense pastes, these WBC materials need to be stencil printed at the back of a wafer, b-staged cured and then mounted onto a wafer mounting tape. However, mounted stencil printed wafers have a limited storage life because the adhesion between the stencil printed material and the mounting tape tends to increase with time. The problem is more evident with wafers that have been sawn into very small die size since there would always be some excess dice left on the wafer tape after every production run. These remnant dice need to be stored in dry cabinets until the next production run is scheduled. The storage time could take months, depending on the device forecast. As a consequence, stencil printed wafers that exceed the storage life are scrapped. This paper presents the work done on material characterisation and process characterisation in order to define the maximum allowable storage life of stencil printed wafers with the objective of minimizing wastage. Material tests such as DSC, TGA, peel test were performed in parallel with process characterisation to relate die attach process responses with the degree of cure, adhesion strength between stencil print material and wafer mounting tape, as well as thermal stability of the Wafer Backside Coating material (or adhesive). MSL1 was performed to assess the package reliability with the extended storage life of stencil printed wafer on wafer mounting tape.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125001514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521757
D. Chir, R. Yeo
Plasma cleaning has been employed to increase the yield and reliability of gold wire bonding for many years in the IC packaging industry. However with the rising cost of gold, increasing numbers of manufacturers are transitioning to copper wire for the economic benefits. Bonding with copper wire is not without challenges; special equipment and different process parameters are required as copper wire is harder and is easily oxidised. Due to these properties of copper, obtaining an intimate contact between copper wire and bond pad can be difficult. Hence it is important to ensure that the bonding surface is clean of contaminants which could inhibit the bonding process. Bond pads with different surface materials exhibit different characteristics which necessitates different approaches to plasma treatment. Aluminium has a self-passivating property that helps it to be less susceptible to severe oxidation. Hence, the main concern for aluminium pads will be the removal of surface contaminants. On the other, hand copper is more susceptible to oxide formation. Therefore extra care must be taken to ensure a surface clean of both contaminants and oxides is achieved prior to the copper wire bonding process. This paper looks at the effects of plasma treatment for copper wire bonding, taking into account the prior considerations. It also discusses results which show that proper optimization of plasma process parameters is necessary to improve the uniformity of the wire bonding process. This is especially critical when trying to obtain a higher bonding yield for surfaces which exhibit poor bondability.
{"title":"Plasma process considerations for copper wire bonding","authors":"D. Chir, R. Yeo","doi":"10.1109/IEMT.2012.6521757","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521757","url":null,"abstract":"Plasma cleaning has been employed to increase the yield and reliability of gold wire bonding for many years in the IC packaging industry. However with the rising cost of gold, increasing numbers of manufacturers are transitioning to copper wire for the economic benefits. Bonding with copper wire is not without challenges; special equipment and different process parameters are required as copper wire is harder and is easily oxidised. Due to these properties of copper, obtaining an intimate contact between copper wire and bond pad can be difficult. Hence it is important to ensure that the bonding surface is clean of contaminants which could inhibit the bonding process. Bond pads with different surface materials exhibit different characteristics which necessitates different approaches to plasma treatment. Aluminium has a self-passivating property that helps it to be less susceptible to severe oxidation. Hence, the main concern for aluminium pads will be the removal of surface contaminants. On the other, hand copper is more susceptible to oxide formation. Therefore extra care must be taken to ensure a surface clean of both contaminants and oxides is achieved prior to the copper wire bonding process. This paper looks at the effects of plasma treatment for copper wire bonding, taking into account the prior considerations. It also discusses results which show that proper optimization of plasma process parameters is necessary to improve the uniformity of the wire bonding process. This is especially critical when trying to obtain a higher bonding yield for surfaces which exhibit poor bondability.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128935307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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