Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521775
B. Lai, R. Su
Green energy sources such as solar power, wind, and biomass ... are getting more attention especially after the nuclear crisis caused by earthquake in Mar. 2011 in Japan. The solar power has been considered to be the major contributor of the green energy. There are more than enough solar irradiations available to satisfy the world's energy demands. However the traditional photovoltaic (PV) systems suffer from various power losses, the performance shows average losses of about 20%-30% in electricity production. Some companies provide advance system architectures which can boost solar panel output power by up to 20%-25%. One of a key element of the system is the DC-DC converter [1]. Texas Instruments' high voltage gate driver ICs (HVIC) can be used as a DC-DC converter, half/full bridge applications or class-D audio amplifiers. There are challenges for the HVIC testing. First, the timing measurements for propagation delay matching in both buck and boost which need to be in nanoseconds range but the typical production automatic test equipment (ATE) specification of timing measurement unit (TMU) accuracy is approximate 2 nanoseconds (ns) and meanwhile, the output voltage of gate driver application can exceed 100 volts. Second, test time and multi-site testing have to be considered. In this paper, we have discussed the critical timing measurements and have successfully implemented the multi-site delay matching testing on IFLEXTM ATE platform with 100 picoseconds (ps) resolution while the boost is operating at 120V.
{"title":"Precision delay matching testing for gate driver ICs on IFLEX™ tester platform","authors":"B. Lai, R. Su","doi":"10.1109/IEMT.2012.6521775","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521775","url":null,"abstract":"Green energy sources such as solar power, wind, and biomass ... are getting more attention especially after the nuclear crisis caused by earthquake in Mar. 2011 in Japan. The solar power has been considered to be the major contributor of the green energy. There are more than enough solar irradiations available to satisfy the world's energy demands. However the traditional photovoltaic (PV) systems suffer from various power losses, the performance shows average losses of about 20%-30% in electricity production. Some companies provide advance system architectures which can boost solar panel output power by up to 20%-25%. One of a key element of the system is the DC-DC converter [1]. Texas Instruments' high voltage gate driver ICs (HVIC) can be used as a DC-DC converter, half/full bridge applications or class-D audio amplifiers. There are challenges for the HVIC testing. First, the timing measurements for propagation delay matching in both buck and boost which need to be in nanoseconds range but the typical production automatic test equipment (ATE) specification of timing measurement unit (TMU) accuracy is approximate 2 nanoseconds (ns) and meanwhile, the output voltage of gate driver application can exceed 100 volts. Second, test time and multi-site testing have to be considered. In this paper, we have discussed the critical timing measurements and have successfully implemented the multi-site delay matching testing on IFLEXTM ATE platform with 100 picoseconds (ps) resolution while the boost is operating at 120V.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128348888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521756
Y. C. Soh, C. C. Lim, T. Y. Hin, C. S. Teoh
Cu bonding continues to gain its popularity due to cheaper cost & better product performances. However, conventional bond pad structure such as Al, AlCu or AlSiCu pose higher risk of pad crater or lifted metal, as Cu bonded ball is 30% harder than Au bonded ball. Hence, this limits the progress of Cu bonding conversion for <;1μm pad thickness & sensitive BPOA (Bond Pad Over Active) devices. With the plan of speed up Cu bonding conversion, harder bond pad structure that made of NiPd stack was introduced to overcome such risks that encountered on conventional bond pad structure. This paper will discuss the development work to establish 1.0 mils Cu bonding process for NiPd bond pad on QFN package. Feasibility study stage includes NiPd stack plating thickness evaluation; CMP (Chemical Mechanical Polishing) bond pad topography impact on bondability; plasma cleaning evaluation on NiPd pad. Response surface methodology (RSM) was used as design of experiment (DOE) tools to analyze critical bonding characteristics & determine process window through prediction profiler & contour plot. Look Ahead Reliability (LAR) units were built to assess the reliability performances of Cu bonding on NiPd bond pad with standard stress tests such as MSL1, Autoclave, TMCL & HTOL. Zero reliability failure was reported on Cu bonding to NiPd pad upon completion of LAR. However ground bond broken weld was observed at TMCL. Existing ground bond loop distance from die edge was too short, causing steep looping profile & it was broken under thermo-mechanical stress. New design rule for loop distance from die edge will be studied to understand the shortest distance allowable for Cu wire. With all the thorough process assessments & design rule limitation understanding, qualification build could be arranged to qualify NiPd bond pad with Cu bonding. More products would be converted to NiPd bond pad for Cu bonding conversion once the new technology has been qualified.
由于更便宜的成本和更好的产品性能，铜键合继续受到欢迎。然而，传统的键合垫结构如Al、AlCu或AlSiCu，由于Cu键合球的硬度比Au键合球高30%，因此存在较高的垫坑或抬升金属的风险。因此，这限制了< 1μm焊板厚度和敏感BPOA (Bond pad Over Active)器件的Cu键合转换的进展。在加快铜键转换的计划下，引入了由NiPd堆制成的更硬的键垫结构，克服了传统键垫结构遇到的这些风险。本文将讨论建立QFN封装上NiPd键合垫1.0 mils铜键合工艺的开发工作。可行性研究阶段包括NiPd堆镀厚度评估;化学机械抛光(CMP)粘结垫形貌对粘结性的影响NiPd垫的等离子清洗评价。采用响应面法(RSM)作为实验设计(DOE)工具，通过预测剖面仪和等高线图分析键合关键特性并确定工艺窗口。建立了前瞻性可靠性(LAR)单元，通过MSL1、Autoclave、TMCL和HTOL等标准应力测试，评估NiPd键合垫上Cu键合的可靠性性能。据报道，在完成LAR后，铜与NiPd焊盘的粘合可靠性为零。然而，在TMCL上观察到接地键断焊缝。现有接地键环距模具边缘距离过短，导致环形陡，在热机械应力作用下断裂。研究环距模具边缘的新设计规则，以确定铜丝允许的最短距离。通过所有彻底的工艺评估和设计规则限制的理解，可以安排资格构建来对带有Cu键合的NiPd键合垫进行资格认证。一旦新技术合格，将有更多的产品转化为NiPd键垫进行铜键转换。
{"title":"Cu bonding development & challenges on NiPd bond pad","authors":"Y. C. Soh, C. C. Lim, T. Y. Hin, C. S. Teoh","doi":"10.1109/IEMT.2012.6521756","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521756","url":null,"abstract":"Cu bonding continues to gain its popularity due to cheaper cost & better product performances. However, conventional bond pad structure such as Al, AlCu or AlSiCu pose higher risk of pad crater or lifted metal, as Cu bonded ball is 30% harder than Au bonded ball. Hence, this limits the progress of Cu bonding conversion for <;1μm pad thickness & sensitive BPOA (Bond Pad Over Active) devices. With the plan of speed up Cu bonding conversion, harder bond pad structure that made of NiPd stack was introduced to overcome such risks that encountered on conventional bond pad structure. This paper will discuss the development work to establish 1.0 mils Cu bonding process for NiPd bond pad on QFN package. Feasibility study stage includes NiPd stack plating thickness evaluation; CMP (Chemical Mechanical Polishing) bond pad topography impact on bondability; plasma cleaning evaluation on NiPd pad. Response surface methodology (RSM) was used as design of experiment (DOE) tools to analyze critical bonding characteristics & determine process window through prediction profiler & contour plot. Look Ahead Reliability (LAR) units were built to assess the reliability performances of Cu bonding on NiPd bond pad with standard stress tests such as MSL1, Autoclave, TMCL & HTOL. Zero reliability failure was reported on Cu bonding to NiPd pad upon completion of LAR. However ground bond broken weld was observed at TMCL. Existing ground bond loop distance from die edge was too short, causing steep looping profile & it was broken under thermo-mechanical stress. New design rule for loop distance from die edge will be studied to understand the shortest distance allowable for Cu wire. With all the thorough process assessments & design rule limitation understanding, qualification build could be arranged to qualify NiPd bond pad with Cu bonding. More products would be converted to NiPd bond pad for Cu bonding conversion once the new technology has been qualified.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124637288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521821
G. Henshall, K. Sweatman, K. Howell, U. M. de Tino, J. Miremadi, R. Parker, R. Coyle, J. Smetana, J. Nguyen, Weiping Liu, R. Pandher, D. Daily, M. Currie, Tae-Kyu Lee, J. Silk, B. Jones, S. Tisdale, F. Hua, M. Osterman, T. Sack, P. Snugovsky, A. Syed, A. Allen, J. Arnold, D. Moore, G. Chang, E. Benedetto
Significant innovations in Pb-free solder alloy formulations are being driven by volume manufacturing and field experiences. As a result, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common near-eutectic Sn-Ag-Cu (SAC) alloys first established as replacements for Sn-37Pb. The increasing number of Pb-free alloys provides opportunities to address shortcomings of near-eutectic SAC, such as poor mechanical shock performance, but also introduces a variety of technical and logistical risks. Since 2008, the Pb-Free Alloy Characterization Program sponsored by the International Electronics Manufacturing Initiative (iNEMI) has been working to fill the gap in knowledge associated with thermal fatigue resistance of these new solder alloys. Results from the extensive experimental program are now becoming available and are being published through a series of publications (see References). This paper provides a summary of the overall iNEMI's program goals, the experimental structure, and the results and analysis of thermal cycling for low silver alloys, containing 1 wt.% or less Ag. Results indicated that there is a correlation between the characteristic life of short dwell thermal cycles and Ag content. Increase in the Ag content increased the characteristic life. Another important finding is that all low-and no-Ag alloys performed better than Sn-37Pb under the test conditions. Finally, as the stress levels increase during thermal cycling, the performance differences between the Pb-free alloys diminish, and their performance appears to be approaching that of Sn-37Pb.
{"title":"iNEMI Pb-free alloy characterization project report: Thermal fatigue results for low and no-Ag alloys","authors":"G. Henshall, K. Sweatman, K. Howell, U. M. de Tino, J. Miremadi, R. Parker, R. Coyle, J. Smetana, J. Nguyen, Weiping Liu, R. Pandher, D. Daily, M. Currie, Tae-Kyu Lee, J. Silk, B. Jones, S. Tisdale, F. Hua, M. Osterman, T. Sack, P. Snugovsky, A. Syed, A. Allen, J. Arnold, D. Moore, G. Chang, E. Benedetto","doi":"10.1109/IEMT.2012.6521821","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521821","url":null,"abstract":"Significant innovations in Pb-free solder alloy formulations are being driven by volume manufacturing and field experiences. As a result, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common near-eutectic Sn-Ag-Cu (SAC) alloys first established as replacements for Sn-37Pb. The increasing number of Pb-free alloys provides opportunities to address shortcomings of near-eutectic SAC, such as poor mechanical shock performance, but also introduces a variety of technical and logistical risks. Since 2008, the Pb-Free Alloy Characterization Program sponsored by the International Electronics Manufacturing Initiative (iNEMI) has been working to fill the gap in knowledge associated with thermal fatigue resistance of these new solder alloys. Results from the extensive experimental program are now becoming available and are being published through a series of publications (see References). This paper provides a summary of the overall iNEMI's program goals, the experimental structure, and the results and analysis of thermal cycling for low silver alloys, containing 1 wt.% or less Ag. Results indicated that there is a correlation between the characteristic life of short dwell thermal cycles and Ag content. Increase in the Ag content increased the characteristic life. Another important finding is that all low-and no-Ag alloys performed better than Sn-37Pb under the test conditions. Finally, as the stress levels increase during thermal cycling, the performance differences between the Pb-free alloys diminish, and their performance appears to be approaching that of Sn-37Pb.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521789
E. Chung, E. Erfe
For most high-power semiconductor device, the predominant heat dissipation path is through the die attach material. Hence, die attach material must possess excellent conductivity, both thermally and also electrically. Metal based solder alloys such as AuSi and AuSn possess these desired properties, but are relatively more expensive as compared to organic-based adhesives filled with conductive metals such as silver or other metal alloy. This paper discusses the various methodologies used during the material selection of high thermally conductive die attach dispense adhesives intended for power applications, focusing on Ag-filled and mixed-metal alloy adhesives. Carsem's own materials lab was utilized to perform thermal analyses, viscosity and electrical testing on different die attach dispense adhesives. After material characterisation, process characterisation was carried out in order to determine their dispensability and manufacturability. Candidate materials which exhibited good electrical and process characteristics were shortlisted for further evaluation in actual assembly. Finally, reliability testing was performed in order to assess the package reliability.
{"title":"Material characterisation of high thermally conductive die attach pastes for high power applications","authors":"E. Chung, E. Erfe","doi":"10.1109/IEMT.2012.6521789","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521789","url":null,"abstract":"For most high-power semiconductor device, the predominant heat dissipation path is through the die attach material. Hence, die attach material must possess excellent conductivity, both thermally and also electrically. Metal based solder alloys such as AuSi and AuSn possess these desired properties, but are relatively more expensive as compared to organic-based adhesives filled with conductive metals such as silver or other metal alloy. This paper discusses the various methodologies used during the material selection of high thermally conductive die attach dispense adhesives intended for power applications, focusing on Ag-filled and mixed-metal alloy adhesives. Carsem's own materials lab was utilized to perform thermal analyses, viscosity and electrical testing on different die attach dispense adhesives. After material characterisation, process characterisation was carried out in order to determine their dispensability and manufacturability. Candidate materials which exhibited good electrical and process characteristics were shortlisted for further evaluation in actual assembly. Finally, reliability testing was performed in order to assess the package reliability.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115747250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521799
H. Auer, H. Hirscher, P. Desjardins, J. Weichart
As with any emerging technology, 2.5D and 3D IC TSV packaging integration brings new challenges. Amongst others, we will review thin wafer handling, organic passivation outgassing control, glue layers critical thermal management and TSV high aspect ratio barrier and seed layers deposition. We will then demonstrate how Oerlikon's PVD technology has managed to address each of these issues with manufacturing low COO solutions.
与任何新兴技术一样，2.5D和3D IC TSV封装集成带来了新的挑战。其中，我们将回顾薄晶圆处理，有机钝化除气控制，胶层临界热管理和TSV高宽高比屏障和种子层沉积。然后，我们将展示欧瑞康的PVD技术如何通过制造低COO解决方案来解决这些问题。
{"title":"Low COO PVD solutions addressing 2.5D and 3D TSV packaging challenges","authors":"H. Auer, H. Hirscher, P. Desjardins, J. Weichart","doi":"10.1109/IEMT.2012.6521799","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521799","url":null,"abstract":"As with any emerging technology, 2.5D and 3D IC TSV packaging integration brings new challenges. Amongst others, we will review thin wafer handling, organic passivation outgassing control, glue layers critical thermal management and TSV high aspect ratio barrier and seed layers deposition. We will then demonstrate how Oerlikon's PVD technology has managed to address each of these issues with manufacturing low COO solutions.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126421594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521830
Mian Tao, S. Lee, M. Yuen, Guoqi Zhang, W. V. van Driel
In the literature, the junction temperature of a light-emitting diode (LED) has been considered having a uniform distribution over the whole chip. Such a perception is based on the assumption that the die attach adhesive (DAA) covers the whole bottom of the LED chip with a uniform thickness. However, in reality, there may be insufficient DAA during the chip mounting process. As a result, non-uniform junction temperature may be induced and hot spots could occur. Therefore, it is essential to investigate the effect of DAA on the creation of hot spots at the LED junction. In the present study, LED chips were mounted with various amounts of DAA on a leadframe designed for high power LED. A high resolution infra-red (IR) camera was used to measure the temperature on the surface of the LED chip. The obtained IR images were calibrated carefully in order to eliminate the influence from IR emissivity. Hot spots were observed at the junction areas where DAA was missing. Detailed analysis for illustrating the effect of DAA distribution on hot spots is presented and reasons for such a phenomenon are discussed.
{"title":"Effect of die attach adhesive defects on the junction temperature uniformity of LED chips","authors":"Mian Tao, S. Lee, M. Yuen, Guoqi Zhang, W. V. van Driel","doi":"10.1109/IEMT.2012.6521830","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521830","url":null,"abstract":"In the literature, the junction temperature of a light-emitting diode (LED) has been considered having a uniform distribution over the whole chip. Such a perception is based on the assumption that the die attach adhesive (DAA) covers the whole bottom of the LED chip with a uniform thickness. However, in reality, there may be insufficient DAA during the chip mounting process. As a result, non-uniform junction temperature may be induced and hot spots could occur. Therefore, it is essential to investigate the effect of DAA on the creation of hot spots at the LED junction. In the present study, LED chips were mounted with various amounts of DAA on a leadframe designed for high power LED. A high resolution infra-red (IR) camera was used to measure the temperature on the surface of the LED chip. The obtained IR images were calibrated carefully in order to eliminate the influence from IR emissivity. Hot spots were observed at the junction areas where DAA was missing. Detailed analysis for illustrating the effect of DAA distribution on hot spots is presented and reasons for such a phenomenon are discussed.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521751
M.N.M. Ching, L. Ying
The heat affected zone (HAZ) is the major concern during wire loop formation. Wire looping is a process that involves machine mechanical movement as well as wire physical bending. Commonly, in order to avoid failure caused by mechanical stresses, most of the wire loop process setup will tend to avoid the HAZ. There are several factors contributing towards the length of HAZ. A study done by Sun et. al. explains that the increase of electron flame off (EFO) time is proportional towards the increase of HAZ length. Ultra low loop introduced an extreme bending process on top of the copper ball bond at the HAZ area. Wire necking or fracture is the major concern due to the effect of folding, bending and compression of the wire. The main focus of this paper will discuss on the detail and thorough characterization of ultra low loop, as low as 40-50um height in 22um copper wire in terms of process capability & robustness, material property & behavior (e.g.: grain structure) as well as the mechanical property (e.g.: hardness & strength). Common analytical method and material preparation setup error will be discussed and explained to understand the reasons behind in the data variations obtained.
{"title":"Characterization on ultra low loop Cu wire property and behavior","authors":"M.N.M. Ching, L. Ying","doi":"10.1109/IEMT.2012.6521751","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521751","url":null,"abstract":"The heat affected zone (HAZ) is the major concern during wire loop formation. Wire looping is a process that involves machine mechanical movement as well as wire physical bending. Commonly, in order to avoid failure caused by mechanical stresses, most of the wire loop process setup will tend to avoid the HAZ. There are several factors contributing towards the length of HAZ. A study done by Sun et. al. explains that the increase of electron flame off (EFO) time is proportional towards the increase of HAZ length. Ultra low loop introduced an extreme bending process on top of the copper ball bond at the HAZ area. Wire necking or fracture is the major concern due to the effect of folding, bending and compression of the wire. The main focus of this paper will discuss on the detail and thorough characterization of ultra low loop, as low as 40-50um height in 22um copper wire in terms of process capability & robustness, material property & behavior (e.g.: grain structure) as well as the mechanical property (e.g.: hardness & strength). Common analytical method and material preparation setup error will be discussed and explained to understand the reasons behind in the data variations obtained.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128483541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521805
M. Whitmore, J. Schake, C. Ashmore
Miniaturisation is pushing the stencil printing process. As features become smaller, solder paste transfer efficiency is becoming more critical. In latest research work, actual paste deposit volumes and transfer efficiency have been monitored and compared for both square and round apertures with area ratio's ranging from 0.20 thru to 1.35. This covers apertures sizes of between 100 and 550 microns in a nominal 100 micron thick stencil foil. In addition, the effect of ultrasonically activated squeegees (ProActiv) has been assessed as part of the same experiment. A further comparison has also been made between type 4 and type 4.5 solder paste aswell. The data presented here will help provide guidelines for stencil aperture designs and strategies for ultra-fille pitch components such as 0.3CSP's.
{"title":"The impact of stencil aperture design for next generation ultra-fine pitch printing","authors":"M. Whitmore, J. Schake, C. Ashmore","doi":"10.1109/IEMT.2012.6521805","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521805","url":null,"abstract":"Miniaturisation is pushing the stencil printing process. As features become smaller, solder paste transfer efficiency is becoming more critical. In latest research work, actual paste deposit volumes and transfer efficiency have been monitored and compared for both square and round apertures with area ratio's ranging from 0.20 thru to 1.35. This covers apertures sizes of between 100 and 550 microns in a nominal 100 micron thick stencil foil. In addition, the effect of ultrasonically activated squeegees (ProActiv) has been assessed as part of the same experiment. A further comparison has also been made between type 4 and type 4.5 solder paste aswell. The data presented here will help provide guidelines for stencil aperture designs and strategies for ultra-fille pitch components such as 0.3CSP's.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129389272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521839
Y. Toyama, I. Shohji
Tensile properties of several lead-free solder were investigated at a strain rate ranging from 2 × 10-3 s-1 to 2 × 102 s-1 at room temperature using micro-size specimens. Five kinds of lead-free solder which are Sn-3mass%Ag-0.5mass%Cu, Sn-0.7mass%Cu, Sn-5mass%Sb, Sn-8.5mass%Sb and Sn-13mass%Sb were prepared. Sn-37mass%Pb solder was also prepared as a comparison. Tensile strength increases with increasing the strain rate and is proportional to the logarithm of the strain rate. In Sn-3Ag-0.5Cu and Sn-37Pb solder, specimens were necked uniformly and dimple fracture mainly occurred. Tensile strength became relatively high in those solder. In Sn-0.7Cu, Sn-5Sb and Sn-8.5Sb solder, specimens were not necked uniformly and chisel point fracture was observed. Tensile strength of such solder became relatively low compared with those of Sn-3Ag-0.5Cu and Sn-37Pb solder. In Sn-13Sb solder, brittle fracture occurred and elongation decreased compared with other solder. For elongation, Sn-5Sb and Sn-8.5Sb solder showed an excellent value of approximately 90% at the maximum strain rate investigated.
{"title":"Effect of strain rate on tensile properties of miniature size lead-free alloys","authors":"Y. Toyama, I. Shohji","doi":"10.1109/IEMT.2012.6521839","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521839","url":null,"abstract":"Tensile properties of several lead-free solder were investigated at a strain rate ranging from 2 × 10-3 s-1 to 2 × 102 s-1 at room temperature using micro-size specimens. Five kinds of lead-free solder which are Sn-3mass%Ag-0.5mass%Cu, Sn-0.7mass%Cu, Sn-5mass%Sb, Sn-8.5mass%Sb and Sn-13mass%Sb were prepared. Sn-37mass%Pb solder was also prepared as a comparison. Tensile strength increases with increasing the strain rate and is proportional to the logarithm of the strain rate. In Sn-3Ag-0.5Cu and Sn-37Pb solder, specimens were necked uniformly and dimple fracture mainly occurred. Tensile strength became relatively high in those solder. In Sn-0.7Cu, Sn-5Sb and Sn-8.5Sb solder, specimens were not necked uniformly and chisel point fracture was observed. Tensile strength of such solder became relatively low compared with those of Sn-3Ag-0.5Cu and Sn-37Pb solder. In Sn-13Sb solder, brittle fracture occurred and elongation decreased compared with other solder. For elongation, Sn-5Sb and Sn-8.5Sb solder showed an excellent value of approximately 90% at the maximum strain rate investigated.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521810
M. Majid, C. Khor, M. K. Abdullah, M. Z. Abdullah, W. Rahiman, A. Jappar, M. Aris
In the present paper, a 3D numerical prediction has been made to study the flip chip underfill process using the epoxy molding compound (EMC). The prediction considered the EMC filling behavior for the flow induced between the tiny gap of silicon die and substrate. Three different arrangements of the solder bump have been tested in this work. The EMC is treated as a generalized Newtonian fluid (GNF). The developed methodology combines the Kawamura and Kawahara technique, and the melt front volume tracking method to solve the two-phase flow field around the solder bumps. The Castro-Macosko rheology model with Arrhenius temperature dependence is adopted in the viscosity model. The predictions are made to investigate the filling patterns at several time intervals. The results show that the underfill process for solder bump with Type A gives minimum filling time and better filling yield. The effect of gap height between the plate and substrate on the underfill process also has been considered. The close agreement between prediction and experimental results from the previous work illustrates the applicability of the present numerical model.
{"title":"Three dimensional numerical prediction of epoxy flow during the underfill process in flip chip packaging","authors":"M. Majid, C. Khor, M. K. Abdullah, M. Z. Abdullah, W. Rahiman, A. Jappar, M. Aris","doi":"10.1109/IEMT.2012.6521810","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521810","url":null,"abstract":"In the present paper, a 3D numerical prediction has been made to study the flip chip underfill process using the epoxy molding compound (EMC). The prediction considered the EMC filling behavior for the flow induced between the tiny gap of silicon die and substrate. Three different arrangements of the solder bump have been tested in this work. The EMC is treated as a generalized Newtonian fluid (GNF). The developed methodology combines the Kawamura and Kawahara technique, and the melt front volume tracking method to solve the two-phase flow field around the solder bumps. The Castro-Macosko rheology model with Arrhenius temperature dependence is adopted in the viscosity model. The predictions are made to investigate the filling patterns at several time intervals. The results show that the underfill process for solder bump with Type A gives minimum filling time and better filling yield. The effect of gap height between the plate and substrate on the underfill process also has been considered. The close agreement between prediction and experimental results from the previous work illustrates the applicability of the present numerical model.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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