Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521808
S. Gholizadehsangesaraki, S. Begum, M. Nainar, Z. Kothandapani
Development of high performance titanium dioxide (TiO2) based varistor materials demands binders to improve its physical properties which will ultimately enhance its electrical performances. The material used for ceramic based varistor should exhibit good mechanical properties. As for desired mechanical properties, porosity should be minimal, high fired density, high sintered strength and small average grain size are desired. In this paper effect of PVA (binder) on TiO2 was investigated and its influence on physical, mechanical and microstructure was observed. The binder was added during ball milling and then followed by the shaping and sintering process. The samples were characterized by evaluating fired density, hardness, compressive strength and microstructure. Our studies revealed that varistor disc with higher density, hardness and strength can be produced with the use of binder.
{"title":"Affect of binder on mechanical and physical characterization of titanium dioxide based varistor","authors":"S. Gholizadehsangesaraki, S. Begum, M. Nainar, Z. Kothandapani","doi":"10.1109/IEMT.2012.6521808","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521808","url":null,"abstract":"Development of high performance titanium dioxide (TiO2) based varistor materials demands binders to improve its physical properties which will ultimately enhance its electrical performances. The material used for ceramic based varistor should exhibit good mechanical properties. As for desired mechanical properties, porosity should be minimal, high fired density, high sintered strength and small average grain size are desired. In this paper effect of PVA (binder) on TiO2 was investigated and its influence on physical, mechanical and microstructure was observed. The binder was added during ball milling and then followed by the shaping and sintering process. The samples were characterized by evaluating fired density, hardness, compressive strength and microstructure. Our studies revealed that varistor disc with higher density, hardness and strength can be produced with the use of binder.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129376069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521812
Z. Abdullah, L. Vigneswaran, A. Ang, G. Yuan
In the fast- paced semiconductor industry the need for package solution arises in order to cope with emerging miniaturization trend. As wafer thickness decreases to 100 μm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping not only during grinding but also at subsequent processing steps.Thinner dies will be able to perform faster heat dissipation to the Cu leadframe to improve the Rth and at the same time will be able to improve the Rdson performance. An effort to assemble an Ultra Thin Dies has been made at die bonding using soft solder, solder paste and also Au Sn Diffusion Soldering. This paper discusses the process optimization and challenges being done at die bond process by using multi needles and peel and ramp concept in order to pick and place such a thin dies in the range of chip thickness less than 60 um . Challenges such as die warpage has been minimized by optimizing the impact of vacuum suction during pick and place on the ultra thin wafer since thin die is very flexible and will be very much influence by the vacuum suction force. The other key parameter is the design of the collect vacuum holes which induced the suction force across the chip surface and will influence its stability during pick and place. The two concepts of pick and place using multi needles and peel and ramp have its own advantages and disadvantages. The experiments conducted revealed the capability of the multi needles and peel and ramp and for stable production both concept works in certain chip sizes with its own process limitation. A feasibility study on ultra thin wafer thickness during pick up and assembly process shows the concept used at die bonding can reduces the stress impact exerted on the chip during pick and place with a proper design of die bonding collet, reduction of die warpage and effect of vacuum suction during pick up process. However in order to achieve a stable production a lot of efforts still need to be done and it involves process optimization , die bonding equipment control and front end wafer technology side.
{"title":"Die attach capability on ultra thin wafer thickness for power semiconductor","authors":"Z. Abdullah, L. Vigneswaran, A. Ang, G. Yuan","doi":"10.1109/IEMT.2012.6521812","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521812","url":null,"abstract":"In the fast- paced semiconductor industry the need for package solution arises in order to cope with emerging miniaturization trend. As wafer thickness decreases to 100 μm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping not only during grinding but also at subsequent processing steps.Thinner dies will be able to perform faster heat dissipation to the Cu leadframe to improve the Rth and at the same time will be able to improve the Rdson performance. An effort to assemble an Ultra Thin Dies has been made at die bonding using soft solder, solder paste and also Au Sn Diffusion Soldering. This paper discusses the process optimization and challenges being done at die bond process by using multi needles and peel and ramp concept in order to pick and place such a thin dies in the range of chip thickness less than 60 um . Challenges such as die warpage has been minimized by optimizing the impact of vacuum suction during pick and place on the ultra thin wafer since thin die is very flexible and will be very much influence by the vacuum suction force. The other key parameter is the design of the collect vacuum holes which induced the suction force across the chip surface and will influence its stability during pick and place. The two concepts of pick and place using multi needles and peel and ramp have its own advantages and disadvantages. The experiments conducted revealed the capability of the multi needles and peel and ramp and for stable production both concept works in certain chip sizes with its own process limitation. A feasibility study on ultra thin wafer thickness during pick up and assembly process shows the concept used at die bonding can reduces the stress impact exerted on the chip during pick and place with a proper design of die bonding collet, reduction of die warpage and effect of vacuum suction during pick up process. However in order to achieve a stable production a lot of efforts still need to be done and it involves process optimization , die bonding equipment control and front end wafer technology side.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123774500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521823
Z. Conroy, J. Balangue, P. B. Geiger, S. Butkovich
Product cost and revenue trends are not consistent with the cost of Test, Inspection and Measurement (TIM) technologies. Specifically, while Moore's Law has applied to the silicon in the product, it does not apply to the overall cost of test of the resulting higher-functionality, desirably lower-cost product. Higher performance and lower cost test equipment, while also desirable, are not enough to solve the gap between the cost of increasing requirements for test/inspection coverage and price that customers are willing to pay for the product. Product design solutions (testability features) that facilitate lower cost test solutions while keeping adequate test coverage, must be explored. Test methodology and strategy need to be reconsidered. Increasing product complexity and reduced test point access are driving a desire to increase use of technologies such as Boundary-Scan and BIST (Built-In-Self-Test) to improve test coverage. The International Electronics Manufacturing Initiative (iNEMI) has two ongoing projects investigating the gaps and ultimately driving for industry changes in the deployment of those technologies. This paper presents the results from those two projects. The first portion of the paper introduces the outputs from the iNEMI Boundary-scan project team, which reviewed current available test methods and strategy for testing the external memory devices and analyzed the gaps and opportunities. The second portion of the paper discusses the opportunity of BIST technology for board level testing and the needs for standardization. The two projects clarify the requirements needed for the existing boundary-scan IEEE1149.1 standard and other industry standards to bridge the gap for lack of test point access and improved testability of products.
{"title":"Current and future manufacturing test solution strategies - iNEMI Boundary-scan and Built in Self Test (BIST) technology integration for future standardization","authors":"Z. Conroy, J. Balangue, P. B. Geiger, S. Butkovich","doi":"10.1109/IEMT.2012.6521823","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521823","url":null,"abstract":"Product cost and revenue trends are not consistent with the cost of Test, Inspection and Measurement (TIM) technologies. Specifically, while Moore's Law has applied to the silicon in the product, it does not apply to the overall cost of test of the resulting higher-functionality, desirably lower-cost product. Higher performance and lower cost test equipment, while also desirable, are not enough to solve the gap between the cost of increasing requirements for test/inspection coverage and price that customers are willing to pay for the product. Product design solutions (testability features) that facilitate lower cost test solutions while keeping adequate test coverage, must be explored. Test methodology and strategy need to be reconsidered. Increasing product complexity and reduced test point access are driving a desire to increase use of technologies such as Boundary-Scan and BIST (Built-In-Self-Test) to improve test coverage. The International Electronics Manufacturing Initiative (iNEMI) has two ongoing projects investigating the gaps and ultimately driving for industry changes in the deployment of those technologies. This paper presents the results from those two projects. The first portion of the paper introduces the outputs from the iNEMI Boundary-scan project team, which reviewed current available test methods and strategy for testing the external memory devices and analyzed the gaps and opportunities. The second portion of the paper discusses the opportunity of BIST technology for board level testing and the needs for standardization. The two projects clarify the requirements needed for the existing boundary-scan IEEE1149.1 standard and other industry standards to bridge the gap for lack of test point access and improved testability of products.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121945330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521832
Lee Pik San, Ong Kang Eu, I. Azid
Embedded structure of chip has created issues of thermo-mechanical reliability which is a great concern in electronic industries nowadays. Embedded structure that consists of components with different Coefficient of Thermal expansion (CTE) may lead to failure because of the heat dissipations performance and CTE mismatch. Therefore, in this paper, finite element analysis is carried out using ABAQUS to investigate the effect of chip thickness and substrate on failure under one cycle of thermal cycling load. Modified Coffin-Manson relation is used to predict fatigue life of copper trace which has the highest Von Mises stress in the model. Thermo-mechanical reliability is determined by comparing fatigue life of the models. Reliability of embedded chip is higher if the fatigue life is longer. It was found that greater thickness of silicon chip will lead to lower fatigue life and less reliable. Besides, higher difference of CTE between substrate materials and copper trace has lower fatigue life. However, thermal conductivity of the substrate material has to be taken into consideration because it can improve heat dissipations performance and this improves reliability of embedded chip.
{"title":"Thermal analysis of embedded chip","authors":"Lee Pik San, Ong Kang Eu, I. Azid","doi":"10.1109/IEMT.2012.6521832","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521832","url":null,"abstract":"Embedded structure of chip has created issues of thermo-mechanical reliability which is a great concern in electronic industries nowadays. Embedded structure that consists of components with different Coefficient of Thermal expansion (CTE) may lead to failure because of the heat dissipations performance and CTE mismatch. Therefore, in this paper, finite element analysis is carried out using ABAQUS to investigate the effect of chip thickness and substrate on failure under one cycle of thermal cycling load. Modified Coffin-Manson relation is used to predict fatigue life of copper trace which has the highest Von Mises stress in the model. Thermo-mechanical reliability is determined by comparing fatigue life of the models. Reliability of embedded chip is higher if the fatigue life is longer. It was found that greater thickness of silicon chip will lead to lower fatigue life and less reliable. Besides, higher difference of CTE between substrate materials and copper trace has lower fatigue life. However, thermal conductivity of the substrate material has to be taken into consideration because it can improve heat dissipations performance and this improves reliability of embedded chip.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127534942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521806
HongWen Zhang, N. Lee
In the current work, a mixed powder BiAgX solder paste system with the melting temperature above 260°C and comparable, or better, reliability to the high lead-containing solders has been studied. The mixed powder solder paste system is composed of a high-melting first alloy solder powder as a majority and the additive solder powder as a minority. The additive solder is designed to react preferentially with various surface finish materials before, or together with, the melting of the majority solder to form a controllable IMC layer. The IMC layer of the mixed powder system is controllable by the species and quantity of the additive solder, and it is observed to be insensitive to thermal aging and thermal cycling in current tests, while the high lead-containing solders show a considerable increase in IMC layer thickness. Both micron-sized Ag-rich particles and AgSn phases along the Bi colony boundaries in the joints have been observed. The exposed Ag-rich particles and the surrounding stepwise pattern in the Bi matrix on the fracture surface indicate that these Ag-rich particles constrain the dislocation movement in Bi matrix, and thus enhance the strength and the ductility of the joint.
{"title":"High reliability high melting mixed lead-free BiAgX solder paste system","authors":"HongWen Zhang, N. Lee","doi":"10.1109/IEMT.2012.6521806","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521806","url":null,"abstract":"In the current work, a mixed powder BiAgX solder paste system with the melting temperature above 260°C and comparable, or better, reliability to the high lead-containing solders has been studied. The mixed powder solder paste system is composed of a high-melting first alloy solder powder as a majority and the additive solder powder as a minority. The additive solder is designed to react preferentially with various surface finish materials before, or together with, the melting of the majority solder to form a controllable IMC layer. The IMC layer of the mixed powder system is controllable by the species and quantity of the additive solder, and it is observed to be insensitive to thermal aging and thermal cycling in current tests, while the high lead-containing solders show a considerable increase in IMC layer thickness. Both micron-sized Ag-rich particles and AgSn phases along the Bi colony boundaries in the joints have been observed. The exposed Ag-rich particles and the surrounding stepwise pattern in the Bi matrix on the fracture surface indicate that these Ag-rich particles constrain the dislocation movement in Bi matrix, and thus enhance the strength and the ductility of the joint.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521822
B. Pfahl, H. Fu, C. Richardson
iNEMI (International Electronics Manufacturing Initiative) has been creating and exploiting technology roadmaps for the electronics industry for 20 years. It has become recognized as an important tool for defining the “state of the art” in the electronics industry as well as identifying emerging and disruptive technologies. It also includes keys to developing future iNEMI projects and setting industry R&D priorities over the next 10 years. The roadmap is updated every two years with global participation from the industry. The 2013 version of iNEMI roadmap will be released to the public in March 2013. This paper provides a preview of the electronics industry paradigm shifts and the key technology developments and issues. It focuses on the Organic Packaging and Organic PCB Roadmaps, and on the Gap Analysis Process and Resulting iNEMI Actions.
{"title":"Highlights of iNEMI 2013 technology roadmaps","authors":"B. Pfahl, H. Fu, C. Richardson","doi":"10.1109/IEMT.2012.6521822","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521822","url":null,"abstract":"iNEMI (International Electronics Manufacturing Initiative) has been creating and exploiting technology roadmaps for the electronics industry for 20 years. It has become recognized as an important tool for defining the “state of the art” in the electronics industry as well as identifying emerging and disruptive technologies. It also includes keys to developing future iNEMI projects and setting industry R&D priorities over the next 10 years. The roadmap is updated every two years with global participation from the industry. The 2013 version of iNEMI roadmap will be released to the public in March 2013. This paper provides a preview of the electronics industry paradigm shifts and the key technology developments and issues. It focuses on the Organic Packaging and Organic PCB Roadmaps, and on the Gap Analysis Process and Resulting iNEMI Actions.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521745
C. Tai, H. Y. Lim, C. H. Teo, P. J. A. Swee
The increase of gold price had pushed industrial to develop copper wire in order to stay competitive. However, copper is not precious material like gold, there are numerous challenges in bonding & reliability risk associated with stringent automotive reliability requirements. Corrosion associated with copper wire bonding is considered one of the hard to solve reliability risk as the occurrence is in very low ppm and there was no specific pattern observed on the corroded bondpad location. This paper is focusing on the copper wire interconnect with Aluminum pad corrosion in humidity test including autoclave and temperature humidity bias test.
{"title":"An investigation on Cu wire bond corrosion and mitigation technique for automotive reliability","authors":"C. Tai, H. Y. Lim, C. H. Teo, P. J. A. Swee","doi":"10.1109/IEMT.2012.6521745","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521745","url":null,"abstract":"The increase of gold price had pushed industrial to develop copper wire in order to stay competitive. However, copper is not precious material like gold, there are numerous challenges in bonding & reliability risk associated with stringent automotive reliability requirements. Corrosion associated with copper wire bonding is considered one of the hard to solve reliability risk as the occurrence is in very low ppm and there was no specific pattern observed on the corroded bondpad location. This paper is focusing on the copper wire interconnect with Aluminum pad corrosion in humidity test including autoclave and temperature humidity bias test.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126770234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521809
Z. Kothandapani, Shahida Begum, M. Nainar, S. Gholizadeh, Wong Menn Yee
TiO2 varistor material acts as surge arrestors against transient voltages in electrical and electronic equipments. However, the enhancement of properties as a surge protector is very much dependent on the types of dopants being used. Not only that, the microstructure and enhanced mechanical characteristics is anticipated to improve the surge characteristics. In this investigation, the effect of Cobalt Oxide (Co3O4) on Titanium Dioxide (TiO2) was investigated. The percent of dopant was varied at various levels and the prepared samples were characterized by evaluating the physical properties like green density, fired density, sintered strength, axial and radial shrinkage, average grain size and microstructure. A comparison between doped and undoped TiO2 was also made. The physical, mechanical and microstructure were improved for doped TiO2 samples and it was highest for the samples prepared from powder with 98.5% TiO2.1.5% Co3O4 and sintered at 1350°C.
{"title":"Physical characterization of Titanium Dioxide based varistor materials doped with Cobalt Oxide","authors":"Z. Kothandapani, Shahida Begum, M. Nainar, S. Gholizadeh, Wong Menn Yee","doi":"10.1109/IEMT.2012.6521809","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521809","url":null,"abstract":"TiO2 varistor material acts as surge arrestors against transient voltages in electrical and electronic equipments. However, the enhancement of properties as a surge protector is very much dependent on the types of dopants being used. Not only that, the microstructure and enhanced mechanical characteristics is anticipated to improve the surge characteristics. In this investigation, the effect of Cobalt Oxide (Co3O4) on Titanium Dioxide (TiO2) was investigated. The percent of dopant was varied at various levels and the prepared samples were characterized by evaluating the physical properties like green density, fired density, sintered strength, axial and radial shrinkage, average grain size and microstructure. A comparison between doped and undoped TiO2 was also made. The physical, mechanical and microstructure were improved for doped TiO2 samples and it was highest for the samples prepared from powder with 98.5% TiO2.1.5% Co3O4 and sintered at 1350°C.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521814
Yan-Shan Ng, E. S. Cabatbat, L. Guirit
In packaging MEMS pressure sensor applications such as tire pressure sensors, silicone gels are widely used due to its unique characteristics in meeting specific automotive requirements. The device requires low stress die adhesive to protect the sensor dies from any mechanical stress during field application. Since the sensing device is directly mounted into the wheel's rim, another critical requirement is to withstand the centrifugal force while the tire is rotating at high speed as well as be able to withstand any harsh chemicals which the tire may be exposed to. The device must also withstand the harsh changes in environmental temperature which can go over 100degC in summer and far below zero in winter. The silicone gels selected to suit these requirements were found to have various assembly packaging as well as reliability challenges. This paper discusses the material and process challenges associated with the application of these gels. Comprehensive studies and process characterization were conducted to address these challenges.
{"title":"Material & process challenges for tire pressure monitoring sensor (TPMS) packaging","authors":"Yan-Shan Ng, E. S. Cabatbat, L. Guirit","doi":"10.1109/IEMT.2012.6521814","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521814","url":null,"abstract":"In packaging MEMS pressure sensor applications such as tire pressure sensors, silicone gels are widely used due to its unique characteristics in meeting specific automotive requirements. The device requires low stress die adhesive to protect the sensor dies from any mechanical stress during field application. Since the sensing device is directly mounted into the wheel's rim, another critical requirement is to withstand the centrifugal force while the tire is rotating at high speed as well as be able to withstand any harsh chemicals which the tire may be exposed to. The device must also withstand the harsh changes in environmental temperature which can go over 100degC in summer and far below zero in winter. The silicone gels selected to suit these requirements were found to have various assembly packaging as well as reliability challenges. This paper discusses the material and process challenges associated with the application of these gels. Comprehensive studies and process characterization were conducted to address these challenges.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130067715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521791
L. Sim, Yong Wae Chet
The development of new TO package towards package miniaturization trend for improving cost performance while enhancing product performance to low ohmic resistance and high current capability had brought challenges into the design for manufacturability and reliability. An innovation of TO package, TO Leadless (TOLL), enables Infineon to maintain technology leadership in Power Semiconductors and competitiveness of business in offering latest product technologies and solutions for Automotive application. The design of TOLL increased the power density and it has large die pad area for power chip size maximization and low profile lead structure for short wire bond looping are greatly contributing to low ohmic resistance and high current capability. The Automotive MOSFET product characterization showed TOLL performed ohmic resistance (Ron) lower and current rating higher than D2PAK. The lead post design of TOLL for power and logic interconnects provides compatibility for broad range of power semiconductors family such as MOSFET, high current PROFET, Power PROFET, Connect FET, NovalithIC, Complimentary MOS, SiC JFET and others. The unique design of TOLL also enables economies of scale in manufacturing and avoids additional cost for conversion at mold tool and test contactor in handling difference products. Throughout development of TOLL, an invention “intrusion mold edge” design was patented and implemented in TOLL for production handling enhancement. As TOLL design is optimized to a low profile leadframe and molded body package for power enhancement, die attach interconnects reliability performance had become a great challenge. The optimization of die attach process did not demonstrate improvement of solder fatigue stress after temperature cycling of reliability test. The die attach solder fatigue due to thermal-mechanical stress, package and chip mechanical designs were characterized to determine the most effective approach to enhance the reliability performance. The innovation is to introduce appropriate chip thickness to minimize the thermal-mechanical stress. As a result, TOLL achieved a high performance and reliable package while maintaining the cost effectiveness.
新型TO封装朝着封装小型化的方向发展，以提高成本效益，同时将产品性能提高到低欧姆电阻和大电流能力，这对设计的可制造性和可靠性提出了挑战。创新的TO封装，TO无铅封装(TOLL)，使英飞凌能够在功率半导体领域保持技术领先地位，并在为汽车应用提供最新产品技术和解决方案方面保持业务竞争力。TOLL的设计提高了功率密度，并具有较大的晶片面积以实现功率芯片尺寸最大化，以及低轮廓引线结构以实现短线键合环路，从而大大提高了低欧姆电阻和高电流能力。汽车MOSFET产品表征表明，TOLL具有比D2PAK更低的欧姆电阻(Ron)和更高的电流额定值。用于电源和逻辑互连的前端设计为广泛的功率半导体家族提供兼容性，例如MOSFET，高电流PROFET, power PROFET, Connect FET, NovalithIC, Complimentary MOS, SiC JFET等。TOLL的独特设计还实现了制造中的规模经济，并避免了在处理不同产品时在模具和测试接触器上进行转换的额外成本。在TOLL的发展过程中，一项发明“入侵模具边缘”设计获得了专利，并在TOLL中实施，以增强生产处理能力。由于为了提高功率，TOLL的设计被优化为采用低轮廓引线框架和模制车身封装，因此对模接互连的可靠性性能提出了很大的挑战。在可靠性试验温度循环后，焊料的疲劳应力并没有得到改善。对热机械应力引起的焊点疲劳、封装和芯片的机械设计进行了分析，以确定提高可靠性性能的最有效方法。创新之处在于引入合适的切屑厚度以最小化热机械应力。因此，TOLL在保持成本效益的同时实现了高性能和可靠的封装。
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