Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509788
G. Cretu, F. Magrini, Friedrich zur Nieden, K. Esmark, S. Decker
A GGNMOS device is presented as a vehicle to compare different methods of analyzing the device behavior under fast transient events (CDM, CCTLP, vf-TLP, TCAD mixed mode simulations). The slope developed as a key parameter for the failure mode. The necessity along with the advantages and disadvantages of these methods are discussed.
{"title":"Analysis of forward recovery in GGNMOS devices under fast transients","authors":"G. Cretu, F. Magrini, Friedrich zur Nieden, K. Esmark, S. Decker","doi":"10.23919/EOS/ESD.2018.8509788","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509788","url":null,"abstract":"A GGNMOS device is presented as a vehicle to compare different methods of analyzing the device behavior under fast transient events (CDM, CCTLP, vf-TLP, TCAD mixed mode simulations). The slope developed as a key parameter for the failure mode. The necessity along with the advantages and disadvantages of these methods are discussed.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509739
Collin Reiman, N. Jack, E. Rosenbaum
A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for key latch-up metrics, such as holding and trigger voltage, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices.
{"title":"Latch-up Model of Non-collinear PNPN Structures","authors":"Collin Reiman, N. Jack, E. Rosenbaum","doi":"10.23919/EOS/ESD.2018.8509739","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509739","url":null,"abstract":"A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for key latch-up metrics, such as holding and trigger voltage, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123009374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509750
T. Smedes, Greg O’Sullivan, R. Derikx, Artemio García, Bob Knoppers
We show that CDM testing of non-connected pins can result in over-stress or under-stress on the subsequently connected pin tested, and thus can lead to incorrect qualification. Mitigation options are discussed. We show that in particular cases CDM stressing non-connected pins may identify unique fail modes.
{"title":"Undesired Effects of CDM Stressing Non-Connected Pins","authors":"T. Smedes, Greg O’Sullivan, R. Derikx, Artemio García, Bob Knoppers","doi":"10.23919/EOS/ESD.2018.8509750","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509750","url":null,"abstract":"We show that CDM testing of non-connected pins can result in over-stress or under-stress on the subsequently connected pin tested, and thus can lead to incorrect qualification. Mitigation options are discussed. We show that in particular cases CDM stressing non-connected pins may identify unique fail modes.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eos/esd.2018.8509769
{"title":"The David F. Barber Sr. Memorial Award: Theo Smedes","authors":"","doi":"10.23919/eos/esd.2018.8509769","DOIUrl":"https://doi.org/10.23919/eos/esd.2018.8509769","url":null,"abstract":"","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509765
Pengyu Wei, Giorgi Maghlakelidze, Jianchi Zhou, H. Gossner, D. Pommerenke
A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.
{"title":"An Application of System Level Efficient ESD Design for HighSpeed USB3.x Interface","authors":"Pengyu Wei, Giorgi Maghlakelidze, Jianchi Zhou, H. Gossner, D. Pommerenke","doi":"10.23919/EOS/ESD.2018.8509765","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509765","url":null,"abstract":"A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509781
G. Notermans, Hans-Martin Ritter, S. Holland, D. Pogany
The dynamic voltage overshoot of an ESD protection during triggering is determined by conductivity modulation in the silicon and inductive overshoot in the metal traces. The paper describes how to separate the two contributions and how to model these phenomena. It shows how to use this result to boost system protection for a typical USB3 interface beyond 15kV.
{"title":"Modeling dynamic overshoot in ESD protections","authors":"G. Notermans, Hans-Martin Ritter, S. Holland, D. Pogany","doi":"10.23919/EOS/ESD.2018.8509781","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509781","url":null,"abstract":"The dynamic voltage overshoot of an ESD protection during triggering is determined by conductivity modulation in the silicon and inductive overshoot in the metal traces. The paper describes how to separate the two contributions and how to model these phenomena. It shows how to use this result to boost system protection for a typical USB3 interface beyond 15kV.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128493589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509741
D. Marreiro, V. Vashchenko
The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities.
{"title":"Substrate Isolation Options Effect on HV Latch-up","authors":"D. Marreiro, V. Vashchenko","doi":"10.23919/EOS/ESD.2018.8509741","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509741","url":null,"abstract":"The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509756
Michael Ammer, A. Rupp, Yiqun Cao, C. Russ, Martin Sauter, L. Maurer
On-chip ESD protection in smart power technologies is often done with MOSFETs, either self-protecting or as dedicated ESD-protection. Turned on by intrinsic gate-drain capacitive coupling they conduct dynamically channel current as well as additional avalanche current depending on MOSFET type. A generic approach to model this transient behavior for system ESD and disturbance pulse simulation is presented.
{"title":"Modeling the Transient Behavior of MOS-Transistors during ESD and Disturbance Pulses in a System with a Generic Black Box Approach","authors":"Michael Ammer, A. Rupp, Yiqun Cao, C. Russ, Martin Sauter, L. Maurer","doi":"10.23919/EOS/ESD.2018.8509756","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509756","url":null,"abstract":"On-chip ESD protection in smart power technologies is often done with MOSFETs, either self-protecting or as dedicated ESD-protection. Turned on by intrinsic gate-drain capacitive coupling they conduct dynamically channel current as well as additional avalanche current depending on MOSFET type. A generic approach to model this transient behavior for system ESD and disturbance pulse simulation is presented.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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