Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509746
C. Russ, Michael Ammer, K. Esmark
The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns.
{"title":"Predicting System Level ESD Robustness Using a Comprehensive Modelling Approach","authors":"C. Russ, Michael Ammer, K. Esmark","doi":"10.23919/EOS/ESD.2018.8509746","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509746","url":null,"abstract":"The system level ESD robustness of ICs is simulated including all external components. An electro-thermal model is calibrated to power profiles of IC failures. Results provide great confidence for prediction of the joint effectiveness of board- or chip-level protection in reaction to changing system requirements or to different ESD guns.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123182068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509771
D. Alvarez, W. Hartung, R. Bhandari
ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.
{"title":"ESD and Latch-up failures through triple-well in a 65nm CMOS technology","authors":"D. Alvarez, W. Hartung, R. Bhandari","doi":"10.23919/EOS/ESD.2018.8509771","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509771","url":null,"abstract":"ESD and latch-up failures in a 65nm CMOS technology are presented where the triggering of a parasitic thyristor occurs despite the triple-well isolation that prevents the formation of a classical 4-layer SCR structure. The influence on triggering of the anode-to-cathode spacing, guard-ring protection and well resistances are studied for this type of parasitic device.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509757
You Li, M. Miao, R. Gauthier
We present an ESD P-direction STI diode fabricated in an advanced bulk FinFET technology. The impact on process and design parameters are evaluated in detail. With design optimization, the ESD P-direction STI diode achieves 46% and 16% performance improvement for It2/C and It2/Area relative to the C-direction design.
{"title":"Design and Optimization of ESD P-Direction Diode in Bulk FinFET Technology","authors":"You Li, M. Miao, R. Gauthier","doi":"10.23919/EOS/ESD.2018.8509757","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509757","url":null,"abstract":"We present an ESD P-direction STI diode fabricated in an advanced bulk FinFET technology. The impact on process and design parameters are evaluated in detail. With design optimization, the ESD P-direction STI diode achieves 46% and 16% performance improvement for It2/C and It2/Area relative to the C-direction design.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127622894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509745
B. Shankar, Rahul Singh, R. Sengupta, H. Khand, Ankit Soni, Sayak Dutta Gupta, S. Raghavan, H. Gossner, M. Shrivastava
Electro-thermal behaviour and degradation of recessed GaN Schottky diode are studied under forward and reverse ESD stress. Impact of different surface treatments at Schottky interface, on trap generation and degradation is investigated. Evolution of mechanical stress and defects is probed using onthe-fly Raman spectroscopy. Distinct failure modes are discovered in each case.
{"title":"Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes","authors":"B. Shankar, Rahul Singh, R. Sengupta, H. Khand, Ankit Soni, Sayak Dutta Gupta, S. Raghavan, H. Gossner, M. Shrivastava","doi":"10.23919/EOS/ESD.2018.8509745","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509745","url":null,"abstract":"Electro-thermal behaviour and degradation of recessed GaN Schottky diode are studied under forward and reverse ESD stress. Impact of different surface treatments at Schottky interface, on trap generation and degradation is investigated. Evolution of mechanical stress and defects is probed using onthe-fly Raman spectroscopy. Distinct failure modes are discovered in each case.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132123246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509764
D. Abessolo-Bidzo, R. Derikx, Paul Cappon, S. Zhao
The use of EDA ESD checking tools has grown considerably in the past few years in the semiconductor industry. This paper gives an overview of four different HBM and CDM layout simulation tools. For the first time, a full CDM analysis combining predictive CDM SPICE and Layout simulations are presented.
{"title":"A Study of HBM and CDM Layout Simulations Tools","authors":"D. Abessolo-Bidzo, R. Derikx, Paul Cappon, S. Zhao","doi":"10.23919/EOS/ESD.2018.8509764","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509764","url":null,"abstract":"The use of EDA ESD checking tools has grown considerably in the past few years in the semiconductor industry. This paper gives an overview of four different HBM and CDM layout simulation tools. For the first time, a full CDM analysis combining predictive CDM SPICE and Layout simulations are presented.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509761
Johannes Weber, R. Fung, R. Wong, H. Wolf, A. Horst Gieser, L. Maurer
Challenging the limits of today’s metrology and test setups for CDM and Capacitively Coupled Transmission Line Pulsing (CC-TLP), the study identifies critical stress parameters for A25 Gbps communication device in the CDM-domain. Only CC-TLP stress in combination with a 33/ 63 GHz single shot oscilloscope was able to relate significant differences of failure current distributions to the rise time spread in the order of few tens of picoseconds and to obtain a conclusive sharp pass/fail transition at a certain peak current level.
{"title":"Comparison of CDM and CC-TLP robustness for an ultra-high speed interface IC","authors":"Johannes Weber, R. Fung, R. Wong, H. Wolf, A. Horst Gieser, L. Maurer","doi":"10.23919/EOS/ESD.2018.8509761","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509761","url":null,"abstract":"Challenging the limits of today’s metrology and test setups for CDM and Capacitively Coupled Transmission Line Pulsing (CC-TLP), the study identifies critical stress parameters for A25 Gbps communication device in the CDM-domain. Only CC-TLP stress in combination with a 33/ 63 GHz single shot oscilloscope was able to relate significant differences of failure current distributions to the rise time spread in the order of few tens of picoseconds and to obtain a conclusive sharp pass/fail transition at a certain peak current level.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509766
V. Vashchenko, D. Marreiro, S. Malobabic, H. Sarbishaei, A. Shibkov
A strong miscorrelation between TLP maximum current to failure and corresponding estimated onwafer-HMM pulse passing level of dual-direction SCR ESD device was studied. For multiple SCR ESD devices in 5-80V voltage range the effect was represented by low HMM passing level due to burnout of the structure Npocket to P-substrate isolation junction. It is shown that the phenomenon is specific to the on-wafer HMM test setup itself and is the result of the direct strong coupling of the wafer to the prober chuck at system ground under inductive impedance of the HMM tool connection to the DUT.
{"title":"The HMM-TLP Miscorrelation at Wafer Level Tests","authors":"V. Vashchenko, D. Marreiro, S. Malobabic, H. Sarbishaei, A. Shibkov","doi":"10.23919/EOS/ESD.2018.8509766","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509766","url":null,"abstract":"A strong miscorrelation between TLP maximum current to failure and corresponding estimated onwafer-HMM pulse passing level of dual-direction SCR ESD device was studied. For multiple SCR ESD devices in 5-80V voltage range the effect was represented by low HMM passing level due to burnout of the structure Npocket to P-substrate isolation junction. It is shown that the phenomenon is specific to the on-wafer HMM test setup itself and is the result of the direct strong coupling of the wafer to the prober chuck at system ground under inductive impedance of the HMM tool connection to the DUT.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116566620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509773
G. Langguth, F. Nieden, C. Kupfer, O. Rösch, Benno Mühlbacher, E. Bach
A system level simulation approach is presented for MEMS sensor modules. Module protection and tester parasitics are modelled as ideal RLC network. On-chip ESD protection simulation is based on compact models. Simulation results can quantitatively explain qualification fails and validate the approach, enabling a subsequent optimization of the overall ESD protection.
{"title":"ESD System Level Simulation of MEMS Sensor Modules","authors":"G. Langguth, F. Nieden, C. Kupfer, O. Rösch, Benno Mühlbacher, E. Bach","doi":"10.23919/EOS/ESD.2018.8509773","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509773","url":null,"abstract":"A system level simulation approach is presented for MEMS sensor modules. Module protection and tester parasitics are modelled as ideal RLC network. On-chip ESD protection simulation is based on compact models. Simulation results can quantitatively explain qualification fails and validate the approach, enabling a subsequent optimization of the overall ESD protection.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128423571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509692
Stefan Seidl, F. Nieden, R. Gaertner
Ionizers are often used to limit the charging of insulators in an EPA. Unfortunately, a simple table top characterization with a charged plate monitor is not sufficient to guarantee safe performance when mounted inside a production machine. In this contribution we present a novel alternative by directly measuring the discharge current of an ionizer.
{"title":"Study of the Discharge Current created by an Ionizer","authors":"Stefan Seidl, F. Nieden, R. Gaertner","doi":"10.23919/EOS/ESD.2018.8509692","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509692","url":null,"abstract":"Ionizers are often used to limit the charging of insulators in an EPA. Unfortunately, a simple table top characterization with a charged plate monitor is not sufficient to guarantee safe performance when mounted inside a production machine. In this contribution we present a novel alternative by directly measuring the discharge current of an ionizer.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128602042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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