Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509687
R. Sithanandam, Chanhee Jeon, Kitae Lee, Woojin Seo, K. Song, Yiseul Kim, Jordan Davis, Dong Yup lee, Sukjin Kim, Hangu Kim
This paper reports an un-expected latchup scenario identified when utilizing the forward body bias (FBB) technique in fully depleted silicon-on-insulator (FDSOI) technology. It was found that a parasitic silicon controlled rectifier (SCR) can be formed between p-well/deep n-well/p-sub/n-well which is different from the conventional SCR observed in bulk CMOS technology (p+/n-well/p-sub/n+). The vertical injection mechanism from p-well emitter to deep n-well base and n-well emitter to p-sub base, larger emitter injection area, and larger overdrive voltage due to latchup qualification methodology imposes significant challenges in the guard ring design. Through well calibrated technology computer aided design (TCAD) simulations, the risk is systematically studied and various prevention methods like guard ring design, deep n-well to n-well distance and series resistor are explored and design guidelines for various supply domains are proposed.
{"title":"Unexpected Latchup Risk Observed in FDSOI Technology – Analysis and Prevention Techniques","authors":"R. Sithanandam, Chanhee Jeon, Kitae Lee, Woojin Seo, K. Song, Yiseul Kim, Jordan Davis, Dong Yup lee, Sukjin Kim, Hangu Kim","doi":"10.23919/EOS/ESD.2018.8509687","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509687","url":null,"abstract":"This paper reports an un-expected latchup scenario identified when utilizing the forward body bias (FBB) technique in fully depleted silicon-on-insulator (FDSOI) technology. It was found that a parasitic silicon controlled rectifier (SCR) can be formed between p-well/deep n-well/p-sub/n-well which is different from the conventional SCR observed in bulk CMOS technology (p+/n-well/p-sub/n+). The vertical injection mechanism from p-well emitter to deep n-well base and n-well emitter to p-sub base, larger emitter injection area, and larger overdrive voltage due to latchup qualification methodology imposes significant challenges in the guard ring design. Through well calibrated technology computer aided design (TCAD) simulations, the risk is systematically studied and various prevention methods like guard ring design, deep n-well to n-well distance and series resistor are explored and design guidelines for various supply domains are proposed.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"105 12S2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509749
E. Grund, Thomas Chang, R. Watkins, C. Burke, Justin Katz, R. Gauthier
Charged Device Model testing is confronted with high operating frequencies driving CDM to lower voltage levels and by high-density packages with ever smaller ball/pin pitches. A new CDM discharge head design meets these challenges by making DUT contact first and then an internal spark discharge occurs in a controlled environment.
{"title":"A New CDM Discharge Head for Increased Repeatability and Testing Small Pitch Packages","authors":"E. Grund, Thomas Chang, R. Watkins, C. Burke, Justin Katz, R. Gauthier","doi":"10.23919/EOS/ESD.2018.8509749","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509749","url":null,"abstract":"Charged Device Model testing is confronted with high operating frequencies driving CDM to lower voltage levels and by high-density packages with ever smaller ball/pin pitches. A new CDM discharge head design meets these challenges by making DUT contact first and then an internal spark discharge occurs in a controlled environment.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124915114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509770
Bernard Chin, L. H. Koh
This paper presents a case study of ESD/EOS events causing low yield in trial lots prior to the release of volume production. The use of line ESD audits to check for static charge, grounding and CDM events, voltage spike check and split-lot testing were used to determine the root cause.
{"title":"EOS/ESD in IC Manufacturing Process of GQFN 64L Devices","authors":"Bernard Chin, L. H. Koh","doi":"10.23919/EOS/ESD.2018.8509770","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509770","url":null,"abstract":"This paper presents a case study of ESD/EOS events causing low yield in trial lots prior to the release of volume production. The use of line ESD audits to check for static charge, grounding and CDM events, voltage spike check and split-lot testing were used to determine the root cause.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131354996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509695
B. Sampath Kumar, Milova Paul, H. Gossner, M. Shrivastava
In this paper, physical insights of Drain extended FinFET under ESD stress condition is explored. Key features like bipolar triggering, conductivity modulation and localized hot spot formation pertaining to DeFinFET failure mechanism are discussed comprehensively. Non-uniformity and filament formation in multi-finger DeFinFET is explored.
{"title":"Physical Insights into the ESD behavior of Drain Extended FinFETs","authors":"B. Sampath Kumar, Milova Paul, H. Gossner, M. Shrivastava","doi":"10.23919/EOS/ESD.2018.8509695","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509695","url":null,"abstract":"In this paper, physical insights of Drain extended FinFET under ESD stress condition is explored. Key features like bipolar triggering, conductivity modulation and localized hot spot formation pertaining to DeFinFET failure mechanism are discussed comprehensively. Non-uniformity and filament formation in multi-finger DeFinFET is explored.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125522796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509760
S. Holland, G. Notermans, Hans-Martin Ritter
The transient voltage overshoot of forward biased pn-junction diodes is measured by VF-TLP and compared with TCAD simulations. Based on the simulation results a physics-based analytical model is developed which takes the effect of impact ionization into account and exhibits an excellent match with the TCAD simulations and measurement data.
{"title":"Modelling transient voltage overshoot of a forward biased pn-junction diode with intrinsic doped region","authors":"S. Holland, G. Notermans, Hans-Martin Ritter","doi":"10.23919/EOS/ESD.2018.8509760","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509760","url":null,"abstract":"The transient voltage overshoot of forward biased pn-junction diodes is measured by VF-TLP and compared with TCAD simulations. Based on the simulation results a physics-based analytical model is developed which takes the effect of impact ionization into account and exhibits an excellent match with the TCAD simulations and measurement data.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134054654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509752
Tianshi Wang, C. McAndrew
This paper introduces a way of modeling the abrupt turn-on/off behavior of ESD protection devices using entirely continuous and smooth equations. It presents accurate and robust ESD snapback models that are convenient and flexible to use for various types of ESD protection devices without convergence issues during simulation.
{"title":"A Generic Formalism to Model ESD Snapback for Robust Circuit Simulation","authors":"Tianshi Wang, C. McAndrew","doi":"10.23919/EOS/ESD.2018.8509752","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509752","url":null,"abstract":"This paper introduces a way of modeling the abrupt turn-on/off behavior of ESD protection devices using entirely continuous and smooth equations. It presents accurate and robust ESD snapback models that are convenient and flexible to use for various types of ESD protection devices without convergence issues during simulation.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133700316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509743
S. Duncan, J. Gibson, T. J. Kinnear
As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful.
{"title":"ANSI/ESD S20.20 – The Next Generation","authors":"S. Duncan, J. Gibson, T. J. Kinnear","doi":"10.23919/EOS/ESD.2018.8509743","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509743","url":null,"abstract":"As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133176095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509693
Giorgi Maghlakelidze, Pengyu Wei, Wei Huang, H. Gossner, D. Pommerenke
A fully automated system is developed for the systematic characterization of soft failure robustness for a DUT. The methodology is founded on software-based detection methods and applied to a USB3 interface. The approach is extendable to other interfaces and measurement-based failure detection methods.
{"title":"Pin Specific ESD Soft Failure Characterization Using a Fully Automated Set-up","authors":"Giorgi Maghlakelidze, Pengyu Wei, Wei Huang, H. Gossner, D. Pommerenke","doi":"10.23919/EOS/ESD.2018.8509693","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509693","url":null,"abstract":"A fully automated system is developed for the systematic characterization of soft failure robustness for a DUT. The methodology is founded on software-based detection methods and applied to a USB3 interface. The approach is extendable to other interfaces and measurement-based failure detection methods.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124940685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EOS/ESD.2018.8509776
Leonardo Di Biccari, A. Boroni, L. Cerati, L. Zullino, L. Merlo, A. Andreini
Maximum current value, strictly related to the IC package, is used for suitable CDM ESD protections sizing at required CDM voltage level, but Recovery Effects on HV ESD protections depend on current rise time, another package-dependent parameter in CDM. The impact of current rise time in CDM test is investigated.
{"title":"CDM stress rise time: impact on Forward Recovery Effect for HV ESD protections","authors":"Leonardo Di Biccari, A. Boroni, L. Cerati, L. Zullino, L. Merlo, A. Andreini","doi":"10.23919/EOS/ESD.2018.8509776","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2018.8509776","url":null,"abstract":"Maximum current value, strictly related to the IC package, is used for suitable CDM ESD protections sizing at required CDM voltage level, but Recovery Effects on HV ESD protections depend on current rise time, another package-dependent parameter in CDM. The impact of current rise time in CDM test is investigated.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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