Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025613
Tung Chih Hang, Cheng Cheng Kou, M.K. Radhakrishnan, N. M. Iyer
A systematic physical failure analysis methodology can be applied to distinguish the damage induced by EOS and ESD in sub-micron silicon devices. Eventhough the electrical failure modes observed are identical, by a thorough analysis knowing the differences in failure signatures, as well as employing specific methods, it is found possible to distinguish between EOS and ESD failures to a great extent. Both field failed and simulated failed cases have been studied to establish the difference in failure signatures.
{"title":"Physical failure analysis to distinguish EOS and ESD failures","authors":"Tung Chih Hang, Cheng Cheng Kou, M.K. Radhakrishnan, N. M. Iyer","doi":"10.1109/IPFA.2002.1025613","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025613","url":null,"abstract":"A systematic physical failure analysis methodology can be applied to distinguish the damage induced by EOS and ESD in sub-micron silicon devices. Eventhough the electrical failure modes observed are identical, by a thorough analysis knowing the differences in failure signatures, as well as employing specific methods, it is found possible to distinguish between EOS and ESD failures to a great extent. Both field failed and simulated failed cases have been studied to establish the difference in failure signatures.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124718560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025652
M. Sengupta, C. Tsao, M. Thompson, T. Lundquist
We perform automated alignment of a device's CAD layout to its through silicon-IR image. Light refraction of the optical system blurs and distorts the shape and size of features, causing both edge-based and intensity-based cross-correlation techniques to fail. Our alignment methodology consists of pre-processing (equalization) of the images, followed by sub-resolution offset computation We apply a modeled point spread function (PSF) of the optical system to the CAD image to increase its resemblance to the optical image (resolution-equalization). Using our alignment algorithm, which combines image equalization, over-sampling, and cross-correlation, we demonstrate through-Silicon placement accuracy of 0.1 /spl mu/ with a 1 /spl mu/ resolution optical system.
{"title":"Through-silicon IR image to CAD database alignment","authors":"M. Sengupta, C. Tsao, M. Thompson, T. Lundquist","doi":"10.1109/IPFA.2002.1025652","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025652","url":null,"abstract":"We perform automated alignment of a device's CAD layout to its through silicon-IR image. Light refraction of the optical system blurs and distorts the shape and size of features, causing both edge-based and intensity-based cross-correlation techniques to fail. Our alignment methodology consists of pre-processing (equalization) of the images, followed by sub-resolution offset computation We apply a modeled point spread function (PSF) of the optical system to the CAD image to increase its resemblance to the optical image (resolution-equalization). Using our alignment algorithm, which combines image equalization, over-sampling, and cross-correlation, we demonstrate through-Silicon placement accuracy of 0.1 /spl mu/ with a 1 /spl mu/ resolution optical system.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114986063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025637
F. Stevie, C. Vartuli
Device fabrication with reduced linewidths makes it possible for smaller defects to affect device performance. The availability of 5-7 nm diameter focused ion beams has made it possible to expose most defects of interest for analysis using EDS or AES. However, device dimensions have become so small that even the site specific capability of the FIB can be challenged. The beam current at 7 nm resolution is not sufficient to perform significant material removal, therefore larger diameter beams are required. Failure analysis techniques are often unable to locate the region of interest better than within a few tenths of a micron. As this region is sputtered using the FIB, frequent checks are made to determine if the feature is visible. Unfortunately, it is quite possible in the case of small features to essentially remove most if not all of the material so that elemental identification is not possible. To resolve this problem, a method was developed to combine the features of the FIB to prepare a specimen for lift-out and the features of a scanning transmission electron microscope (STEM). This allows the gathering of information from a specimen of a thickness that would not be viewable in a conventional TEM, but is resolvable with the STEM due to its unique lens configuration.
{"title":"FIB lift-out STEM failure analysis technique","authors":"F. Stevie, C. Vartuli","doi":"10.1109/IPFA.2002.1025637","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025637","url":null,"abstract":"Device fabrication with reduced linewidths makes it possible for smaller defects to affect device performance. The availability of 5-7 nm diameter focused ion beams has made it possible to expose most defects of interest for analysis using EDS or AES. However, device dimensions have become so small that even the site specific capability of the FIB can be challenged. The beam current at 7 nm resolution is not sufficient to perform significant material removal, therefore larger diameter beams are required. Failure analysis techniques are often unable to locate the region of interest better than within a few tenths of a micron. As this region is sputtered using the FIB, frequent checks are made to determine if the feature is visible. Unfortunately, it is quite possible in the case of small features to essentially remove most if not all of the material so that elemental identification is not possible. To resolve this problem, a method was developed to combine the features of the FIB to prepare a specimen for lift-out and the features of a scanning transmission electron microscope (STEM). This allows the gathering of information from a specimen of a thickness that would not be viewable in a conventional TEM, but is resolvable with the STEM due to its unique lens configuration.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124697769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025654
T. Beauchêne, D. Lewis, F. Beaudoin, P. Perdu, P. Fouillat
Recent advances in the field of laser investigations on ICs report on a new measurement technique with a single contact to the substrate pin of the circuit. This measurement mode called Single Contact Optical Beam Induced Current (SC-OBIC) allows investigating all junctions of the circuit, even if they are not connected to an access pin of the device under test. SC-OBIC also provides relevant information about fault location in these junctions. Pulsed laser allows transient studies. It is suitable with lock-in amplifier which strongly improve the sensitivity of the technique and permit to perform successfully backside analysis. This paper presents new results obtained by backside SC-OBIC investigations and their possible applications to fault location on ICs.
{"title":"Backside SC-OBIC using a pulsed NIR-laser and its application to fault location","authors":"T. Beauchêne, D. Lewis, F. Beaudoin, P. Perdu, P. Fouillat","doi":"10.1109/IPFA.2002.1025654","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025654","url":null,"abstract":"Recent advances in the field of laser investigations on ICs report on a new measurement technique with a single contact to the substrate pin of the circuit. This measurement mode called Single Contact Optical Beam Induced Current (SC-OBIC) allows investigating all junctions of the circuit, even if they are not connected to an access pin of the device under test. SC-OBIC also provides relevant information about fault location in these junctions. Pulsed laser allows transient studies. It is suitable with lock-in amplifier which strongly improve the sensitivity of the technique and permit to perform successfully backside analysis. This paper presents new results obtained by backside SC-OBIC investigations and their possible applications to fault location on ICs.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121674960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025643
T. Sakata, H. Takahashi, T. Sekine
In fabrication of LSI devices, wafer surface cleanness is an important factor related to production yield and reliability of products. A dual beam focused ion beam (FIB) system, which is the FIB integrated with scanning electron microscopy (SEM) function, has become an important tool for yield management. In its typical application, defects are initially observed with SEM and part of them are cut with the FIB to expose their cross sections and then the internal structures are reviewed with SEM and/or scanning ion microscopy (SIM). When the dual beam system is used in a production line, one must pay attention to the contamination due to the primary ion source, namely Ga contamination, and also that due to the sputtered species of device constituent atoms. It is of great concern whether the wafer can be returned back to a production line or not after the analysis. With regard to the Ga contamination, the following two cases should be taken into account: (1) the ion milled wafer, (2) the SEM observed wafer without milling. We have investigated the Ga contamination issue in relation to the dual beam system analysis. In this paper, we have focused more on the spatial resolution.
{"title":"Investigation of Ga contamination due to analysis by dual beam FIB","authors":"T. Sakata, H. Takahashi, T. Sekine","doi":"10.1109/IPFA.2002.1025643","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025643","url":null,"abstract":"In fabrication of LSI devices, wafer surface cleanness is an important factor related to production yield and reliability of products. A dual beam focused ion beam (FIB) system, which is the FIB integrated with scanning electron microscopy (SEM) function, has become an important tool for yield management. In its typical application, defects are initially observed with SEM and part of them are cut with the FIB to expose their cross sections and then the internal structures are reviewed with SEM and/or scanning ion microscopy (SIM). When the dual beam system is used in a production line, one must pay attention to the contamination due to the primary ion source, namely Ga contamination, and also that due to the sputtered species of device constituent atoms. It is of great concern whether the wafer can be returned back to a production line or not after the analysis. With regard to the Ga contamination, the following two cases should be taken into account: (1) the ion milled wafer, (2) the SEM observed wafer without milling. We have investigated the Ga contamination issue in relation to the dual beam system analysis. In this paper, we have focused more on the spatial resolution.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025634
C. Sydlo, B. Mottet, H. Ganis, H. Hartnagel, V. Krozer, S. Delage, S. Cassette, E. Chartier, D. Floriot, S. Bland
GaAs HBT (heterojunction bipolar transistor) technology has reached a certain degree of maturity in the last decade, although reliability problems are not completely solved. In consequence, a material system based on InGaP/GaAs is used, resulting in improved device reliability after the base-emitter interface and the metal contacts have been optimised. The increasing demand for security relevant applications and for the mass market requires not only highly reliable devices and their lifetime data, but also an increased physical understanding of degradation mechanisms and short times for reliability evaluation. In this paper, two approaches are presented for the excitement of the "hydrogen-effect", which has been reported in connection with InGaP HBTs.
{"title":"Defect detection and modelling using pulsed electrical stress for reliability investigations on InGaP HBT","authors":"C. Sydlo, B. Mottet, H. Ganis, H. Hartnagel, V. Krozer, S. Delage, S. Cassette, E. Chartier, D. Floriot, S. Bland","doi":"10.1109/IPFA.2002.1025634","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025634","url":null,"abstract":"GaAs HBT (heterojunction bipolar transistor) technology has reached a certain degree of maturity in the last decade, although reliability problems are not completely solved. In consequence, a material system based on InGaP/GaAs is used, resulting in improved device reliability after the base-emitter interface and the metal contacts have been optimised. The increasing demand for security relevant applications and for the mass market requires not only highly reliable devices and their lifetime data, but also an increased physical understanding of degradation mechanisms and short times for reliability evaluation. In this paper, two approaches are presented for the excitement of the \"hydrogen-effect\", which has been reported in connection with InGaP HBTs.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122751958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025617
M. Ker, Jeng-Jie Peng, H. Jiang
The internal damage issue caused by ESD stress was investigated through a real case of high-voltage driver IC with separated power pins. After the HBM ESD tests applied on silicon chips of the original design, failure analysis was done with the help of OM and SEM to find out the failure spots. The results of failure analysis show that the internal damages on the interface circuit of two circuit blocks are caused due to the absence of the VDD-to-VSS power-rail ESD cell and the ESD cell of connecting different ground lines. By using the proposed effective ESD protection solution, the HBM ESD robustness of the high-voltage driver IC product can be improved to greater than 2.0kV.
{"title":"Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS]","authors":"M. Ker, Jeng-Jie Peng, H. Jiang","doi":"10.1109/IPFA.2002.1025617","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025617","url":null,"abstract":"The internal damage issue caused by ESD stress was investigated through a real case of high-voltage driver IC with separated power pins. After the HBM ESD tests applied on silicon chips of the original design, failure analysis was done with the help of OM and SEM to find out the failure spots. The results of failure analysis show that the internal damages on the interface circuit of two circuit blocks are caused due to the absence of the VDD-to-VSS power-rail ESD cell and the ESD cell of connecting different ground lines. By using the proposed effective ESD protection solution, the HBM ESD robustness of the high-voltage driver IC product can be improved to greater than 2.0kV.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127192158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025626
C. H. Gim
Bitmapping is a common tool used for analysis and device characterisation on volatile and non-volatile memory in integrated circuits. The tester normally provides the electrical failing address and the analyst will use a scramble table to convert the electrical failing address to the physical failing address. A software may be used to descramble the electrical failing addresses and then display the physical location of the failure using simple graphics. In this paper, a novel bitmap technique is presented. Instead of just displaying the X,Y physical location of the failure, which is basically two dimensions, this bitmap technique takes it a step further. The new bitmap technique 'test sensitivity intensity (TSI) bitmap' is a graphical combination of all the listed tools. The idea of using a graphical bitmap was to make it easier to visualise the failure and the pattern of the failure as test conditions change from relaxed conditions to very stringent conditions, compared to a simple data dump memory display.
{"title":"A novel bitmap analysis technique - test sensitivity intensity bitmap","authors":"C. H. Gim","doi":"10.1109/IPFA.2002.1025626","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025626","url":null,"abstract":"Bitmapping is a common tool used for analysis and device characterisation on volatile and non-volatile memory in integrated circuits. The tester normally provides the electrical failing address and the analyst will use a scramble table to convert the electrical failing address to the physical failing address. A software may be used to descramble the electrical failing addresses and then display the physical location of the failure using simple graphics. In this paper, a novel bitmap technique is presented. Instead of just displaying the X,Y physical location of the failure, which is basically two dimensions, this bitmap technique takes it a step further. The new bitmap technique 'test sensitivity intensity (TSI) bitmap' is a graphical combination of all the listed tools. The idea of using a graphical bitmap was to make it easier to visualise the failure and the pattern of the failure as test conditions change from relaxed conditions to very stringent conditions, compared to a simple data dump memory display.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025629
Z. Tokei, F. Lanckmans, G. Van den bosch, M. Van Hove, K. Maex, H. Bender, S. Hens, J. van Landuyt
Copper damascene processing was introduced to reduce circuit speed limiting interconnect RC delays. To prevent copper diffusion into the neighboring dielectric, copper is encapsulated into metallic and dielectric barriers. On the dual damascene level, prior to copper metallization, a pre-clean is applied in order to clean via bottoms. This is necessary to improve yield and decrease via resistance. Conventional preclean employs directional Ar+ bombardment of the wafer surface. This leads to facetting of recess openings and copper sputtering from the underlying metal layer, which is then re-deposited onto recess bottoms. Although several papers detail the impact of pre-clean on via resistance none of them treats in detail the eventual issues related to copper re-deposition underneath the metallic barrier in direct contact with the dielectric. The present paper shows how conventional pre-clean can influence Cu+ drift rate due to copper re-deposition, plasma damage and via resistance.
{"title":"Reliability of copper dual damascene influenced by pre-clean","authors":"Z. Tokei, F. Lanckmans, G. Van den bosch, M. Van Hove, K. Maex, H. Bender, S. Hens, J. van Landuyt","doi":"10.1109/IPFA.2002.1025629","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025629","url":null,"abstract":"Copper damascene processing was introduced to reduce circuit speed limiting interconnect RC delays. To prevent copper diffusion into the neighboring dielectric, copper is encapsulated into metallic and dielectric barriers. On the dual damascene level, prior to copper metallization, a pre-clean is applied in order to clean via bottoms. This is necessary to improve yield and decrease via resistance. Conventional preclean employs directional Ar+ bombardment of the wafer surface. This leads to facetting of recess openings and copper sputtering from the underlying metal layer, which is then re-deposited onto recess bottoms. Although several papers detail the impact of pre-clean on via resistance none of them treats in detail the eventual issues related to copper re-deposition underneath the metallic barrier in direct contact with the dielectric. The present paper shows how conventional pre-clean can influence Cu+ drift rate due to copper re-deposition, plasma damage and via resistance.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114074468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025609
J. Delétage, F. Verdier, B. Plano, Y. Deshayes, L. Béchou, Y. Danto
Presents some results in order to derive reliability behaviour of BGA (ball grid array) assemblies when they are submitted to thermal cycles mission profile, as it is now common in a lot of industrial applications. In the field of surface mounted technology (SMT), reliability testing has become longer and very expensive. This is due to the large variety of technological features that can be encountered even on the same board where different package sizes and types can coexist. It is important in this case to identify the most critical attribute and to try to simplify the reliability test procedure through the definition of a "generic" accelerated test, performed on only one assembly and extensible to package configurations on condition that the assembling technology has not changed.
{"title":"Reliability estimation of BGA and CSP assemblies using degradation law model and technological parameters deviations","authors":"J. Delétage, F. Verdier, B. Plano, Y. Deshayes, L. Béchou, Y. Danto","doi":"10.1109/IPFA.2002.1025609","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025609","url":null,"abstract":"Presents some results in order to derive reliability behaviour of BGA (ball grid array) assemblies when they are submitted to thermal cycles mission profile, as it is now common in a lot of industrial applications. In the field of surface mounted technology (SMT), reliability testing has become longer and very expensive. This is due to the large variety of technological features that can be encountered even on the same board where different package sizes and types can coexist. It is important in this case to identify the most critical attribute and to try to simplify the reliability test procedure through the definition of a \"generic\" accelerated test, performed on only one assembly and extensible to package configurations on condition that the assembling technology has not changed.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116311904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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