Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025619
Z.G. Song, J. Y. Dai, S. Ansari, C. Oh, S. Redkar
To keep the evidence of the root cause, focused ion beam (FIB) cross-section and transmission electron microscope (TEM) analysis are the effective techniques for further analysis when a unit is de-processed to contact-level and front-end layers are still intact. To make sure that FIB cross-section hits a defect, it is very important to localize the defect precisely in advance. Since the contacts are the only access to the front-end layers of a semiconductor device, it should be possible to utilize them as probes to pinpoint the defects related to the front-end processes. In this paper, The technique of contact-level passive voltage contrast was employed to identify the contacts with abnormal contrast and thus localize the front-end processing defects.
{"title":"Front-end processing defect localization by contact-level passive voltage contrast technique and root cause analysis","authors":"Z.G. Song, J. Y. Dai, S. Ansari, C. Oh, S. Redkar","doi":"10.1109/IPFA.2002.1025619","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025619","url":null,"abstract":"To keep the evidence of the root cause, focused ion beam (FIB) cross-section and transmission electron microscope (TEM) analysis are the effective techniques for further analysis when a unit is de-processed to contact-level and front-end layers are still intact. To make sure that FIB cross-section hits a defect, it is very important to localize the defect precisely in advance. Since the contacts are the only access to the front-end layers of a semiconductor device, it should be possible to utilize them as probes to pinpoint the defects related to the front-end processes. In this paper, The technique of contact-level passive voltage contrast was employed to identify the contacts with abnormal contrast and thus localize the front-end processing defects.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121074830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025604
E. I. Cole, P. Tangyunyong, C. Hawkins, M. Bruce, V. Bruce, R. Ring, W.-L. Chong
Resistive interconnection localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.
{"title":"Resistive interconnection localization","authors":"E. I. Cole, P. Tangyunyong, C. Hawkins, M. Bruce, V. Bruce, R. Ring, W.-L. Chong","doi":"10.1109/IPFA.2002.1025604","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025604","url":null,"abstract":"Resistive interconnection localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025667
A. V. Vairagar, S. B. Patil, D. Pete, P. C. Waghmare, R. Dusane, N. Venkatramani, V. Ramgopal Rao
In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.
{"title":"Suppression of boron penetration by hot wire CVD polysilicon","authors":"A. V. Vairagar, S. B. Patil, D. Pete, P. C. Waghmare, R. Dusane, N. Venkatramani, V. Ramgopal Rao","doi":"10.1109/IPFA.2002.1025667","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025667","url":null,"abstract":"In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127089591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025632
H. Nguyen, C. Salm, J. Vroemen, J. Voets, B. Krabbenborg, J. Bisschop, A. Mouthaan, F. Kuper
Temperature cycling in power ICs is a reliability hazard, even more so when electromigration is playing a role as well. The frequency of the temperature cycling is in the audio domain, which makes it impossible to test in environmental chambers. In the paper, the design and application of a novel test chip to study fast temperature cycling, electromigration and their interaction in multilevel interconnection systems is reported. Incorporated into the test chip are a heating element, a temperature sensor, and extrusion monitors. Simulation was used to study the initial stress distributions after processing and local temperature distributions in the test chip during the temperature transient. First experimental results have been obtained in the area of fast temperature cycling experiments (by using internal heating only) and electromigration experiments. Failure distributions and failure modes are discussed. Results indicate that on-chip cycling is a powerful tool to study reliability of power ICs under realistic conditions.
{"title":"Test chip for detecting thin film cracking induced by fast temperature cycling and electromigration in multilevel interconnect systems","authors":"H. Nguyen, C. Salm, J. Vroemen, J. Voets, B. Krabbenborg, J. Bisschop, A. Mouthaan, F. Kuper","doi":"10.1109/IPFA.2002.1025632","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025632","url":null,"abstract":"Temperature cycling in power ICs is a reliability hazard, even more so when electromigration is playing a role as well. The frequency of the temperature cycling is in the audio domain, which makes it impossible to test in environmental chambers. In the paper, the design and application of a novel test chip to study fast temperature cycling, electromigration and their interaction in multilevel interconnection systems is reported. Incorporated into the test chip are a heating element, a temperature sensor, and extrusion monitors. Simulation was used to study the initial stress distributions after processing and local temperature distributions in the test chip during the temperature transient. First experimental results have been obtained in the area of fast temperature cycling experiments (by using internal heating only) and electromigration experiments. Failure distributions and failure modes are discussed. Results indicate that on-chip cycling is a powerful tool to study reliability of power ICs under realistic conditions.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025614
M. Ker, Hsin-Chyh Hsu, Jeng-Jie Peng
A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25 /spl mu/m CMOS process.
{"title":"Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness","authors":"M. Ker, Hsin-Chyh Hsu, Jeng-Jie Peng","doi":"10.1109/IPFA.2002.1025614","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025614","url":null,"abstract":"A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25 /spl mu/m CMOS process.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025663
A. Agarwal, R. Nagarajan, J. Singh
It is shown that the LPCVD deposition technique and annealing of polysilicon effect the mechanical properties of the released structures, for micromachined sensors. Tensile residual stress is often required for a stable polysilicon MEMS structure after final release process.
{"title":"A process technique to engineer the stress of thick doped polysilicon films for MEMS applications","authors":"A. Agarwal, R. Nagarajan, J. Singh","doi":"10.1109/IPFA.2002.1025663","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025663","url":null,"abstract":"It is shown that the LPCVD deposition technique and annealing of polysilicon effect the mechanical properties of the released structures, for micromachined sensors. Tensile residual stress is often required for a stable polysilicon MEMS structure after final release process.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116367655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025646
A. Du, C. Tung, D. Lu, D. Gui, Y. F. Chow
The advancement in VLSI processes has reached such a stage that the RC delay caused by interconnects has played a major role in deciding the performance of the circuit. The low-k dielectric materials are the main research areas for next generation IC processes (N.H. Hendricks, Proc. DUMIC, pp. 17-26, 2000). The organic low-k materials are potential materials for ultra-low-k dielectrics. Due to the difficulty in TEM sample preparation, there is very little published data on microstructure study of organic low-k materials. In this paper, a few low-k organic materials are studied by TEM, EELS, FTIR and SIMS. The results show that the organic material can reach ultra low k value with good controlled nano-porous microstructure even though there is no significant change in the chemical bonding. The nano-porous structure causes the micro-roughness at the interface of dielectric layer with barrier layers.
VLSI工艺的进步已经达到了这样一个阶段，互连引起的RC延迟已经在决定电路的性能方面发挥了主要作用。低k介电材料是下一代集成电路工艺的主要研究领域(N.H. Hendricks, Proc. DUMIC, pp. 17- 26,2000)。有机低钾材料是超低钾电介质的潜在材料。由于TEM样品制备的困难，关于有机低k材料微观结构研究的文献很少。本文采用TEM、EELS、FTIR和SIMS等方法对几种低k有机材料进行了研究。结果表明，该有机材料在化学键无明显变化的情况下，可以达到超低k值，纳米孔结构控制良好。纳米孔结构导致介电层与势垒层界面处的微粗糙度。
{"title":"The organic low-k materials microstructure study","authors":"A. Du, C. Tung, D. Lu, D. Gui, Y. F. Chow","doi":"10.1109/IPFA.2002.1025646","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025646","url":null,"abstract":"The advancement in VLSI processes has reached such a stage that the RC delay caused by interconnects has played a major role in deciding the performance of the circuit. The low-k dielectric materials are the main research areas for next generation IC processes (N.H. Hendricks, Proc. DUMIC, pp. 17-26, 2000). The organic low-k materials are potential materials for ultra-low-k dielectrics. Due to the difficulty in TEM sample preparation, there is very little published data on microstructure study of organic low-k materials. In this paper, a few low-k organic materials are studied by TEM, EELS, FTIR and SIMS. The results show that the organic material can reach ultra low k value with good controlled nano-porous microstructure even though there is no significant change in the chemical bonding. The nano-porous structure causes the micro-roughness at the interface of dielectric layer with barrier layers.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130284624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025630
C. Gan, F. Wei, C. Thompson, K. Pey, W. Choi, S. Hau-Riege, B. Yu
Currently, several kilometers of interconnects are used to construct a state-of-the-art Si-based integrated circuit, which has up to 8 levels of metallization. The failure mechanisms and reliability of the different layers of metallization are assumed to be the same in circuit-level reliability analysis. Although this may be true in Al interconnects, it may not be so for Cu dual-damascene lines. In this paper, we report on differences in the failure mechanisms between the first (M1) and second (M2) levels of Cu metallization, and how it affects the overall circuit reliability for Cu metallization.
{"title":"Contrasting failure characteristics of different levels of Cu dual-damascene metallization","authors":"C. Gan, F. Wei, C. Thompson, K. Pey, W. Choi, S. Hau-Riege, B. Yu","doi":"10.1109/IPFA.2002.1025630","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025630","url":null,"abstract":"Currently, several kilometers of interconnects are used to construct a state-of-the-art Si-based integrated circuit, which has up to 8 levels of metallization. The failure mechanisms and reliability of the different layers of metallization are assumed to be the same in circuit-level reliability analysis. Although this may be true in Al interconnects, it may not be so for Cu dual-damascene lines. In this paper, we report on differences in the failure mechanisms between the first (M1) and second (M2) levels of Cu metallization, and how it affects the overall circuit reliability for Cu metallization.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"377 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025640
Ng Sea Chooi, Ng Jou Ching
Electrical properties of semiconductor devices change drastically with doping. Doping alone has no distinguishable topographical contrast or carrier concentration levels when compared to a non-doped area of an active region. As a result of that, dopant profiling and p-n junction delineation has become one very critical step in failure analysis to identify and confirm dopant abnormalities. One of the most promising techniques for two-dimensional delineation of dopants in silicon is based on chemical etching of doped regions and subsequent observation using the scanning electron microscope (SEM) or transmission electron microscope (TEM). This paper presents the use of focus ion beam (FIB) cross sectioning and selective chemical etching to perform p-n junction delineation for identifying dopant implantation defects at silicon level.
{"title":"Dopant delineation: novel technique for silicon dopant implantation defects identification","authors":"Ng Sea Chooi, Ng Jou Ching","doi":"10.1109/IPFA.2002.1025640","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025640","url":null,"abstract":"Electrical properties of semiconductor devices change drastically with doping. Doping alone has no distinguishable topographical contrast or carrier concentration levels when compared to a non-doped area of an active region. As a result of that, dopant profiling and p-n junction delineation has become one very critical step in failure analysis to identify and confirm dopant abnormalities. One of the most promising techniques for two-dimensional delineation of dopants in silicon is based on chemical etching of doped regions and subsequent observation using the scanning electron microscope (SEM) or transmission electron microscope (TEM). This paper presents the use of focus ion beam (FIB) cross sectioning and selective chemical etching to perform p-n junction delineation for identifying dopant implantation defects at silicon level.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116116158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025671
Zhichun Wang, J. Ackaert, C. Salm, E. De Backer, G. Van den bosch, W. Zawalski
In this paper, we compare the hot carrier (HC) stress and oxide breakdown results with the fast and commonly used gate leakage current measurement. A clear correlation is found between low levels of gate leakage and both HC degradation and oxide breakdown. We, for the first time, demonstrate that the value of the gate leakage current is not only a failure indicator but also a good indicator of the reliability of the devices. A new testing method was developed to reveal latent as well as actual plasma damage, for a wide range of gate oxide quality in a very fast way. The gate oxide was stressed to break down using a ramping voltage. Moreover, oxide time-to-breakdown (t/sub bd/) was measured with constant voltage stress. These two testing methods have been compared.
{"title":"Correlation between hot carrier stress, oxide breakdown and gate leakage current for monitoring plasma processing induced damage on gate oxide","authors":"Zhichun Wang, J. Ackaert, C. Salm, E. De Backer, G. Van den bosch, W. Zawalski","doi":"10.1109/IPFA.2002.1025671","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025671","url":null,"abstract":"In this paper, we compare the hot carrier (HC) stress and oxide breakdown results with the fast and commonly used gate leakage current measurement. A clear correlation is found between low levels of gate leakage and both HC degradation and oxide breakdown. We, for the first time, demonstrate that the value of the gate leakage current is not only a failure indicator but also a good indicator of the reliability of the devices. A new testing method was developed to reveal latent as well as actual plasma damage, for a wide range of gate oxide quality in a very fast way. The gate oxide was stressed to break down using a ramping voltage. Moreover, oxide time-to-breakdown (t/sub bd/) was measured with constant voltage stress. These two testing methods have been compared.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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