Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025605
R.C.J. Wang, J. Shih, L. Chu, K. Doong, L.S. Wang, P.C. Weil, D. Su, C.T. Yang, C. Chiu, D. Su, Y.K. Peng, J. Yue, J.Y.M. Lee
As the device geometry continued to be scaled toward deep sub-micron, high dose ion implantation was essential in the source/drain engineering for semiconductor device fabrication. However, carbonized photoresist residuals became a critical issue in the photoresist stripping step of high dose ion implantation process. In order to remove photoresist residuals effectively and completely, a fluorine-based gas such as CF/sub 4/ was widely used in photoresist ashing applications. A non-optimized CF/sub 4/ ashing recipe would cause fluorine penetration into the gate oxide and affect device parameters. In this work, ashing recipes with different CF/sub 4/ plasma processing times were used in the source/drain photoresist stripping process to evaluate its influence. Results of this experiment showed that longer CF/sub 4/ plasma processing time gave rise to more gate oxide thickness, higher threshold voltage, negative shift of flatband voltage, good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). In addition, oxide integrity degradation in charge-to-breakdown (Q/sub bd/) was observed.
{"title":"The effect of CF/sub 4/ plasma on the device parameters and reliability properties of 0.18 /spl mu/m MOSFETs","authors":"R.C.J. Wang, J. Shih, L. Chu, K. Doong, L.S. Wang, P.C. Weil, D. Su, C.T. Yang, C. Chiu, D. Su, Y.K. Peng, J. Yue, J.Y.M. Lee","doi":"10.1109/IPFA.2002.1025605","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025605","url":null,"abstract":"As the device geometry continued to be scaled toward deep sub-micron, high dose ion implantation was essential in the source/drain engineering for semiconductor device fabrication. However, carbonized photoresist residuals became a critical issue in the photoresist stripping step of high dose ion implantation process. In order to remove photoresist residuals effectively and completely, a fluorine-based gas such as CF/sub 4/ was widely used in photoresist ashing applications. A non-optimized CF/sub 4/ ashing recipe would cause fluorine penetration into the gate oxide and affect device parameters. In this work, ashing recipes with different CF/sub 4/ plasma processing times were used in the source/drain photoresist stripping process to evaluate its influence. Results of this experiment showed that longer CF/sub 4/ plasma processing time gave rise to more gate oxide thickness, higher threshold voltage, negative shift of flatband voltage, good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). In addition, oxide integrity degradation in charge-to-breakdown (Q/sub bd/) was observed.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025665
E. Gaumont, A. Wolter, H. Schenk, G. Georgelin, M. Schmoger
We present results of failure and reliability investigations on silicon Micro Scanning Mirrors. The electrical insulation resistance, mechanical shock resistance and long-run stability were characterized. By design optimization including a combination of filled and open insulation trenches we achieve an average insulation resistance of more than 10 G/spl Omega/ at 20 V. The experimental data from devices with an eigenfrequency between 270 Hz and 350 Hz show that they withstand a shock acceleration of more than 6900 g in 3 axes when not operated and of 2500 g at least when operated. This remarkably results are due to several optimized design aspects. In long-run tests with high deflection angles the springs were exposed to a torsional stress of up to 1.5 GPa for more than 1.6/spl times/10/sup 9/ periods. No failure or significant change of the eigenfrequency was observed.
{"title":"Mechanical and electrical failures and reliability of Micro Scanning Mirrors","authors":"E. Gaumont, A. Wolter, H. Schenk, G. Georgelin, M. Schmoger","doi":"10.1109/IPFA.2002.1025665","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025665","url":null,"abstract":"We present results of failure and reliability investigations on silicon Micro Scanning Mirrors. The electrical insulation resistance, mechanical shock resistance and long-run stability were characterized. By design optimization including a combination of filled and open insulation trenches we achieve an average insulation resistance of more than 10 G/spl Omega/ at 20 V. The experimental data from devices with an eigenfrequency between 270 Hz and 350 Hz show that they withstand a shock acceleration of more than 6900 g in 3 axes when not operated and of 2500 g at least when operated. This remarkably results are due to several optimized design aspects. In long-run tests with high deflection angles the springs were exposed to a torsional stress of up to 1.5 GPa for more than 1.6/spl times/10/sup 9/ periods. No failure or significant change of the eigenfrequency was observed.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116159696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025660
P. Durr, U. Dauderstadt, D. Kunze, M. Auvert, H. Lakner
Modern UV-lithography is searching for new highly parallel writing concepts. Spatial light modulation (SLM) with optical MEMS devices offers such possibilities. Special emphasis must be put on the ability of SLM devices to handle ultraviolet light (UV). For deep UV laser mask writing (248 nm) we designed and fabricated a 2048/spl times/512 pixel optical MEMS with individually addressable aluminum micro-mirrors. In order to support the small volume production and the qualification of such devices we have set up test and characterization systems for failure analysis and lifetime testing. In order to ensure a high quality of the optical MEMS e.g. a map of the device under test is needed showing the exact position of defective pixels together with the type of defect like not responding, always deflected, wrong spring constant, or poorly reflecting surface. Additionally information on the flatness of the mirrors and on their lifetime under UV pulsed illumination are required. This paper describes the concepts of our test systems, their experimental realization, and results obtained for our optical MEMS chips.
{"title":"Reliability test and failure analysis of optical MEMS","authors":"P. Durr, U. Dauderstadt, D. Kunze, M. Auvert, H. Lakner","doi":"10.1109/IPFA.2002.1025660","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025660","url":null,"abstract":"Modern UV-lithography is searching for new highly parallel writing concepts. Spatial light modulation (SLM) with optical MEMS devices offers such possibilities. Special emphasis must be put on the ability of SLM devices to handle ultraviolet light (UV). For deep UV laser mask writing (248 nm) we designed and fabricated a 2048/spl times/512 pixel optical MEMS with individually addressable aluminum micro-mirrors. In order to support the small volume production and the qualification of such devices we have set up test and characterization systems for failure analysis and lifetime testing. In order to ensure a high quality of the optical MEMS e.g. a map of the device under test is needed showing the exact position of defective pixels together with the type of defect like not responding, always deflected, wrong spring constant, or poorly reflecting surface. Additionally information on the flatness of the mirrors and on their lifetime under UV pulsed illumination are required. This paper describes the concepts of our test systems, their experimental realization, and results obtained for our optical MEMS chips.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025670
K.P. Cheung
Plasma charging damage to thin gate dielectric evolves with the integrated circuit technology. As gate dielectric thins down, its sensitivity to electrical stress changes, so are the impacts of such stress on device and circuit reliability. Concurrent to that change, is the change in plasma systems used in production. The convolution of the two determines the seriousness of plasma charging damage, as well as its methods of characterization. As the industry poise to make yet another major change, namely to high-k gate dielectric, the problem of plasma charging damage will have to be treated differently again.
{"title":"Plasma charging damage to gate dielectric-past, present and future","authors":"K.P. Cheung","doi":"10.1109/IPFA.2002.1025670","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025670","url":null,"abstract":"Plasma charging damage to thin gate dielectric evolves with the integrated circuit technology. As gate dielectric thins down, its sensitivity to electrical stress changes, so are the impacts of such stress on device and circuit reliability. Concurrent to that change, is the change in plasma systems used in production. The convolution of the two determines the seriousness of plasma charging damage, as well as its methods of characterization. As the industry poise to make yet another major change, namely to high-k gate dielectric, the problem of plasma charging damage will have to be treated differently again.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127899947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025616
I. Manna, P. Tan, Y. Tan, K. Lo
Studied the effect of non-destructive ESD events on hot carrier degradation parameters in an advanced deep submicron technology. Also investigated are two ESD protection strategies (substrate-biased NMOS and source injection technique) and they are shown to have unequal performance from the standpoint of hot-carrier reliability after ESD pre-stress.
{"title":"A study of interaction between electrostatic discharge and hot carrier effect and its effect on protection circuit reliability","authors":"I. Manna, P. Tan, Y. Tan, K. Lo","doi":"10.1109/IPFA.2002.1025616","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025616","url":null,"abstract":"Studied the effect of non-destructive ESD events on hot carrier degradation parameters in an advanced deep submicron technology. Also investigated are two ESD protection strategies (substrate-biased NMOS and source injection technique) and they are shown to have unequal performance from the standpoint of hot-carrier reliability after ESD pre-stress.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025638
K. Mohammad, K. Sim
The semiconductor industry is pushing the technology envelope of integrated circuit packaging: aggressively shrinking the geometry and introducing cost competitive materials and processing technology. The need for more powerful package FA techniques also increases, especially in the area of higher resolution imaging and material characterization. The field emission SEM no longer has the spatial resolution needed to image thin film interfaces found in new generation packages. Hence, TEM was called into action, especially in analyzing thin interfaces such as the solder joint interface and copper via interface. The sample preparation technique for package FA is the gating factor for TEM analysis. The conventional TEM preparation techniques such as wedge and dimpling are not compatible with the advanced packaging materials. The FIB cross-section technique is applicable but typically takes a long time to prepare by trimming to the region of interest (ROI) and then polishing to a 20 /spl mu/m sliver. There is a great need for effective TEM sample preparation techniques to make TEM available to package failure analysis. FIB lift-out and ultramicrotomy techniques have been improvised to meet this need.
{"title":"Novel application of FIB lift-out and ultramicrotomy for advanced package failure analysis","authors":"K. Mohammad, K. Sim","doi":"10.1109/IPFA.2002.1025638","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025638","url":null,"abstract":"The semiconductor industry is pushing the technology envelope of integrated circuit packaging: aggressively shrinking the geometry and introducing cost competitive materials and processing technology. The need for more powerful package FA techniques also increases, especially in the area of higher resolution imaging and material characterization. The field emission SEM no longer has the spatial resolution needed to image thin film interfaces found in new generation packages. Hence, TEM was called into action, especially in analyzing thin interfaces such as the solder joint interface and copper via interface. The sample preparation technique for package FA is the gating factor for TEM analysis. The conventional TEM preparation techniques such as wedge and dimpling are not compatible with the advanced packaging materials. The FIB cross-section technique is applicable but typically takes a long time to prepare by trimming to the region of interest (ROI) and then polishing to a 20 /spl mu/m sliver. There is a great need for effective TEM sample preparation techniques to make TEM available to package failure analysis. FIB lift-out and ultramicrotomy techniques have been improvised to meet this need.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121291029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025618
Huixian Wu, J. Cargo, J. Serpiello, J. Mcginn
There is not much work reported for RIE of polysilicon for FMA and moreover, there are still many challenging issues for RIE of poly silicon including etch selectivity, surface roughness, poly residues and the optimization of the process parameters. In this work, we have studied the poly silicon etching characteristics for chlorine and fluorine based RIE systems. We investigated the dependence of poly etch rate and etch selectivity on the process parameters including O/sub 2/ flow, chamber pressure, ICP power and RIE power. The goal of this work was to characterize the effects of process parameters on etch rate, etch selectivity and surface roughness for the etching of poly silicon over gate oxide in FMA de-processing.
{"title":"Characterization of reactive ion etching of polysilicon over gate oxide for failure mode analysis deprocessing","authors":"Huixian Wu, J. Cargo, J. Serpiello, J. Mcginn","doi":"10.1109/IPFA.2002.1025618","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025618","url":null,"abstract":"There is not much work reported for RIE of polysilicon for FMA and moreover, there are still many challenging issues for RIE of poly silicon including etch selectivity, surface roughness, poly residues and the optimization of the process parameters. In this work, we have studied the poly silicon etching characteristics for chlorine and fluorine based RIE systems. We investigated the dependence of poly etch rate and etch selectivity on the process parameters including O/sub 2/ flow, chamber pressure, ICP power and RIE power. The goal of this work was to characterize the effects of process parameters on etch rate, etch selectivity and surface roughness for the etching of poly silicon over gate oxide in FMA de-processing.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131548414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025612
S. Voldman
Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis in the models, methodology, and mechanisms evaluation for improving ESD robustness of semiconductor products and magnetic recording heads are discussed.
{"title":"Electrostatic discharge (ESD) and failure analysis: models, methodologies and mechanisms","authors":"S. Voldman","doi":"10.1109/IPFA.2002.1025612","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025612","url":null,"abstract":"Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis in the models, methodology, and mechanisms evaluation for improving ESD robustness of semiconductor products and magnetic recording heads are discussed.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130388506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025636
P. Jacob
OBIRCH has been shown to be a suitable instrument for failure- and weakness detection in power semiconductor devices, where emission microscopy (EMMI) is usually impossible due to the thick metal layers and high doping concentrations of the silicon (allowing no backside access). Since the current sensitivity performance of this method is outstanding, OBIRCH does not only detect the main leakage path, but additional/potential bypass paths or weaknesses, too. Thus, physical analysis may even be possible in those cases where the main leakage path does not allow further physical conclusions due to the critical structures being melted.
{"title":"Defect- and structure-weakness-localization on power semiconductors using OBIRCH (optical beam induced resistivity change)","authors":"P. Jacob","doi":"10.1109/IPFA.2002.1025636","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025636","url":null,"abstract":"OBIRCH has been shown to be a suitable instrument for failure- and weakness detection in power semiconductor devices, where emission microscopy (EMMI) is usually impossible due to the thick metal layers and high doping concentrations of the silicon (allowing no backside access). Since the current sensitivity performance of this method is outstanding, OBIRCH does not only detect the main leakage path, but additional/potential bypass paths or weaknesses, too. Thus, physical analysis may even be possible in those cases where the main leakage path does not allow further physical conclusions due to the critical structures being melted.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116378364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025635
X. Gagnard, O. Bonnaud
A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.
{"title":"Building-in reliability, application to bipolar/CMOS/DMOS technology","authors":"X. Gagnard, O. Bonnaud","doi":"10.1109/IPFA.2002.1025635","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025635","url":null,"abstract":"A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134274404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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