Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025649
V.K. Wong, P.F. Low, C.H. Lock, K. H. Siek
In this paper, we present the multiple techniques analysis of a blocked p+ implant in a p/sup +//N-well diode which forms the ESD protection of a pin. We will describe the leakage model and various observations that are made by advanced failure analysis tools. Since the pn junction forms one of the fundamental devices in realizing the MOSFET, the understanding of the characteristics of the malformed diode is crucial for predicting the effect of partially blocked source/drain implants for future failure analysis.
{"title":"Multiple techniques approach failure analysis for a blocked p+ implant induced leakage in an ESD protection diode","authors":"V.K. Wong, P.F. Low, C.H. Lock, K. H. Siek","doi":"10.1109/IPFA.2002.1025649","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025649","url":null,"abstract":"In this paper, we present the multiple techniques analysis of a blocked p+ implant in a p/sup +//N-well diode which forms the ESD protection of a pin. We will describe the leakage model and various observations that are made by advanced failure analysis tools. Since the pn junction forms one of the fundamental devices in realizing the MOSFET, the understanding of the characteristics of the malformed diode is crucial for predicting the effect of partially blocked source/drain implants for future failure analysis.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126563583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025611
Y. Deshayes, L. Bechoul, Y. Danto
Deals with results achieved from nonlinear thermomechanical simulations using finite element method (FEM) of a direct modulation 1.55 /spl mu/m laser module for telecommunication applications. In this paper, two main parts will be developed: evaluation of stresses and strains in the critical zones based on both technological and thermomechanical analyses of the whole laser module (construction design, dissimilar materials, mismatched CTE) and relation between calculated strains and optical misalignment responsible for gradual power drift. Experimental failure analysis will be also conducted to validate thermomechanical simulations, focused in particular on laser weld joints. In this context, both thermal, electrical and thermomechanical simulations on the package must be realized using an original approach based on multiphysics computations of ANSYS software.
{"title":"Three-dimensional FEM simulations of thermomechanical stresses in 1.55 /spl mu/m laser modules","authors":"Y. Deshayes, L. Bechoul, Y. Danto","doi":"10.1109/IPFA.2002.1025611","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025611","url":null,"abstract":"Deals with results achieved from nonlinear thermomechanical simulations using finite element method (FEM) of a direct modulation 1.55 /spl mu/m laser module for telecommunication applications. In this paper, two main parts will be developed: evaluation of stresses and strains in the critical zones based on both technological and thermomechanical analyses of the whole laser module (construction design, dissimilar materials, mismatched CTE) and relation between calculated strains and optical misalignment responsible for gradual power drift. Experimental failure analysis will be also conducted to validate thermomechanical simulations, focused in particular on laser weld joints. In this context, both thermal, electrical and thermomechanical simulations on the package must be realized using an original approach based on multiphysics computations of ANSYS software.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025633
H. Ceric, S. Selberherr
One of the most important issues in the reliability study of IC interconnect lines is electromigration. This phenomenon results in the formation and growth of voids in metal interconnects, which can cause significant fluctuations in interconnect resistance and in the extreme case sever the interconnect line. The electromigration failure occurs, according to different failure criteria by a resistance change of 10-20 %. To accurately simulate interconnect resistance change due to electromigration, tracking the void shape and position is necessary. Simulations of void evolution in linear interconnects began with sharp interface models which showed the insufficiency of these models (D.R. Fridline and A.F. Bower, 1999; M.K. Gungor and D. Maroudas, 1999). Later, prompted by the complexity of void surfaces, diffuse interface models were introduced (R.B.M. Mahadevan, 1999). An alternative diffuse interface model based on the double obstacle potential was proposed by D.N. Bhate et al (2000). However, all these methods require structured underlying meshes and were applied to simple rectangular interconnect geometries. To reach higher mesh adaptability and appropriate refinement quality for the finite element scheme solving diffuse interface models, we used a version of the recursive local mesh refinement algorithm introduced by J. Kossacky (J. Comput. Appl. Math., vol. 55, pp. 275-288, 1994).
电迁移是集成电路互连线路可靠性研究中的一个重要问题。这种现象会导致金属互连中空洞的形成和生长，从而导致互连电阻的显著波动，在极端情况下会切断互连线路。根据不同的失效准则，电迁移会发生10- 20%的电阻变化。为了准确地模拟由于电迁移引起的互连电阻变化，跟踪空洞的形状和位置是必要的。线性互连中空洞演化的模拟从尖锐界面模型开始，显示出这些模型的不足(D.R. Fridline和A.F. Bower, 1999;M.K. Gungor and D. Maroudas, 1999)。后来，由于空洞表面的复杂性，引入了漫射界面模型(R.B.M. Mahadevan, 1999)。D.N. Bhate等人(2000)提出了另一种基于双障碍势的扩散界面模型。然而，所有这些方法都需要结构化的底层网格，并应用于简单的矩形互连几何。为了对求解扩散界面模型的有限元方案达到更高的网格适应性和适当的细化质量，我们使用了J. Kossacky (J. Comput)引入的递归局部网格细化算法的一个版本。达成。数学。，第55卷，275-288页，1994年)。
{"title":"Electromigration induced evolution of voids in current crowding areas of interconnects","authors":"H. Ceric, S. Selberherr","doi":"10.1109/IPFA.2002.1025633","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025633","url":null,"abstract":"One of the most important issues in the reliability study of IC interconnect lines is electromigration. This phenomenon results in the formation and growth of voids in metal interconnects, which can cause significant fluctuations in interconnect resistance and in the extreme case sever the interconnect line. The electromigration failure occurs, according to different failure criteria by a resistance change of 10-20 %. To accurately simulate interconnect resistance change due to electromigration, tracking the void shape and position is necessary. Simulations of void evolution in linear interconnects began with sharp interface models which showed the insufficiency of these models (D.R. Fridline and A.F. Bower, 1999; M.K. Gungor and D. Maroudas, 1999). Later, prompted by the complexity of void surfaces, diffuse interface models were introduced (R.B.M. Mahadevan, 1999). An alternative diffuse interface model based on the double obstacle potential was proposed by D.N. Bhate et al (2000). However, all these methods require structured underlying meshes and were applied to simple rectangular interconnect geometries. To reach higher mesh adaptability and appropriate refinement quality for the finite element scheme solving diffuse interface models, we used a version of the recursive local mesh refinement algorithm introduced by J. Kossacky (J. Comput. Appl. Math., vol. 55, pp. 275-288, 1994).","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025615
I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, M. Ker
Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.
{"title":"Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product","authors":"I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, M. Ker","doi":"10.1109/IPFA.2002.1025615","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025615","url":null,"abstract":"Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025608
N. K. Jha, M.S. Baghini, V. Rao
The effect of channel hot carrier (CHC) stress under typical analog operating conditions is studied for the first time for single halo (SH) p-MOSFET devices. The SH devices show less degradation under identical operating conditions compared to conventional MOSFETs. The effect of SH implant parameters on device degradation is presented.
{"title":"Performance and reliability of single halo deep sub-micron p-MOSFETs for analog applications","authors":"N. K. Jha, M.S. Baghini, V. Rao","doi":"10.1109/IPFA.2002.1025608","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025608","url":null,"abstract":"The effect of channel hot carrier (CHC) stress under typical analog operating conditions is studied for the first time for single halo (SH) p-MOSFET devices. The SH devices show less degradation under identical operating conditions compared to conventional MOSFETs. The effect of SH implant parameters on device degradation is presented.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025628
J. Gambino, A. Stamper, T. McDevitt, V. McGahay, S. Luce, T. Pricer, B. Porth, C. Senowitz, R. Kontra, M. Gibson, H. Wildman, A. Piper, C. Benson, T. Standaert, P. Biolsi, E. Cooney
The integration of Cu with low-k dielectrics poses a number of challenges. In this paper, we describe yield issues associated with integration of three different low-k dielectrics; FSG (fluorosilicate glass), OSG (organosilicate glass), and polymers. Process issues that are discussed include patterning of the dielectrics, cleaning of the Cu surface, and Cu polishing.
{"title":"Integration of copper with low-k dielectrics for 0.13 /spl mu/m technology","authors":"J. Gambino, A. Stamper, T. McDevitt, V. McGahay, S. Luce, T. Pricer, B. Porth, C. Senowitz, R. Kontra, M. Gibson, H. Wildman, A. Piper, C. Benson, T. Standaert, P. Biolsi, E. Cooney","doi":"10.1109/IPFA.2002.1025628","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025628","url":null,"abstract":"The integration of Cu with low-k dielectrics poses a number of challenges. In this paper, we describe yield issues associated with integration of three different low-k dielectrics; FSG (fluorosilicate glass), OSG (organosilicate glass), and polymers. Process issues that are discussed include patterning of the dielectrics, cleaning of the Cu surface, and Cu polishing.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125601051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025674
S. Tan, C. Ang, C. Lek, T.P. Chen, B.J. Cho, A. See, L. Chan
The impact of nitrogen plasma nitridation on the interfacial quality of ultrathin oxide (1.8 nm and 2.6 nm) and negative bias temperature instability (NBTI) have been investigated. It is found that the plasma-nitridation can more effectively suppress nitrogen-induced and boron-induced hole mobility degradation than that of thermal nitridation. Therefore, a higher amount of nitrogen can be incorporated into the plasma-nitrided oxide to suppress boron penetration without compromising the oxide interfacial quality. Furthermore, plasma-nitrided oxides have higher resistance to NBTI and longer NBTI-lifetime than that of thermal-nitrided oxides.
{"title":"Characterization of ultrathin plasma nitrided gate dielectrics in pMOSFET for 0.18 /spl mu/m technology and beyond","authors":"S. Tan, C. Ang, C. Lek, T.P. Chen, B.J. Cho, A. See, L. Chan","doi":"10.1109/IPFA.2002.1025674","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025674","url":null,"abstract":"The impact of nitrogen plasma nitridation on the interfacial quality of ultrathin oxide (1.8 nm and 2.6 nm) and negative bias temperature instability (NBTI) have been investigated. It is found that the plasma-nitridation can more effectively suppress nitrogen-induced and boron-induced hole mobility degradation than that of thermal nitridation. Therefore, a higher amount of nitrogen can be incorporated into the plasma-nitrided oxide to suppress boron penetration without compromising the oxide interfacial quality. Furthermore, plasma-nitrided oxides have higher resistance to NBTI and longer NBTI-lifetime than that of thermal-nitrided oxides.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129004712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025657
A. Altes, I. Joachimsthaler, G. Zimmermann, R. Heiderhoff, L. Balk
A resistive probe based Scanning Thermal Microscope (SThM) was implemented in an analysis chamber of a Scanning Electron Microscope (SEM). By means of this hybrid-system thermal device, specific characteristics are detectable. Variable punctual heat sources can be simulated and the influence of ambient parameters can be investigated.
{"title":"SEM/SThM-hybrid-system: a new tool for advanced thermal analysis of electronic devices","authors":"A. Altes, I. Joachimsthaler, G. Zimmermann, R. Heiderhoff, L. Balk","doi":"10.1109/IPFA.2002.1025657","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025657","url":null,"abstract":"A resistive probe based Scanning Thermal Microscope (SThM) was implemented in an analysis chamber of a Scanning Electron Microscope (SEM). By means of this hybrid-system thermal device, specific characteristics are detectable. Variable punctual heat sources can be simulated and the influence of ambient parameters can be investigated.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"744 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132780408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025666
M. Mugnier, S. K. Manhas, D. Chandra Sekhar, S. Krishnan, R. Cross, E. M. Sankara Narayanan, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán
The degradation characteristics of polycrystalline silicon Off-set Drain High Voltage Thin Film Transistors (OD-HVTFTs) are reported. The results demonstrate a pronounced kink in the transfer characteristics at high gate bias, due to degradation of the offset region. This effect is particularly noticeable in non-hydrogenated HVTFTs. Annealing of devices in atmospheric ambient after stress shows temperature dependent recovery.
{"title":"Degradation behaviour of polysilicon high voltage thin film transistors","authors":"M. Mugnier, S. K. Manhas, D. Chandra Sekhar, S. Krishnan, R. Cross, E. M. Sankara Narayanan, M. M. De Souza, D. Flores, M. Vellvehí, J. Millán","doi":"10.1109/IPFA.2002.1025666","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025666","url":null,"abstract":"The degradation characteristics of polycrystalline silicon Off-set Drain High Voltage Thin Film Transistors (OD-HVTFTs) are reported. The results demonstrate a pronounced kink in the transfer characteristics at high gate bias, due to degradation of the offset region. This effect is particularly noticeable in non-hydrogenated HVTFTs. Annealing of devices in atmospheric ambient after stress shows temperature dependent recovery.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126796478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of post-decoupled-plasma-nitridation annealing of ultra-thin gate oxide","authors":"C. Lek, B. Cho, W. Loh, C. Ang, Wenhe Lin, Yun-Ling Tan, Jia-Zheng Zhen, L. Chan, S. Tan, Tupei Chen","doi":"10.1109/IPFA.2002.1025669","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025669","url":null,"abstract":"Silicon Nan0 Device Laboratory (SNDL), Dept. of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, e-mail : elebjcho@us.edu.sg 'Chartered Semiconductor Manufacturing Ltd, Technology Development Department, 60 Woodlands Industrial Park D, Street 2, Singapore 738406 Department of Electrical & Electronics Engineering, Nanyang Technological University, Nanyang Avenue. Singapore 639798 2","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132289872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：