Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718265
J. Troe
The age of mobile data is upon us, and all indications point to a worldwide growth comparable to the rapid growth of cellular telephony. This paper provides an overview of mobile data options available to users, and provides a description of a specific mobile data option, the RAM Mobile Data, Inc. program. The Ericsson Mobitex packet switched mobile data system is now in operation in Scandinavia and Canada. RAM Mobile Data, Inc. is operating a growing national public Mobitex network in the U.S., and will soon be operating Mobitex networks in the U.K., and in other countries not yet announced. The system architecture is "open," and an interface specification is available which will permit any company to enter the mobile data business by providing mobile and portable radio/terminal equipment, and application software, to users of the RAM networks.
{"title":"Mobile-Data Packet-Networks","authors":"J. Troe","doi":"10.1109/ELECTR.1991.718265","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718265","url":null,"abstract":"The age of mobile data is upon us, and all indications point to a worldwide growth comparable to the rapid growth of cellular telephony. This paper provides an overview of mobile data options available to users, and provides a description of a specific mobile data option, the RAM Mobile Data, Inc. program. The Ericsson Mobitex packet switched mobile data system is now in operation in Scandinavia and Canada. RAM Mobile Data, Inc. is operating a growing national public Mobitex network in the U.S., and will soon be operating Mobitex networks in the U.K., and in other countries not yet announced. The system architecture is \"open,\" and an interface specification is available which will permit any company to enter the mobile data business by providing mobile and portable radio/terminal equipment, and application software, to users of the RAM networks.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"BC-19 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718263
F. Pourboghrat
In this paper, the applications of neural networks for the design of learning controllers are discussed. It is argued that the usual error back propagation (EBP) algorithm cannot be readily used for the training of neural controllers. Instead, in order to ensure the convergence of the training process and the stability of the closed-loop system, a stability approach must be taken to derive a learning algorithm. We use Liapunov's stability approach to develop a learning rule for neural network controllers that would guarantee the stability of the training process under mild conditions, These controllers do not require a priori information about the plant dynamics. The designed controller is then used for the control of robots.
{"title":"Aplications Of Neural Networks In The Controller Design","authors":"F. Pourboghrat","doi":"10.1109/ELECTR.1991.718263","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718263","url":null,"abstract":"In this paper, the applications of neural networks for the design of learning controllers are discussed. It is argued that the usual error back propagation (EBP) algorithm cannot be readily used for the training of neural controllers. Instead, in order to ensure the convergence of the training process and the stability of the closed-loop system, a stability approach must be taken to derive a learning algorithm. We use Liapunov's stability approach to develop a learning rule for neural network controllers that would guarantee the stability of the training process under mild conditions, These controllers do not require a priori information about the plant dynamics. The designed controller is then used for the control of robots.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124945404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718296
M. Spitzer
This paper provides a discussion of current progress in III-V multijunction solar cells. A review of tandem cell principles is first presented, followed by a review of current research results reported by several active groups. Structures yielding efficiencies in the range of 25% to 35% are discussed. A brief discussion of the attainable efficiency in a three-junction approach is presented.
{"title":"Advances In High Performance Multijunction III-V Solar Cells","authors":"M. Spitzer","doi":"10.1109/ELECTR.1991.718296","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718296","url":null,"abstract":"This paper provides a discussion of current progress in III-V multijunction solar cells. A review of tandem cell principles is first presented, followed by a review of current research results reported by several active groups. Structures yielding efficiencies in the range of 25% to 35% are discussed. A brief discussion of the attainable efficiency in a three-junction approach is presented.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125207156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718220
J. Handy
In the span of only five years cache memories, once an arcane method of eking the last ounce of processing power from large mainframe computers, have become a household word. Caches are now offered in most high-end personal computers, as well as in all workstations. Caches offer a means of putting today's CPU architectures to their highest capability, without requiring massive changes in the direction of processing. This does not imply that we have reached a steady state, where the only developments to be expected will be improvements in CPU speed and cache size. The cache will be found to facilitate radical changes in computer architecture without requiring equivalent changes in CPU design. Caches are already being used to allow the implementation of tightly-coupled multiprocessor systems, some of whose throughputs are more than proportional to the number of processors used in the system.
{"title":"Where Are Cache Memories Going?","authors":"J. Handy","doi":"10.1109/ELECTR.1991.718220","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718220","url":null,"abstract":"In the span of only five years cache memories, once an arcane method of eking the last ounce of processing power from large mainframe computers, have become a household word. Caches are now offered in most high-end personal computers, as well as in all workstations. Caches offer a means of putting today's CPU architectures to their highest capability, without requiring massive changes in the direction of processing. This does not imply that we have reached a steady state, where the only developments to be expected will be improvements in CPU speed and cache size. The cache will be found to facilitate radical changes in computer architecture without requiring equivalent changes in CPU design. Caches are already being used to allow the implementation of tightly-coupled multiprocessor systems, some of whose throughputs are more than proportional to the number of processors used in the system.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718242
G. Randall, P. Denardo
{"title":"Physical Integration As A Phase Of CIM","authors":"G. Randall, P. Denardo","doi":"10.1109/ELECTR.1991.718242","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718242","url":null,"abstract":"","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"612 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718270
J. Brown
The IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture [1] as well as other scan path methodologies use a serial interface for transmitting data to and from the circuit under test. This serial communication presents an efficiency problem in transferring data between a processor and the scan ring. This paper describes the architecture and features of a device that interfaces a parallel host bus to a serial test bus. The Parallel/Serial (P/S) Converter integrates several features to simplify board test and offers a way to make scan operations more efficient by managing shift operations directly in hardware.
{"title":"Design Of A Parallel Bus-to-Scan Test Port Converter","authors":"J. Brown","doi":"10.1109/ELECTR.1991.718270","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718270","url":null,"abstract":"The IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture [1] as well as other scan path methodologies use a serial interface for transmitting data to and from the circuit under test. This serial communication presents an efficiency problem in transferring data between a processor and the scan ring. This paper describes the architecture and features of a device that interfaces a parallel host bus to a serial test bus. The Parallel/Serial (P/S) Converter integrates several features to simplify board test and offers a way to make scan operations more efficient by managing shift operations directly in hardware.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718274
E. Belohoubek
Samples of high-Tc superconductors are becoming readily available from a variety of sources. This paper explores the basic properties of these new materials with respect to their applicability to microwave components and systems, and provides an over-view of the state-of-the-art for the most important microwave characteristics.
{"title":"Properties Of High-T/sub c/ Superconductors At Microwave Frequencies","authors":"E. Belohoubek","doi":"10.1109/ELECTR.1991.718274","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718274","url":null,"abstract":"Samples of high-Tc superconductors are becoming readily available from a variety of sources. This paper explores the basic properties of these new materials with respect to their applicability to microwave components and systems, and provides an over-view of the state-of-the-art for the most important microwave characteristics.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718204
W. Gutschick
Advances in programmable logic are moving these devices from the category of "specialty devices" to "standard devices" that are used in almost every digital design. As the devices have become more complex, the design software needed to design with them has become more complex, the design software needed to design with them has become more sophisticated. In fact, in many cases choosing the right design software is as important as choosing the devices themselves. Many engineers would even argue that choosing the right software is more important than the silicon since the software can be the factor which limits the usefulness of the silicon and quality of the design.
{"title":"Choosing The Software Is As Important As Choosing The Silicon","authors":"W. Gutschick","doi":"10.1109/ELECTR.1991.718204","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718204","url":null,"abstract":"Advances in programmable logic are moving these devices from the category of \"specialty devices\" to \"standard devices\" that are used in almost every digital design. As the devices have become more complex, the design software needed to design with them has become more complex, the design software needed to design with them has become more sophisticated. In fact, in many cases choosing the right design software is as important as choosing the devices themselves. Many engineers would even argue that choosing the right software is more important than the silicon since the software can be the factor which limits the usefulness of the silicon and quality of the design.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718653
Z. Amitai, D. Wyland
Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.
{"title":"Burst Mode Memories Improve Cache Design","authors":"Z. Amitai, D. Wyland","doi":"10.1109/ELECTR.1991.718653","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718653","url":null,"abstract":"Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115967985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-16DOI: 10.1109/ELECTR.1991.718268
J. Andrews
With increased system packaging density, testability advantages of scan design were applied to IC boundary pins for ensured pin access where direct physical contact was becoming increasingly difficult. As the advantages of boundary-scan were becoming recognized in many commercial applications, it became apparent that a universal definition was needed to achieve the economies of using an industry standard. This led to the 1990 approval of IEEE Standard 1149. 1.
{"title":"IEEE Standard Boundary Scan 1149.1 An Introduction","authors":"J. Andrews","doi":"10.1109/ELECTR.1991.718268","DOIUrl":"https://doi.org/10.1109/ELECTR.1991.718268","url":null,"abstract":"With increased system packaging density, testability advantages of scan design were applied to IC boundary pins for ensured pin access where direct physical contact was becoming increasingly difficult. As the advantages of boundary-scan were becoming recognized in many commercial applications, it became apparent that a universal definition was needed to achieve the economies of using an industry standard. This led to the 1990 approval of IEEE Standard 1149. 1.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114727426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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