Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606271
M. Harada, R. Satoh, O. Yamada, A. Yabushita, M. Itoh, T. Netsu, T. Terouchi
The demand for reliable thin-film metallization that can be repaired repeatedly by soldering has been increasing because multichip module on ceramic (MCM-C) has become widely used in workstations as well as main frame computers. This kind of metallization is also suitable for use with Pb-free solder with a high Sn content whereas a conventional metallization is consumed quickly by Sn. A Ni-W sputtered metallization satisfying this requirement has been developed by the authors. The reaction between Ni-W and Sn during soldering creates a Sn-Ni-W alloy layer. The diffusion of Sn into Ni-W and the formation of Sn-Ni-W is slower than any other thin-film metallization for solder interconnections ever applied to electronic devices, and this makes multiple solder repairs on a substrate possible. Furthermore, Ni-W is adequate for LSI metallization. Additionally, the film thickness appropriate to given amount of solder can be determined by adding the term for solder height to the frequency factor Do. This is especially important in designing fine connections for electronic devices.
{"title":"A new Ni-W thin film metallization for solder interconnections and design method of metallization thickness","authors":"M. Harada, R. Satoh, O. Yamada, A. Yabushita, M. Itoh, T. Netsu, T. Terouchi","doi":"10.1109/ECTC.1997.606271","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606271","url":null,"abstract":"The demand for reliable thin-film metallization that can be repaired repeatedly by soldering has been increasing because multichip module on ceramic (MCM-C) has become widely used in workstations as well as main frame computers. This kind of metallization is also suitable for use with Pb-free solder with a high Sn content whereas a conventional metallization is consumed quickly by Sn. A Ni-W sputtered metallization satisfying this requirement has been developed by the authors. The reaction between Ni-W and Sn during soldering creates a Sn-Ni-W alloy layer. The diffusion of Sn into Ni-W and the formation of Sn-Ni-W is slower than any other thin-film metallization for solder interconnections ever applied to electronic devices, and this makes multiple solder repairs on a substrate possible. Furthermore, Ni-W is adequate for LSI metallization. Additionally, the film thickness appropriate to given amount of solder can be determined by adding the term for solder height to the frequency factor Do. This is especially important in designing fine connections for electronic devices.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128574631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606176
G. Rinne
A survey of the flip chip industry was undertaken to investigate the various solder bumping technologies reported in the literature. The methods are classified into four main deposition categories: vapor phase, liquid phase, solid phase, and electrochemical. Theoretical and empirical evaluations of these techniques, based on work at MCNC and Unitive Electronics Inc., are provided.
{"title":"Solder bumping methods for flip chip packaging","authors":"G. Rinne","doi":"10.1109/ECTC.1997.606176","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606176","url":null,"abstract":"A survey of the flip chip industry was undertaken to investigate the various solder bumping technologies reported in the literature. The methods are classified into four main deposition categories: vapor phase, liquid phase, solid phase, and electrochemical. Theoretical and empirical evaluations of these techniques, based on work at MCNC and Unitive Electronics Inc., are provided.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606325
S. Sathe, B. Sammakia, R. Kodnani, M. Gaynes
Electrically conductive adhesives (ECAs) have been proposed as an alternative to solder in the surface mount (SMT) and flip chip attach (FCA) applications. This paper describes the development of a transient heat transfer model of a chip bonding process using the ECA bumps. The chip is heated using a top thermode directly contacting the chip and the card is heated from the back side (Z=0) using a heater. A detailed three-dimensional heat transfer model to account for the conduction, heat storage and convection and radiation from the card is developed using the finite volume technique. The spatial and temporal temperature distributions are studied through initial ramp-up, dwell and cool-down processes. It is seen that the bump temperatures are dominated and controlled by the heating process near the chip as opposed to heating the back side of the card. The numerical model is verified via actual measurements and the agreement is within 15 percent.
{"title":"A study of the thermal characteristics of a conductive adhesive chip attach process","authors":"S. Sathe, B. Sammakia, R. Kodnani, M. Gaynes","doi":"10.1109/ECTC.1997.606325","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606325","url":null,"abstract":"Electrically conductive adhesives (ECAs) have been proposed as an alternative to solder in the surface mount (SMT) and flip chip attach (FCA) applications. This paper describes the development of a transient heat transfer model of a chip bonding process using the ECA bumps. The chip is heated using a top thermode directly contacting the chip and the card is heated from the back side (Z=0) using a heater. A detailed three-dimensional heat transfer model to account for the conduction, heat storage and convection and radiation from the card is developed using the finite volume technique. The spatial and temporal temperature distributions are studied through initial ramp-up, dwell and cool-down processes. It is seen that the bump temperatures are dominated and controlled by the heating process near the chip as opposed to heating the back side of the card. The numerical model is verified via actual measurements and the agreement is within 15 percent.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130632314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606230
R.W. Johnson
Electrical Engineering curriculums typically concentrate first on electronic circuit analysis and then on design. However, elegant circuit designs often do not translate into commercially successful products. Business, safety, manufacturing and marketing issues are also key elements in viable product development. To involve the students in the broader scope of electronic product development, a two quarter Student Factory Senior Design project has been created. In this class, students progress from product concept to actual product sales and cover all of the steps in between. The objective of the course is to provide the students with firsthand experience in the complex interactions involved with product development and commercialization. This paper describes the class organization and operation. The product developed, a desktop thermometer, is also discussed.
{"title":"The student factory at Auburn University","authors":"R.W. Johnson","doi":"10.1109/ECTC.1997.606230","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606230","url":null,"abstract":"Electrical Engineering curriculums typically concentrate first on electronic circuit analysis and then on design. However, elegant circuit designs often do not translate into commercially successful products. Business, safety, manufacturing and marketing issues are also key elements in viable product development. To involve the students in the broader scope of electronic product development, a two quarter Student Factory Senior Design project has been created. In this class, students progress from product concept to actual product sales and cover all of the steps in between. The objective of the course is to provide the students with firsthand experience in the complex interactions involved with product development and commercialization. This paper describes the class organization and operation. The product developed, a desktop thermometer, is also discussed.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122227096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606308
Shouguan Lin, J. Constable, W. Brodsky, G. Thiel, D. Sun
A dendrite connector has a taller asperity field than conventional connectors. The surface texture of dendrites on 322 pads has been measured using a WYKO RST Plus/sup TM/ 3D optical profilometer. The measurements were used to build statistical distributions of the dendrite height and bearing area functions for the force and resistance models. Mechanical and electrical characteristics of a dendrite pad mating with a smooth surface have been studied using two separate experimental techniques. The first set of experiments was done using a computer controlled micro-mechanical tester. A dendrite pad was pushed by a steel rod against a smooth gold plated steel block. The rod was moved in 1 /spl mu/m steps and the resulting force and resistance at 13 current levels were recorded. In the second set of experiments, a dendrite pad was pushed against a glass microscope slide and the contacting dendrites were observed by placing the entire fixture on a Metallograph microscope. The force was applied using a differential screw and the resulting load was measured using a small load cell attached to the screw. Thus the loading process was directly observed, and images were digitized and processed to determine the contact spots and contact area. Following the mechanical loading, the dendrite samples were again scanned using the WYKO profilometer to determine the permanent deformation of the dendrites. With measured statistical data for the dendrite pads, a Greenwood and Williamson type model was used to predict the contact force and resistance. The results from the model are compared with the experimental results and observations.
{"title":"Mechanical and electrical characterization of a dendrite connector","authors":"Shouguan Lin, J. Constable, W. Brodsky, G. Thiel, D. Sun","doi":"10.1109/ECTC.1997.606308","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606308","url":null,"abstract":"A dendrite connector has a taller asperity field than conventional connectors. The surface texture of dendrites on 322 pads has been measured using a WYKO RST Plus/sup TM/ 3D optical profilometer. The measurements were used to build statistical distributions of the dendrite height and bearing area functions for the force and resistance models. Mechanical and electrical characteristics of a dendrite pad mating with a smooth surface have been studied using two separate experimental techniques. The first set of experiments was done using a computer controlled micro-mechanical tester. A dendrite pad was pushed by a steel rod against a smooth gold plated steel block. The rod was moved in 1 /spl mu/m steps and the resulting force and resistance at 13 current levels were recorded. In the second set of experiments, a dendrite pad was pushed against a glass microscope slide and the contacting dendrites were observed by placing the entire fixture on a Metallograph microscope. The force was applied using a differential screw and the resulting load was measured using a small load cell attached to the screw. Thus the loading process was directly observed, and images were digitized and processed to determine the contact spots and contact area. Following the mechanical loading, the dendrite samples were again scanned using the WYKO profilometer to determine the permanent deformation of the dendrites. With measured statistical data for the dendrite pads, a Greenwood and Williamson type model was used to predict the contact force and resistance. The results from the model are compared with the experimental results and observations.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606217
L. Higgins, R. Cole, D. Duane
The electrical performance benefits afforded by the use of low interconnect parasitic Flip Chip packaging offers even greater system level benefit when used with Multichip Modules (MCM). The flip chip bumping and assembly cost must be minimized for high volume commodity products. An evaluation was undertaken to assess the cost, performance, and reliability of gold wire ball bump assembly for a Level Two cache memory module. The module was already in development with the more standard lead-tin solder based bumping and assembly, and it was desired to determine if gold ball bump bonding could offer any advantages. In this paper, the ball bumps are characterized and the flip chip plastic ball grid array (FC-PBGA) MCM assembly process is described. The test and reliability evaluation plan for the MCM is also discussed.
{"title":"Fast static RAM Level Two cache MCM with gold wire ball bumped flip chip assembly","authors":"L. Higgins, R. Cole, D. Duane","doi":"10.1109/ECTC.1997.606217","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606217","url":null,"abstract":"The electrical performance benefits afforded by the use of low interconnect parasitic Flip Chip packaging offers even greater system level benefit when used with Multichip Modules (MCM). The flip chip bumping and assembly cost must be minimized for high volume commodity products. An evaluation was undertaken to assess the cost, performance, and reliability of gold wire ball bump assembly for a Level Two cache memory module. The module was already in development with the more standard lead-tin solder based bumping and assembly, and it was desired to determine if gold ball bump bonding could offer any advantages. In this paper, the ball bumps are characterized and the flip chip plastic ball grid array (FC-PBGA) MCM assembly process is described. The test and reliability evaluation plan for the MCM is also discussed.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606232
J. A. Walker, J. Ford, N. Basavanhally
Fabrication and performance of a silicon micromechanical optical modulator are presented. The modulator is expected to be very low cost due to the ease of providing fiber alignment to the large optical window of the device. Two packaging configurations are described which take advantage of this attribute.
{"title":"Performance and packaging implications of a MEMS based optical modulator for WDM fiber-to-the home systems","authors":"J. A. Walker, J. Ford, N. Basavanhally","doi":"10.1109/ECTC.1997.606232","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606232","url":null,"abstract":"Fabrication and performance of a silicon micromechanical optical modulator are presented. The modulator is expected to be very low cost due to the ease of providing fiber alignment to the large optical window of the device. Two packaging configurations are described which take advantage of this attribute.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606197
E. Strzelecka, D.A. Louderback, K. Bertilsson, B. Thibeault, M. Mondry, L. Coldren
Higher computer clock speeds will require alternate technologies to overcome the performance limitations of backplane electrical interconnections. One such method is to use parallel free-space beams for board-to-board interconnects. We demonstrate a free-space optical link using 980 nm vertical-cavity lasers (VCLs) as transmitters and back-side illuminated double-pass Schottky diodes as receivers. These devices are integrated on-chip with refractive microlenses, resulting in components that can be used directly in systems, without the need for external optics. A single-mode dielectrically-apertured VCL of diameter 3.1 /spl mu/m integrated with a microlens, has a far-field divergence half-angle of /spl sim/1 degree, allowing for an interconnect length of /spl sim/5 mm. VCLs of this size have bandwidths /spl sim/15 GHz at powers /spl sim/1 mW, suitable for high-speed optical interconnects. We have studied the tolerance of the free-space link to mechanical misalignments and to fabrication variations by evaluating the power throughput and crosstalk from adjacent channels positioned on a 250 /spl mu/m pitch. The misalignment tolerances were also evaluated experimentally. We achieved data transmission at 400 Mbit/s with bit error rate (BER) <10/sup -12/ through the free-space system with microlensed components. The data rate is presently limited by the packaging, not the inherent bandwidth of the VCL. We have also demonstrated data transmission at 3 Gbit/s with BER<10/sup -12/ by launching signal from the microlensed VCL directly to a fiber-coupled high-speed receiver.
{"title":"Free-space optical link realized with microlensed components","authors":"E. Strzelecka, D.A. Louderback, K. Bertilsson, B. Thibeault, M. Mondry, L. Coldren","doi":"10.1109/ECTC.1997.606197","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606197","url":null,"abstract":"Higher computer clock speeds will require alternate technologies to overcome the performance limitations of backplane electrical interconnections. One such method is to use parallel free-space beams for board-to-board interconnects. We demonstrate a free-space optical link using 980 nm vertical-cavity lasers (VCLs) as transmitters and back-side illuminated double-pass Schottky diodes as receivers. These devices are integrated on-chip with refractive microlenses, resulting in components that can be used directly in systems, without the need for external optics. A single-mode dielectrically-apertured VCL of diameter 3.1 /spl mu/m integrated with a microlens, has a far-field divergence half-angle of /spl sim/1 degree, allowing for an interconnect length of /spl sim/5 mm. VCLs of this size have bandwidths /spl sim/15 GHz at powers /spl sim/1 mW, suitable for high-speed optical interconnects. We have studied the tolerance of the free-space link to mechanical misalignments and to fabrication variations by evaluating the power throughput and crosstalk from adjacent channels positioned on a 250 /spl mu/m pitch. The misalignment tolerances were also evaluated experimentally. We achieved data transmission at 400 Mbit/s with bit error rate (BER) <10/sup -12/ through the free-space system with microlensed components. The data rate is presently limited by the packaging, not the inherent bandwidth of the VCL. We have also demonstrated data transmission at 3 Gbit/s with BER<10/sup -12/ by launching signal from the microlensed VCL directly to a fiber-coupled high-speed receiver.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122884482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606238
R. Fillion, B. Burdick, D. Shaddock, P. Piacente
An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.
{"title":"Chip scale packaging using chip-on-flex technology","authors":"R. Fillion, B. Burdick, D. Shaddock, P. Piacente","doi":"10.1109/ECTC.1997.606238","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606238","url":null,"abstract":"An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115563611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606166
G. Selvaduray, F. Baret
This paper describes the development of an engineering education curriculum in microelectronic packaging at both the undergraduate and graduate levels, at the College of Engineering, San Jose State University. Motivation for establishing courses to support such a curriculum and the needs of the local electronics industry are discussed. The undergraduate courses are taught in the lecture/laboratory mode, thus requiring students to conduct experiments. The interdisciplinary graduate curriculum is offered as an area of specialization within the Master of Science in Engineering program. Guest speakers from industry are invited to discuss advances and challenges present in this constantly evolving field. The College also offers short courses for engineers practicing in industry. With NSF funding, workshops for skills enhancement of university faculty are currently in the planning stage; four such workshops will be offered during 1997-1998.
{"title":"Microelectronics packaging curriculum development at San Jose State University","authors":"G. Selvaduray, F. Baret","doi":"10.1109/ECTC.1997.606166","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606166","url":null,"abstract":"This paper describes the development of an engineering education curriculum in microelectronic packaging at both the undergraduate and graduate levels, at the College of Engineering, San Jose State University. Motivation for establishing courses to support such a curriculum and the needs of the local electronics industry are discussed. The undergraduate courses are taught in the lecture/laboratory mode, thus requiring students to conduct experiments. The interdisciplinary graduate curriculum is offered as an area of specialization within the Master of Science in Engineering program. Guest speakers from industry are invited to discuss advances and challenges present in this constantly evolving field. The College also offers short courses for engineers practicing in industry. With NSF funding, workshops for skills enhancement of university faculty are currently in the planning stage; four such workshops will be offered during 1997-1998.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114268159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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