Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160168
P. Asbeck, L. Larson, D. Kimball, M. Kwak, M. Hassan, C. Hsia, C. Presti, A. Scuderi
Envelope tracking provides the potential for achieving high efficiency in power amplifiers for next generation wireless systems with high peak-to-average ratio signals such as LTE. Envelope modulators with low cost, high efficiency and wide bandwidth are critical enablers for the widespread application of ET. This presentation reviews the development of various Si ICs for ET applications in basestation PAs and in handset PAs. Requirements of voltage swing, bandwidth, and accuracy are first described. BCD technology-based Si ICs for envelope modulators achieving voltages as high as 50V are presented, for operation in basestations with LDMOS and GaN RF power transistors. CMOS-based Si envelope modulator ICs for operation in wireless handsets are also discussed. ET amplifiers that achieve overall efficiency as high as 45% in 20MHz LTE handset applications are presented.
{"title":"Si IC development for high efficiency envelope tracking power amplifiers","authors":"P. Asbeck, L. Larson, D. Kimball, M. Kwak, M. Hassan, C. Hsia, C. Presti, A. Scuderi","doi":"10.1109/SIRF.2012.6160168","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160168","url":null,"abstract":"Envelope tracking provides the potential for achieving high efficiency in power amplifiers for next generation wireless systems with high peak-to-average ratio signals such as LTE. Envelope modulators with low cost, high efficiency and wide bandwidth are critical enablers for the widespread application of ET. This presentation reviews the development of various Si ICs for ET applications in basestation PAs and in handset PAs. Requirements of voltage swing, bandwidth, and accuracy are first described. BCD technology-based Si ICs for envelope modulators achieving voltages as high as 50V are presented, for operation in basestations with LDMOS and GaN RF power transistors. CMOS-based Si envelope modulator ICs for operation in wireless handsets are also discussed. ET amplifiers that achieve overall efficiency as high as 45% in 20MHz LTE handset applications are presented.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160169
N. Rouhi, D. Jain, P. Burke
Many studies have suggested the potential applications of carbon nanotubes (CNT) in conventional analogue radiofrequency (RF) technology. This is due in part to near-ballistic electron transport and expected high frequency performance. In this paper, we will present the latest understanding of the potential applications of nanotubes in this broad application area.
{"title":"Radio frequency nanoelectronics based on carbon nanotubes","authors":"N. Rouhi, D. Jain, P. Burke","doi":"10.1109/SIRF.2012.6160169","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160169","url":null,"abstract":"Many studies have suggested the potential applications of carbon nanotubes (CNT) in conventional analogue radiofrequency (RF) technology. This is due in part to near-ballistic electron transport and expected high frequency performance. In this paper, we will present the latest understanding of the potential applications of nanotubes in this broad application area.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160131
J. P. Guzman, C. Calvez, R. Pilard, F. Gianesello, M. Ney, D. Gloria, C. Person
A new dielectric resonator antenna (DRA) solution for the complete integration of radio front end at 60GHz is presented. The solution is a SoC configuration consisting of an integrated PA and a CPW fed slot on 65nm CMOS SOI (Silicon on Insulator) technology from ST Microelectronics. A co-design strategy is taken into consideration to reduce the size of the system and matching circuit losses. A total size of 1mm2 die has been achieved for both PA and Antenna excitation element. The antenna element as a whole is then taken from this SoC solution into a SiP configuration which can integrate the DR and silicon based elements, achieving a high gain (5dBi) and a bandwidth of 5GHz in the specified band.
{"title":"Silicon integrated dielectric resonator antenna solution for 60GHz front-end modules","authors":"J. P. Guzman, C. Calvez, R. Pilard, F. Gianesello, M. Ney, D. Gloria, C. Person","doi":"10.1109/SIRF.2012.6160131","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160131","url":null,"abstract":"A new dielectric resonator antenna (DRA) solution for the complete integration of radio front end at 60GHz is presented. The solution is a SoC configuration consisting of an integrated PA and a CPW fed slot on 65nm CMOS SOI (Silicon on Insulator) technology from ST Microelectronics. A co-design strategy is taken into consideration to reduce the size of the system and matching circuit losses. A total size of 1mm2 die has been achieved for both PA and Antenna excitation element. The antenna element as a whole is then taken from this SoC solution into a SiP configuration which can integrate the DR and silicon based elements, achieving a high gain (5dBi) and a bandwidth of 5GHz in the specified band.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124751069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160160
R. Islam, R. Henderson
The attenuation constant of interconnects fabricated in foundry and post-CMOS processing are compared up to 110 GHz. Two dielectric materials with thicknesses less than 10 microns are deposited on a lossy silicon (Si) substrate. The interlayer dielectric (ILD) from 180 nm TSMC and benzocylobutene (BCB) are used to characterize losses measured on coplanar waveguide (CPW) and grounded CPW (GCPW) at millimeter-wave (mm-wave) frequencies. CPW lines on BCB have comparable or better loss performance compared to the foundry GCPW lines at 100 GHz.
{"title":"Performance of coplanar interconnects for millimeter-wave applications","authors":"R. Islam, R. Henderson","doi":"10.1109/SIRF.2012.6160160","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160160","url":null,"abstract":"The attenuation constant of interconnects fabricated in foundry and post-CMOS processing are compared up to 110 GHz. Two dielectric materials with thicknesses less than 10 microns are deposited on a lossy silicon (Si) substrate. The interlayer dielectric (ILD) from 180 nm TSMC and benzocylobutene (BCB) are used to characterize losses measured on coplanar waveguide (CPW) and grounded CPW (GCPW) at millimeter-wave (mm-wave) frequencies. CPW lines on BCB have comparable or better loss performance compared to the foundry GCPW lines at 100 GHz.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128281788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160124
F. Robert, P. Cathelin, P. Triaire, F. Epifano, A. Diet, M. Villegas, G. Baudoin
In this paper, we present a bandpass filter designed and implemented in 65-nm CMOS. From 0.8-2.2GHz filtering requirements are very challenging. This filter is dedicated to fully digital RF Tx cellular architectures, and is available for any Tx architecture. Our filter uses highly linear CMOS active inductors that exhibit Q factors above 1000 at cellular frequencies to reduce filter insertion losses. The highly linear characteristic of implemented active inductors drive it us to 0dBm operation while providing at least 24dB attenuation at ± 400MHz from F0. Measurement results of the filter show a central frequency (F0) of 1.8GHz with 135MHz of -3dB bandwidth (BW) with less than 0.1dB IL.
{"title":"A Tx RF 0.1dB IL bandpass filter for fully digital cellular transmitters in 65-nm CMOS","authors":"F. Robert, P. Cathelin, P. Triaire, F. Epifano, A. Diet, M. Villegas, G. Baudoin","doi":"10.1109/SIRF.2012.6160124","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160124","url":null,"abstract":"In this paper, we present a bandpass filter designed and implemented in 65-nm CMOS. From 0.8-2.2GHz filtering requirements are very challenging. This filter is dedicated to fully digital RF Tx cellular architectures, and is available for any Tx architecture. Our filter uses highly linear CMOS active inductors that exhibit Q factors above 1000 at cellular frequencies to reduce filter insertion losses. The highly linear characteristic of implemented active inductors drive it us to 0dBm operation while providing at least 24dB attenuation at ± 400MHz from F0. Measurement results of the filter show a central frequency (F0) of 1.8GHz with 135MHz of -3dB bandwidth (BW) with less than 0.1dB IL.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160140
Bo Xiang, A. Kopa, Zhongtao Fu, A. Apsel
In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip.
{"title":"An integrated Ku-band nanosecond time-stretching system using improved dispersive delay line (DDL)","authors":"Bo Xiang, A. Kopa, Zhongtao Fu, A. Apsel","doi":"10.1109/SIRF.2012.6160140","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160140","url":null,"abstract":"In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132314024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160151
E. Cohen, O. Degani, S. Ravid, D. Ritter
A three stage transformer differential cross coupled (CC) LNA and PA with integrated baluns for operation in the 57-66GHz band are presented. The LNA fabricated in a 90nm CMOS process achieves 23dB gain and 4.6dB NF at 13mA and 1.3V supply, with 0.06mm2 in size. The PA, also fabricated in a 90nm CMOS process, has maximum power added efficiency (PAE) of 19.4%, 9.4dBm Psat, and 23dB gain with a 12GHz BW and 0.05mm2 chip size. A 2 stage PA fabricated in a digital 40nm CMOS achieves 19dB gain and a record PAE of 24%. The paper analyzes the advantages of MOScap neutralization feedback compared to metal capacitors and low k transformers for process stability and broadband design. Tuning is added to the CC feedback to compensate for process variations.
{"title":"Robust 60 GHz 90nm and 40nm CMOS wideband neutralized amplifiers with 23dB gain 4.6dB NF and 24% PAE","authors":"E. Cohen, O. Degani, S. Ravid, D. Ritter","doi":"10.1109/SIRF.2012.6160151","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160151","url":null,"abstract":"A three stage transformer differential cross coupled (CC) LNA and PA with integrated baluns for operation in the 57-66GHz band are presented. The LNA fabricated in a 90nm CMOS process achieves 23dB gain and 4.6dB NF at 13mA and 1.3V supply, with 0.06mm2 in size. The PA, also fabricated in a 90nm CMOS process, has maximum power added efficiency (PAE) of 19.4%, 9.4dBm Psat, and 23dB gain with a 12GHz BW and 0.05mm2 chip size. A 2 stage PA fabricated in a digital 40nm CMOS achieves 19dB gain and a record PAE of 24%. The paper analyzes the advantages of MOScap neutralization feedback compared to metal capacitors and low k transformers for process stability and broadband design. Tuning is added to the CC feedback to compensate for process variations.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131925042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160127
V. Szortyka, K. Raczkowski, R. Vandebriel, M. Kuijk, P. Wambacq
This paper presents an analog baseband section that implements the beamforming functionality of a 40 nm digital low-power (LP) CMOS 60 GHz transmitter. An input 1dB compression point larger than 240 mVpeak over the whole band is obtained, in a circuit operating with a 1.1 V supply. The targeted phase shift resolution of 22.5 degrees is obtained. Fully automatic, digitally assisted DC offset compensation is also present on-chip. The current consumption is 70 mA.
{"title":"Analog baseband beamformer for use in a phased-array 60 GHz transmitter","authors":"V. Szortyka, K. Raczkowski, R. Vandebriel, M. Kuijk, P. Wambacq","doi":"10.1109/SIRF.2012.6160127","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160127","url":null,"abstract":"This paper presents an analog baseband section that implements the beamforming functionality of a 40 nm digital low-power (LP) CMOS 60 GHz transmitter. An input 1dB compression point larger than 240 mVpeak over the whole band is obtained, in a circuit operating with a 1.1 V supply. The targeted phase shift resolution of 22.5 degrees is obtained. Fully automatic, digitally assisted DC offset compensation is also present on-chip. The current consumption is 70 mA.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128088317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160153
R. Sorge, A. Fischer, R. Pliquett, C. Wipf, P. Schley, R. Barth
We demonstrate the increase of available collector emitter voltage of integrated vertical bipolar transistors by means of an additional lateral drift region introduced between sub collector and collector contact region. The chosen approach enables the fabrication of high voltage bipolar transistors for RF power applications alternatively to the construction of deep collector wells in vertical direction by an extra epitaxy step or ion implantation with very high energy. The new approach was verified with a modified standard SiGe:C HBT integrated in a high performance BiCMOS process. After introduction of an additional lateral drift region with a length of 1.2 μm BVCE0 of the HBT has increased from 7 V to 18 V.
{"title":"Concept of vertical bipolar transistor with lateral drift region, applied to high voltage SiGe HBT","authors":"R. Sorge, A. Fischer, R. Pliquett, C. Wipf, P. Schley, R. Barth","doi":"10.1109/SIRF.2012.6160153","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160153","url":null,"abstract":"We demonstrate the increase of available collector emitter voltage of integrated vertical bipolar transistors by means of an additional lateral drift region introduced between sub collector and collector contact region. The chosen approach enables the fabrication of high voltage bipolar transistors for RF power applications alternatively to the construction of deep collector wells in vertical direction by an extra epitaxy step or ion implantation with very high energy. The new approach was verified with a modified standard SiGe:C HBT integrated in a high performance BiCMOS process. After introduction of an additional lateral drift region with a length of 1.2 μm BVCE0 of the HBT has increased from 7 V to 18 V.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133597461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160149
E. Cohen, A. Israel, O. Degani, D. Ritter
A built in self test (BiST) system for a 60GHz phased array chip with high sensitivity large dynamic range detectors is presented. The system measures the array phase shifter relative step with an accuracy of 5deg and the gain of the TX and RX chain through loopback with an accuracy of +/-1dB across process, temperature, and voltage (PVT). The system is composed of an RF combining detector path between chains with switched coupling, low noise detectors based on self mixing, and bias circuits that compensate for temperature and process variation. The Detector off state load on the PA output is 0.2dB.
{"title":"High sensitivity detector with robust PVT performance for 60GHz BiST phased array systems in 90nm CMOS","authors":"E. Cohen, A. Israel, O. Degani, D. Ritter","doi":"10.1109/SIRF.2012.6160149","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160149","url":null,"abstract":"A built in self test (BiST) system for a 60GHz phased array chip with high sensitivity large dynamic range detectors is presented. The system measures the array phase shifter relative step with an accuracy of 5deg and the gain of the TX and RX chain through loopback with an accuracy of +/-1dB across process, temperature, and voltage (PVT). The system is composed of an RF combining detector path between chains with switched coupling, low noise detectors based on self mixing, and bias circuits that compensate for temperature and process variation. The Detector off state load on the PA output is 0.2dB.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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