Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160150
M. Kaynak, M. Wietstruck, W. Zhang, J. Drews, R. Scholz, D. Knoll, F. Korndorfer, C. Wipf, K. Schulz, M. Elkhouly, K. Kaletta, M. Suchodoletz, K. Zoschke, M. Wilke, O. Ehrmann, V. Muhlhaus, G. Liu, T. Purtova, A. Ulusoy, H. Schumacher, B. Tillack
A BiCMOS embedded RF-MEMS switch module is demonstrated. The module consists of four main blocks: 1) RF-MEMS switch technology, 2) Switch models for design-kit implementation, 3) High Voltage (HV) generation and digital interface, 4) Flexible packaging. The RF-MEMS switch technology is detailed by focusing on the contact model, especially in the down-state. Electromagnetic (EM) and lumped-element models are demonstrated to integrate into foundry process design kit (PDK). The integrated on-chip HV generation and control circuitries are described. A flexible packaging technique is also introduced to package either standalone switches or circuits with several switches.
{"title":"RF-MEMS switch module in a 0.25 μm BiCMOS technology","authors":"M. Kaynak, M. Wietstruck, W. Zhang, J. Drews, R. Scholz, D. Knoll, F. Korndorfer, C. Wipf, K. Schulz, M. Elkhouly, K. Kaletta, M. Suchodoletz, K. Zoschke, M. Wilke, O. Ehrmann, V. Muhlhaus, G. Liu, T. Purtova, A. Ulusoy, H. Schumacher, B. Tillack","doi":"10.1109/SIRF.2012.6160150","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160150","url":null,"abstract":"A BiCMOS embedded RF-MEMS switch module is demonstrated. The module consists of four main blocks: 1) RF-MEMS switch technology, 2) Switch models for design-kit implementation, 3) High Voltage (HV) generation and digital interface, 4) Flexible packaging. The RF-MEMS switch technology is detailed by focusing on the contact model, especially in the down-state. Electromagnetic (EM) and lumped-element models are demonstrated to integrate into foundry process design kit (PDK). The integrated on-chip HV generation and control circuitries are described. A flexible packaging technique is also introduced to package either standalone switches or circuits with several switches.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127805203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160144
E. Lourandakis, K. Nikellis, S. Stefanou, S. Bantas
Layout-dependent effects (LDE) as they are encountered in modern semiconductor technology processes are addressed and considered in this work. In particular, their effect on inductor modeling is discussed based on experimental results of devices fabricated and characterized in a 40 nm technology process. The proposed vector based modeling approach is accounting for these effects and its validity is demonstrated by comparison to experimental data. Improved correlation to measured inductor metrics such as inductance L and quality factor Q is demonstrated by considering the layout-dependent effects.
{"title":"Inductor modeling with layout-dependent effects in 40nm CMOS process","authors":"E. Lourandakis, K. Nikellis, S. Stefanou, S. Bantas","doi":"10.1109/SIRF.2012.6160144","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160144","url":null,"abstract":"Layout-dependent effects (LDE) as they are encountered in modern semiconductor technology processes are addressed and considered in this work. In particular, their effect on inductor modeling is discussed based on experimental results of devices fabricated and characterized in a 40 nm technology process. The proposed vector based modeling approach is accounting for these effects and its validity is demonstrated by comparison to experimental data. Improved correlation to measured inductor metrics such as inductance L and quality factor Q is demonstrated by considering the layout-dependent effects.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132597912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160121
M. Parlak, M. Matsuo, J. Buckwalter
This paper presents the design and implementation of a differential 6-bit variable gain amplifier (VGA) with low group delay imbalance over 64 gain states. Low group delay imbalance is crucial for wireless positioning technologies such as ranging biosensors. The VGA is designed to track the Friss loss and the gain variation is achieved using bias current steering. Two cascaded linear-in-magnitude stages provide 52 dB of gain control. The measured maximum group delay variation is 50 ps over 64 states. The input P1dB gain compression point ranges between -26 dBm and -15 dBm. The saturated output power is -5 dBm for 64 gain states. The VGA is implemented in a 90nm CMOS process and the chip size is 0.035mm2. The VGA consumes 14 mA from a 1.2 V supply excluding the buffer power consumption.
{"title":"A 6-bit wideband variable gain amplifier with low group delay variation in 90nm CMOS","authors":"M. Parlak, M. Matsuo, J. Buckwalter","doi":"10.1109/SIRF.2012.6160121","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160121","url":null,"abstract":"This paper presents the design and implementation of a differential 6-bit variable gain amplifier (VGA) with low group delay imbalance over 64 gain states. Low group delay imbalance is crucial for wireless positioning technologies such as ranging biosensors. The VGA is designed to track the Friss loss and the gain variation is achieved using bias current steering. Two cascaded linear-in-magnitude stages provide 52 dB of gain control. The measured maximum group delay variation is 50 ps over 64 states. The input P1dB gain compression point ranges between -26 dBm and -15 dBm. The saturated output power is -5 dBm for 64 gain states. The VGA is implemented in a 90nm CMOS process and the chip size is 0.035mm2. The VGA consumes 14 mA from a 1.2 V supply excluding the buffer power consumption.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115355575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160138
L. Roselli, F. Alimenti, M. Virili, F. Lolli, B. Popescu, D. Popescu, S. Locci, P. Lugli
This paper describes a feasibility study of a fully organic, low cost, frequency doubler for harmonic RFID applications. The proposed structure is formed by two antennas (RX and TX) printed on paper and an organic Shottky diode able to double the frequency of the received signal. To the author knowledge this contribution proofs for the first time the feasibility of a fully organic non linear electronic circuit for RFID applications.
{"title":"Feasibility study of a fully organic frequency doubler for harmonic RFID applications","authors":"L. Roselli, F. Alimenti, M. Virili, F. Lolli, B. Popescu, D. Popescu, S. Locci, P. Lugli","doi":"10.1109/SIRF.2012.6160138","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160138","url":null,"abstract":"This paper describes a feasibility study of a fully organic, low cost, frequency doubler for harmonic RFID applications. The proposed structure is formed by two antennas (RX and TX) printed on paper and an organic Shottky diode able to double the frequency of the received signal. To the author knowledge this contribution proofs for the first time the feasibility of a fully organic non linear electronic circuit for RFID applications.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"132 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124252829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160128
W. Kuhn
Silicon-on-insulator processes have the potential to realize high-quality factors in spiral inductors, but only if the loss mechanisms involved are clearly understood. Partially-depleted SOI (PD-SOI) processes must address losses in the semiconducting Silicon layer below the spiral inductor turns, even when high-resistivity substrates are employed. These losses are illustrated with a simplified lumped-element model and an array of inductors with different materials below is measured to confirm the theory. Q values achieved are up to 19 in the popular frequency range of 1 to 6 GHz without the use of expensive thick-metal in the process.
{"title":"Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes","authors":"W. Kuhn","doi":"10.1109/SIRF.2012.6160128","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160128","url":null,"abstract":"Silicon-on-insulator processes have the potential to realize high-quality factors in spiral inductors, but only if the loss mechanisms involved are clearly understood. Partially-depleted SOI (PD-SOI) processes must address losses in the semiconducting Silicon layer below the spiral inductor turns, even when high-resistivity substrates are employed. These losses are illustrated with a simplified lumped-element model and an array of inductors with different materials below is measured to confirm the theory. Q values achieved are up to 19 in the popular frequency range of 1 to 6 GHz without the use of expensive thick-metal in the process.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160130
I. Nasr, B. Laemmle, H. Knapp, G. Fischer, R. Weigel, D. Kissinger
This paper presents a wide tuning range modified Colpitts VCO with high output power. The circuit was fabricated using a lowcost SiGe technology with an ft/fmax of 170/250 GHz. The VCO can be tuned between 56.4 and 73.8 GHz having a tuning range of ≈ 27%. The maximum measured output power is +9.4 dBm, and the output power remains above +7.0 dBm over the entire tuning range. The VCO has a minimum phase noise of -95 dBc/Hz, which stays below -88 dBc/Hz over the entire tuning range. On-chip frequency dividers were used to enable easier measurement. A single transformer was designed and used simultaneously for output matching of the VCO and as an output balun. The overall chip draws 112 mA from a 3.3 V supply, where the VCO draws 45 mA of the total current.
{"title":"A wide tuning range high output power 56–74 GHz VCO with on-chip transformer load in SiGe technology","authors":"I. Nasr, B. Laemmle, H. Knapp, G. Fischer, R. Weigel, D. Kissinger","doi":"10.1109/SIRF.2012.6160130","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160130","url":null,"abstract":"This paper presents a wide tuning range modified Colpitts VCO with high output power. The circuit was fabricated using a lowcost SiGe technology with an ft/fmax of 170/250 GHz. The VCO can be tuned between 56.4 and 73.8 GHz having a tuning range of ≈ 27%. The maximum measured output power is +9.4 dBm, and the output power remains above +7.0 dBm over the entire tuning range. The VCO has a minimum phase noise of -95 dBc/Hz, which stays below -88 dBc/Hz over the entire tuning range. On-chip frequency dividers were used to enable easier measurement. A single transformer was designed and used simultaneously for output matching of the VCO and as an output balun. The overall chip draws 112 mA from a 3.3 V supply, where the VCO draws 45 mA of the total current.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128227831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160129
M. Hassan, L. Larson, V. Leung, P. Asbeck
This paper examines the sources of Receive Band Noise (RxBN) in the Envelope Tracking Power Amplifier (ETPA) system. The Envelope Amplifier (EA) nonlinearity is found to be the dominant cause. The output spectrum of the ETPA is compared for the cases of highly linear class-A EA and nonlinear EA. To improve the out-of-band noise performance of the ETPA, Digital Pre-Distortion (DPD) on the envelope path is proposed. It is shown that the out-of-band noise is reduced by 10 dB at 100 MHz offset if a highly linear envelope amplifier is used.
{"title":"Effect of envelope amplifier nonlinearities on the output spectrum of Envelope Tracking Power Amplifiers","authors":"M. Hassan, L. Larson, V. Leung, P. Asbeck","doi":"10.1109/SIRF.2012.6160129","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160129","url":null,"abstract":"This paper examines the sources of Receive Band Noise (RxBN) in the Envelope Tracking Power Amplifier (ETPA) system. The Envelope Amplifier (EA) nonlinearity is found to be the dominant cause. The output spectrum of the ETPA is compared for the cases of highly linear class-A EA and nonlinear EA. To improve the out-of-band noise performance of the ETPA, Digital Pre-Distortion (DPD) on the envelope path is proposed. It is shown that the out-of-band noise is reduced by 10 dB at 100 MHz offset if a highly linear envelope amplifier is used.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160154
C. Palego, J. Hwang, C. Merla, F. Apollonio, M. Liberti
A nanopore test circuit is proposed for single-strand DNA sequencing, which allows real-time sensing of the electric conductance of individual sections of a DNA strand as it is pulled through the nanopore by an electric current at a controlled speed. The test circuit is based on a planar microchamber with a nanochannel drilled through its multilayer graphene electrode by an electron beam. The nanochannel is self-aligned with a nanopore created in the lipid bilayer membrane of liposomes by nanosecond electric pulses. Simulation shows that by carefully controlling the magnitude, period, and repetition rate of the pulses, the diameter of the nanopore can be optimized for the best speed the DNA is pulled through the nanopore.
{"title":"Nanopore test circuit for single-strand DNA sequencing","authors":"C. Palego, J. Hwang, C. Merla, F. Apollonio, M. Liberti","doi":"10.1109/SIRF.2012.6160154","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160154","url":null,"abstract":"A nanopore test circuit is proposed for single-strand DNA sequencing, which allows real-time sensing of the electric conductance of individual sections of a DNA strand as it is pulled through the nanopore by an electric current at a controlled speed. The test circuit is based on a planar microchamber with a nanochannel drilled through its multilayer graphene electrode by an electron beam. The nanochannel is self-aligned with a nanopore created in the lipid bilayer membrane of liposomes by nanosecond electric pulses. Simulation shows that by carefully controlling the magnitude, period, and repetition rate of the pulses, the diameter of the nanopore can be optimized for the best speed the DNA is pulled through the nanopore.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130891486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160126
K. Raczkowski, S. Thijs, J. Tseng, T. Chang, Ming-Hsiang Song, D. Linten, B. Nauwelaers, P. Wambacq
This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based ESD protection schemes applied to mm-wave circuits. The measured ESD protection levels reach 4.5 kV HBM, up to 7.6 A for VFTLP tests and a record of 1 kV CDM. At the same time, the NF of the LNAs is below 8 dB and the gain above 15 dB at 60 GHz, all at 1.1 V supply. These circuits can effectively be used as input stages of a phased array receiver.
{"title":"60 GHz low noise amplifiers with 1 kV CDM protection in 40 nm LP CMOS","authors":"K. Raczkowski, S. Thijs, J. Tseng, T. Chang, Ming-Hsiang Song, D. Linten, B. Nauwelaers, P. Wambacq","doi":"10.1109/SIRF.2012.6160126","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160126","url":null,"abstract":"This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based ESD protection schemes applied to mm-wave circuits. The measured ESD protection levels reach 4.5 kV HBM, up to 7.6 A for VFTLP tests and a record of 1 kV CDM. At the same time, the NF of the LNAs is below 8 dB and the gain above 15 dB at 60 GHz, all at 1.1 V supply. These circuits can effectively be used as input stages of a phased array receiver.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121829624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160132
T. Dinc, S. Zihir, Y. Gurbuz
This paper presents a T/R (transmit/receive) module for X-Band phased arrays using a 0.25 μm SiGe BiCMOS process technology. The T/R module consists of a T/R switch, a SPDT switch, a power amplifier (PA), and a low noise amplifier (LNA). The T/R switch and SPDT switch are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum 3.2 dB insertion loss, maximum 34.8 dB isolation and has a P1dB of 28.2 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band and occupies 0.17 mm2 chip area. The PA achieves a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25% PAE in a 3 GHz bandwidth. Lastly, the LNA has a gain more than 19 dB and 1.65 dB (mean) noise figure at X-Band. More detailed analysis with extended results and utilized techniques will be presented at the conference.
{"title":"SiGe building blocks for on-chip X-Band T/R modules","authors":"T. Dinc, S. Zihir, Y. Gurbuz","doi":"10.1109/SIRF.2012.6160132","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160132","url":null,"abstract":"This paper presents a T/R (transmit/receive) module for X-Band phased arrays using a 0.25 μm SiGe BiCMOS process technology. The T/R module consists of a T/R switch, a SPDT switch, a power amplifier (PA), and a low noise amplifier (LNA). The T/R switch and SPDT switch are implemented using CMOS transistors whereas the PA and LNA are based on SiGe HBTs. The designed T/R switch achieves minimum 3.2 dB insertion loss, maximum 34.8 dB isolation and has a P1dB of 28.2 dBm at 10 GHz. The SPDT switch has less than 2.2 dB loss at X-Band and occupies 0.17 mm2 chip area. The PA achieves a small-signal gain of 25 dB and a saturated output power of 23.2 dBm with 25% PAE in a 3 GHz bandwidth. Lastly, the LNA has a gain more than 19 dB and 1.65 dB (mean) noise figure at X-Band. More detailed analysis with extended results and utilized techniques will be presented at the conference.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133246454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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