Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160162
Ziyan Xu, G. Niu
This paper presents a general purpose method of extracting RF noise in SiGe HBT base and collector currents using the very same compact models used for RFIC design. Practical issues with experimental data are discussed.
{"title":"Compact modeling based extraction of RF noise in SiGe HBT terminal currents","authors":"Ziyan Xu, G. Niu","doi":"10.1109/SIRF.2012.6160162","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160162","url":null,"abstract":"This paper presents a general purpose method of extracting RF noise in SiGe HBT base and collector currents using the very same compact models used for RFIC design. Practical issues with experimental data are discussed.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160145
M. Hellfeld, C. Carta, F. Ellinger
This paper presents the design and characterization of a vector quadrature modulator integrated circuit, fabricated in a 0.25 μm SiGe BiCMOS technology for use in a QPSK wireless transmission system at 60 GHz. The approach chosen for narrowband quadrature generation allows the integration on a 0.98 mm×0.88 mm area, significantly smaller than other reported mm-wave quadrature modulator ICs. The circuit consists of two active double-balanced mixers and a network of transmission lines, whose impedances and lengths are designed to provide simultaneously quadrature differential signals and power matching to 50 Ω for the high-frequency ports of the mixers. On-wafer characterization of the modulator showed an amplitude error of only 0.3 dB and a phase error of 20°, suitable for single-carrier QPSK communications. For optimal operation, the circuit requires -3 dBm of carrier power and 16 mA of bias current from a 3 V supply.
{"title":"Wideband 60 GHz SiGe-BiCMOS vector modulator for ultra-high-datarate wireless transmitters","authors":"M. Hellfeld, C. Carta, F. Ellinger","doi":"10.1109/SIRF.2012.6160145","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160145","url":null,"abstract":"This paper presents the design and characterization of a vector quadrature modulator integrated circuit, fabricated in a 0.25 μm SiGe BiCMOS technology for use in a QPSK wireless transmission system at 60 GHz. The approach chosen for narrowband quadrature generation allows the integration on a 0.98 mm×0.88 mm area, significantly smaller than other reported mm-wave quadrature modulator ICs. The circuit consists of two active double-balanced mixers and a network of transmission lines, whose impedances and lengths are designed to provide simultaneously quadrature differential signals and power matching to 50 Ω for the high-frequency ports of the mixers. On-wafer characterization of the modulator showed an amplitude error of only 0.3 dB and a phase error of 20°, suitable for single-carrier QPSK communications. For optimal operation, the circuit requires -3 dBm of carrier power and 16 mA of bias current from a 3 V supply.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129233267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160119
Xinbo Xiang, J. Sturm
This paper discusses a continuously tunable linear MOS resistor with bi-directional characteristics. The proposal is based on a 2nd order nonlinearity cancellation and is implemented by quasi-floating-gate (QFG) technique. The resistor is optimized for speed, noise and linearity, which makes it well-suited for tunable RF amplifiers. Parallel slices were introduced to enlarge the tuning range. A switching strategy is implemented to guarantee monotonic tuning with limited linearity loss. A testchip is fabricated in 65nm CMOS technology, which shows a -40dB distortion with moderate overdrive voltage and 200mV peak to peak signal amplitude and a high tuning ratio of 19. This MOS resistor has no static power consumption and a layout area of 39μm × 37μm.
{"title":"Tunable linear MOS resistor for RF applications","authors":"Xinbo Xiang, J. Sturm","doi":"10.1109/SIRF.2012.6160119","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160119","url":null,"abstract":"This paper discusses a continuously tunable linear MOS resistor with bi-directional characteristics. The proposal is based on a 2nd order nonlinearity cancellation and is implemented by quasi-floating-gate (QFG) technique. The resistor is optimized for speed, noise and linearity, which makes it well-suited for tunable RF amplifiers. Parallel slices were introduced to enlarge the tuning range. A switching strategy is implemented to guarantee monotonic tuning with limited linearity loss. A testchip is fabricated in 65nm CMOS technology, which shows a -40dB distortion with moderate overdrive voltage and 200mV peak to peak signal amplitude and a high tuning ratio of 19. This MOS resistor has no static power consumption and a layout area of 39μm × 37μm.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115297939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160146
C. Durand, F. Gianesello, R. Pilard, D. Gloria, Y. Imbs, R. Coffy, L. Marechal, Yonggang Jin, Y. Dodo
This paper aims to make a full evaluation of inductor performances integrated in multi layer FO-WLP technology. Technology interest for radio frequency passives is first discussed. The inductor offer, composed of four different inductor families, is described including more than 200 different inductors that were fabricated. Measurements exhibit promising quality factors for such packaging technology, with Q>;50 for a 1.1nH inductor. Comparison with inductors integrated in CMOS demonstrates a 2.4 times quality factor improvement in favor of FO-WLP while the global size is nearly identical. FO-WLP technology has then to be considered as a very promising technology for the integration of high quality passive in CMOS.
{"title":"High performance RF inductors integrated in advanced Fan-Out wafer level packaging technology","authors":"C. Durand, F. Gianesello, R. Pilard, D. Gloria, Y. Imbs, R. Coffy, L. Marechal, Yonggang Jin, Y. Dodo","doi":"10.1109/SIRF.2012.6160146","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160146","url":null,"abstract":"This paper aims to make a full evaluation of inductor performances integrated in multi layer FO-WLP technology. Technology interest for radio frequency passives is first discussed. The inductor offer, composed of four different inductor families, is described including more than 200 different inductors that were fabricated. Measurements exhibit promising quality factors for such packaging technology, with Q>;50 for a 1.1nH inductor. Comparison with inductors integrated in CMOS demonstrates a 2.4 times quality factor improvement in favor of FO-WLP while the global size is nearly identical. FO-WLP technology has then to be considered as a very promising technology for the integration of high quality passive in CMOS.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160171
M. Schroter, S. Chaudhry, J. Zheng, A. Mukherjee, A. Pawlak, S. Lehmann
The BJT/HBT compact transistor model HICUM has been used for may years in the industry for production-type circuit design. This paper presents the basic operating principles of the model in a nutshell and then provides a concise overview on its availability in foundry process design kits and corresponding product applications.
{"title":"SiGe HBT compact modeling for production-type circuit design","authors":"M. Schroter, S. Chaudhry, J. Zheng, A. Mukherjee, A. Pawlak, S. Lehmann","doi":"10.1109/SIRF.2012.6160171","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160171","url":null,"abstract":"The BJT/HBT compact transistor model HICUM has been used for may years in the industry for production-type circuit design. This paper presents the basic operating principles of the model in a nutshell and then provides a concise overview on its availability in foundry process design kits and corresponding product applications.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130870744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160165
J. Reid, J. Oliver, K. Vanhille, D. Sherrer
The development of silicon based integrated circuits has reached a point where a large portion of an RF system can be integrated onto a single die. However, to create complete RF/millimeter-wave systems, it is necessary to integrate this silicon die with several high performance passive components. Specifically, silicon integrated circuits tend to have limited performance for the design of transmission lines, filters, and antennas. The Polystrata process is a three dimensional metal micromachining process that addresses these weaknesses by providing monolithic fabrication of high performance passives. When applied to filters and upper microwave and millimeter-wave frequencies, metal micromachining can provide filter performance comparable with that of waveguide technology but 10-100× smaller. In this presentation, we will provide details of the Polystrata process, and show the performance that can be achieved with filters fabricated using this technology.
{"title":"Three dimensional metal micromachining: A disruptive technology for millimeter-wave filters","authors":"J. Reid, J. Oliver, K. Vanhille, D. Sherrer","doi":"10.1109/SIRF.2012.6160165","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160165","url":null,"abstract":"The development of silicon based integrated circuits has reached a point where a large portion of an RF system can be integrated onto a single die. However, to create complete RF/millimeter-wave systems, it is necessary to integrate this silicon die with several high performance passive components. Specifically, silicon integrated circuits tend to have limited performance for the design of transmission lines, filters, and antennas. The Polystrata process is a three dimensional metal micromachining process that addresses these weaknesses by providing monolithic fabrication of high performance passives. When applied to filters and upper microwave and millimeter-wave frequencies, metal micromachining can provide filter performance comparable with that of waveguide technology but 10-100× smaller. In this presentation, we will provide details of the Polystrata process, and show the performance that can be achieved with filters fabricated using this technology.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121824143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160170
J. Moon, M. Antcliffe, H. Seo, Shu-Ren Lin, A. Schmitz, I. Milosavljevic, K. McCalla, D. Wong, D. Gaskill, P. Campbell, Kangmu Lee, P. Asbeck
Currently, graphene is a topic of very active research fields from science to potential applications. For various RF circuit applications, including low-noise amplifiers, the unique ambipolar nature of graphene field-effect-transistors (FETs) can be utilized for high-performance frequency multipliers, mixers and high-speed radio meters. Potential integration of graphene on Silicon substrates with CMOS compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene MOSFETs to minimize parasitics and improve gate modulation efficiency in the channel with zero or a small bandgap. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. We also attempt to discuss future applications and challenges of graphene.
{"title":"Graphene review: An emerging RF technology","authors":"J. Moon, M. Antcliffe, H. Seo, Shu-Ren Lin, A. Schmitz, I. Milosavljevic, K. McCalla, D. Wong, D. Gaskill, P. Campbell, Kangmu Lee, P. Asbeck","doi":"10.1109/SIRF.2012.6160170","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160170","url":null,"abstract":"Currently, graphene is a topic of very active research fields from science to potential applications. For various RF circuit applications, including low-noise amplifiers, the unique ambipolar nature of graphene field-effect-transistors (FETs) can be utilized for high-performance frequency multipliers, mixers and high-speed radio meters. Potential integration of graphene on Silicon substrates with CMOS compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene MOSFETs to minimize parasitics and improve gate modulation efficiency in the channel with zero or a small bandgap. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. We also attempt to discuss future applications and challenges of graphene.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117323450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160141
J. Tinoco, J. Alvarado, A. G. Martinez-Lopez, J. Raskin
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.
{"title":"Impact of extrinsic capacitances on FinFETs RF performance","authors":"J. Tinoco, J. Alvarado, A. G. Martinez-Lopez, J. Raskin","doi":"10.1109/SIRF.2012.6160141","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160141","url":null,"abstract":"Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124833943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160143
A. Vishnipolsky, E. Socher
This paper presents an F band injection locked frequency tripler (ILFT). The ILFT is based on transformer coupling into the resonator of differential Colpitts oscillator. The locking range of the Tripler is between 90 to 115 GHz thus achieving 24.5% locking range. Transformers are used to couple the signals in and out of the ILFT, without additional power consuming buffers. The ILFT was implemented in 90 nm CMOS process, with a maximum power consumption of the circuit is 17 mW and area of 0.284 mm2 including bond pads.
{"title":"F — Band injection locked tripler based on Colpitts oscillator","authors":"A. Vishnipolsky, E. Socher","doi":"10.1109/SIRF.2012.6160143","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160143","url":null,"abstract":"This paper presents an F band injection locked frequency tripler (ILFT). The ILFT is based on transformer coupling into the resonator of differential Colpitts oscillator. The locking range of the Tripler is between 90 to 115 GHz thus achieving 24.5% locking range. Transformers are used to couple the signals in and out of the ILFT, without additional power consuming buffers. The ILFT was implemented in 90 nm CMOS process, with a maximum power consumption of the circuit is 17 mW and area of 0.284 mm2 including bond pads.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123576461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-01DOI: 10.1109/SIRF.2012.6160134
F. Sonnerat, R. Pilard, F. Gianesello, F. Le Pennec, C. Person, D. Gloria
In order to counteract antenna impedance mismatch due to interaction with environment, one solution is to use a tuner between the front end module and the antenna. In this paper, a 4G antenna tuner integrated in STMicroelectronics 130 nm CMOS SOI technology and operating between 2500 MHz and 2690 MHz is described. Thanks to high power CMOS SOI Digitally Tunable Capacitances (DTCs), the proposed tuner is able to match to 50 Ω an antenna presenting a VSWR degraded up to 5:1. Minimal input reflection coefficient of -10 dB is reached and promising insertion losses are obtained (minimal losses of 3.5 dB for an antenna with initial VSWR of 5:1).
{"title":"4G antenna tuner integrated in a 130 nm CMOS SOI technology","authors":"F. Sonnerat, R. Pilard, F. Gianesello, F. Le Pennec, C. Person, D. Gloria","doi":"10.1109/SIRF.2012.6160134","DOIUrl":"https://doi.org/10.1109/SIRF.2012.6160134","url":null,"abstract":"In order to counteract antenna impedance mismatch due to interaction with environment, one solution is to use a tuner between the front end module and the antenna. In this paper, a 4G antenna tuner integrated in STMicroelectronics 130 nm CMOS SOI technology and operating between 2500 MHz and 2690 MHz is described. Thanks to high power CMOS SOI Digitally Tunable Capacitances (DTCs), the proposed tuner is able to match to 50 Ω an antenna presenting a VSWR degraded up to 5:1. Minimal input reflection coefficient of -10 dB is reached and promising insertion losses are obtained (minimal losses of 3.5 dB for an antenna with initial VSWR of 5:1).","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127647707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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