Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928022
Y. Kishida, Y. Niwa, Y. Kuba, K. Komeda, Katsuhide Setoguchi, T. Matsubara, M. Yanagisawa, S. Tanahashi
In an effort to provide a breakthrough in next-generation fiber optic data links, a new type of opto-electronic package has been developed using ceramic BGA technology (OptoBGA/sup TM/). In this paper, we describe how the OptoBGA/sup TM/ has adequate electrical performance meeting OC-192 or other 10 Gbs transmission specifications. For demonstration, a 10 G serial transmitter is designed and tested to achieve sufficient electrical eye opening of LD driver output when compared to its specifications (LD driver-pulse transient time 35 ps, Imod=100 mA, 20-80%).
{"title":"Surface mountable package (OptoBGA/sup TM/) for 10 G data link","authors":"Y. Kishida, Y. Niwa, Y. Kuba, K. Komeda, Katsuhide Setoguchi, T. Matsubara, M. Yanagisawa, S. Tanahashi","doi":"10.1109/ECTC.2001.928022","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928022","url":null,"abstract":"In an effort to provide a breakthrough in next-generation fiber optic data links, a new type of opto-electronic package has been developed using ceramic BGA technology (OptoBGA/sup TM/). In this paper, we describe how the OptoBGA/sup TM/ has adequate electrical performance meeting OC-192 or other 10 Gbs transmission specifications. For demonstration, a 10 G serial transmitter is designed and tested to achieve sufficient electrical eye opening of LD driver output when compared to its specifications (LD driver-pulse transient time 35 ps, Imod=100 mA, 20-80%).","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123439251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927927
M. Farooq, S. Ray, A. Sarkhel, C. Goldsmith
Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.
{"title":"Evaluation of lead(Pb)-free ceramic ball grid array (CBGA): Wettability, microstructure and reliability","authors":"M. Farooq, S. Ray, A. Sarkhel, C. Goldsmith","doi":"10.1109/ECTC.2001.927927","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927927","url":null,"abstract":"Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123612861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927753
Y. Matsuzawa, T. Itoh, T. Suga
Although various bonding methods have been developed for flip-chip assembly, most of them cannot be applied to smaller pitch interconnection for the next generation. In the present study, a new bonding method, the surface activated bonding (SAB) is introduced. The feasibility of the SAB for bump bonding was investigated by some experiments. The Au electroplated bumps were prepared for experiments. The three different types of material, Au, Cu, and Al were used as contact metals. The reliability of interconnections was tested in temperature storage. As a result, we could achieved the bonding of microbumps with high strength and good electrical connection. It was also found that in the case of bump bonding, SAB can be done under relatively high vacuum pressure condition.
{"title":"Room-temperature interconnection of electroplated Au microbump by means of surface activated bonding method","authors":"Y. Matsuzawa, T. Itoh, T. Suga","doi":"10.1109/ECTC.2001.927753","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927753","url":null,"abstract":"Although various bonding methods have been developed for flip-chip assembly, most of them cannot be applied to smaller pitch interconnection for the next generation. In the present study, a new bonding method, the surface activated bonding (SAB) is introduced. The feasibility of the SAB for bump bonding was investigated by some experiments. The Au electroplated bumps were prepared for experiments. The three different types of material, Au, Cu, and Al were used as contact metals. The reliability of interconnections was tested in temperature storage. As a result, we could achieved the bonding of microbumps with high strength and good electrical connection. It was also found that in the case of bump bonding, SAB can be done under relatively high vacuum pressure condition.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927984
R. Coyle, A. Holliday, P. Solan, C. Yao, H.A. Cyker, J. C. Manock, R. Bond, R.E. Stenerson, R.G. Furrow, M. Occhipinti, S. Gahr
This paper summarizes efforts to improve the assembly quality and solder joint reliability of a molded, plastic ball grid array socket. Metallographic analysis shows that a ball grid array type solder interconnect has superior assembly quality compared to a butt type solder interconnect. Ball shear tests, coupled with reflow preconditioning show that the socket ball attachment exceeds industry requirements established for area array packages. Isothermal aging, ball shear tests, and X-ray fluorescence confirm that the electrolytic Ni/Au surface finish on the socket bond pads presents no risk for interfacial, intermetallic embrittlement. The coefficient of thermal expansion (CTE) of the socket is optimized through the proper selection of material and molding process. The physical property improvements are confirmed using bulk CTE measurements on sockets manufactured with and without material and process optimization. Sockets are assembled on PWB test vehicles using typical surface mount manufacturing processes and temperature cycling is used to assess the long-term, solder joint attachment reliability. Failure analysis of the thermally cycled assemblies shows that the reduction in the anisotropy and mismatch of the CTE alters the failure mode of the sockets, which results in a substantial improvement in the overall long-term attachment reliability. The improvements in solder joint reliability are correlated with the improvements in the thermal expansion properties and the enhanced reliability is discussed in terms of lowering the risk of using this socket technology in more demanding use environments.
{"title":"Solder joint attachment reliability and assembly quality of a molded ball grid array socket","authors":"R. Coyle, A. Holliday, P. Solan, C. Yao, H.A. Cyker, J. C. Manock, R. Bond, R.E. Stenerson, R.G. Furrow, M. Occhipinti, S. Gahr","doi":"10.1109/ECTC.2001.927984","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927984","url":null,"abstract":"This paper summarizes efforts to improve the assembly quality and solder joint reliability of a molded, plastic ball grid array socket. Metallographic analysis shows that a ball grid array type solder interconnect has superior assembly quality compared to a butt type solder interconnect. Ball shear tests, coupled with reflow preconditioning show that the socket ball attachment exceeds industry requirements established for area array packages. Isothermal aging, ball shear tests, and X-ray fluorescence confirm that the electrolytic Ni/Au surface finish on the socket bond pads presents no risk for interfacial, intermetallic embrittlement. The coefficient of thermal expansion (CTE) of the socket is optimized through the proper selection of material and molding process. The physical property improvements are confirmed using bulk CTE measurements on sockets manufactured with and without material and process optimization. Sockets are assembled on PWB test vehicles using typical surface mount manufacturing processes and temperature cycling is used to assess the long-term, solder joint attachment reliability. Failure analysis of the thermally cycled assemblies shows that the reduction in the anisotropy and mismatch of the CTE alters the failure mode of the sockets, which results in a substantial improvement in the overall long-term attachment reliability. The improvements in solder joint reliability are correlated with the improvements in the thermal expansion properties and the enhanced reliability is discussed in terms of lowering the risk of using this socket technology in more demanding use environments.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927717
S. Kiyono, K. Yonehara, R. Graf, W. Howell
The laminate type FBGA package is one of the advanced solution of economic chip scale package, and has started to be used for applications that require low profiles and small areas, such as cellular phones or hand held products. IBM started to use "Mold and Saw" or "Matrix" type FBGA package, a technology to align plural numbers of semiconductor chips on a segment area of the laminate, wire bond, transfer mold, then finally singulate by a dicing saw. The ability to dice the package size independent to the molding chase or punching equipment is the largest benefit of this technology. During the development stage, IBM had observed a phenomenon that the chips were completely separated into two or more segments. Initially the root cause was suspected to be the CTE difference of the materials that generates mechanical warpage to the laminate, but simulational analysis showed no impact. To solve the phenomenon, we discovered the correlation of the laminate profile, solder mask thickness variations, and mechanical stresses on the chip surface. A 'bath tub" shaped solder mask profile at the center of chip placement area on the laminate may cause excessive pressure on the chip during transferring mold compound, and result in chip fractures. Experiments using several variations of laminate profiles were used, and confirmed the larger profile can generate chip cracks. This paper contains details of the phenomenon.
{"title":"Consideration of mechanical chip crack on FBGA packages","authors":"S. Kiyono, K. Yonehara, R. Graf, W. Howell","doi":"10.1109/ECTC.2001.927717","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927717","url":null,"abstract":"The laminate type FBGA package is one of the advanced solution of economic chip scale package, and has started to be used for applications that require low profiles and small areas, such as cellular phones or hand held products. IBM started to use \"Mold and Saw\" or \"Matrix\" type FBGA package, a technology to align plural numbers of semiconductor chips on a segment area of the laminate, wire bond, transfer mold, then finally singulate by a dicing saw. The ability to dice the package size independent to the molding chase or punching equipment is the largest benefit of this technology. During the development stage, IBM had observed a phenomenon that the chips were completely separated into two or more segments. Initially the root cause was suspected to be the CTE difference of the materials that generates mechanical warpage to the laminate, but simulational analysis showed no impact. To solve the phenomenon, we discovered the correlation of the laminate profile, solder mask thickness variations, and mechanical stresses on the chip surface. A 'bath tub\" shaped solder mask profile at the center of chip placement area on the laminate may cause excessive pressure on the chip during transferring mold compound, and result in chip fractures. Experiments using several variations of laminate profiles were used, and confirmed the larger profile can generate chip cracks. This paper contains details of the phenomenon.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127476018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927851
Guo-Wei Xiao, P. Chan, A. Teng, Jian Cai, M. Yuen
The packaging of microelectromechanical systems (MEMS) is complex and it is essential to the successful commercialization of many MEMS devices. In this paper, a pressure sensor and an actuator were assembled on a flexible substrate using FCOF technology. A photolithography process was developed to meet the solder bump fabrication requirement of the sensor chip. Eutectic solder bumps (63Sn/37Pb) with 250 /spl mu/m pitch were fabricated using the electroplating process. The flexible substrate and flip-chip process were designed for the MEMS package. The electrical test results of the MEMS package satisfied the requirements of devices. The samples were evaluated and inspected using various techniques, such as scanning acoustic microscope (SAM), X-ray imaging, scanning electron microscopy (SEM), etc. The flatness of the flexible substrate was essential to the underfill process and reliability of FCOF technology. Most of the shear failure was located at the interface between the solder mask and flexible substrate after the flip-chip assembly.
{"title":"A pressure sensor using flip-chip on low-cost flexible substrate","authors":"Guo-Wei Xiao, P. Chan, A. Teng, Jian Cai, M. Yuen","doi":"10.1109/ECTC.2001.927851","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927851","url":null,"abstract":"The packaging of microelectromechanical systems (MEMS) is complex and it is essential to the successful commercialization of many MEMS devices. In this paper, a pressure sensor and an actuator were assembled on a flexible substrate using FCOF technology. A photolithography process was developed to meet the solder bump fabrication requirement of the sensor chip. Eutectic solder bumps (63Sn/37Pb) with 250 /spl mu/m pitch were fabricated using the electroplating process. The flexible substrate and flip-chip process were designed for the MEMS package. The electrical test results of the MEMS package satisfied the requirements of devices. The samples were evaluated and inspected using various techniques, such as scanning acoustic microscope (SAM), X-ray imaging, scanning electron microscopy (SEM), etc. The flatness of the flexible substrate was essential to the underfill process and reliability of FCOF technology. Most of the shear failure was located at the interface between the solder mask and flexible substrate after the flip-chip assembly.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130914925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927871
Jae-Woong Nab, K. Paik
Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New bumping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as the bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study.
{"title":"Investigation of low cost flip chip under bump metailization (UBM) systems on Cu pads","authors":"Jae-Woong Nab, K. Paik","doi":"10.1109/ECTC.2001.927871","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927871","url":null,"abstract":"Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New bumping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as the bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126632379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927684
Young-Gon Kim, I. Mohammed, Byongsu Seol, T. Kang
A two metal flex-based WAVE package has been developed to replace four metal rigid based PBGA package. High board-level reliability was the primary motivation for this project and an equivalent electrical performance was a challenging target. All the package dimensions were maintained the same as the reference package to allow direct replacement. As a result of the one-year-long development program, the required reliability and performance goals were met successfully. This paper mainly describes the WAVE package design for reliability and performance. Optimal lead design is the most important step for reliable package development. The WAVE geometry model (WAVEGM) was developed to analyze the lead type, lead orientation, bump height, and injection lift height. The 2-metal flex tape was chosen to replace the original 4-metal rigid substrate due to its thinner dielectric layer, lower dielectric constant and improved trace/space design capability. The electrical performance was verified by both simulation and actual measurements of a test device.
{"title":"Wide area vertical expansion (WAVE/sup TM/) package design for high speed application: reliability and performance","authors":"Young-Gon Kim, I. Mohammed, Byongsu Seol, T. Kang","doi":"10.1109/ECTC.2001.927684","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927684","url":null,"abstract":"A two metal flex-based WAVE package has been developed to replace four metal rigid based PBGA package. High board-level reliability was the primary motivation for this project and an equivalent electrical performance was a challenging target. All the package dimensions were maintained the same as the reference package to allow direct replacement. As a result of the one-year-long development program, the required reliability and performance goals were met successfully. This paper mainly describes the WAVE package design for reliability and performance. Optimal lead design is the most important step for reliable package development. The WAVE geometry model (WAVEGM) was developed to analyze the lead type, lead orientation, bump height, and injection lift height. The 2-metal flex tape was chosen to replace the original 4-metal rigid substrate due to its thinner dielectric layer, lower dielectric constant and improved trace/space design capability. The electrical performance was verified by both simulation and actual measurements of a test device.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927793
A. Tay, H. Zhu
This paper describes a numerical study the effect of package geometry on delaminations in plastic IC packages. A comprehensive set of linear elastic, finite element fracture analyses were carried out on a TSSOP (Thin Shrink Small Outline Package) with outer dimensions 9.7 mm/spl times/4.4 mm/spl times/1 mm and die pad dimensions 5.5 mm/spl times/3 mm -0.125 mm. The virtual crack closure method was used to calculate the strain energy release rate (ERR) at the tip of a small crack at the edge of the pad-encapsulant interface. A parametric analysis was carried out. Among other things, it was found that the size of the border between the die and the die pad had the greatest influence on the ERR. If this border was greater than 0.8 mm the ERR became more or less independent of the length of the die. This finding should be very useful for packaging design.
本文对塑料集成电路封装中封装几何形状对分层的影响进行了数值研究。对外径尺寸为9.7 mm/spl times/4.4 mm/spl times/ 1mm、模垫尺寸为5.5 mm/spl times/ 3mm -0.125 mm的TSSOP (Thin Shrink Small Outline Package)进行了一套全面的线弹性有限元断裂分析。采用虚拟裂纹闭合法计算了衬垫-密封剂界面边缘小裂纹尖端的应变能释放率(ERR)。进行了参数分析。除其他因素外，发现模具和模具垫之间的边界大小对ERR的影响最大。如果这个边界大于0.8 mm, ERR或多或少与模具的长度无关。这一发现对包装设计非常有用。
{"title":"Fracture mechanics analysis of the effect of geometry on delaminations in rectangular IC packages","authors":"A. Tay, H. Zhu","doi":"10.1109/ECTC.2001.927793","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927793","url":null,"abstract":"This paper describes a numerical study the effect of package geometry on delaminations in plastic IC packages. A comprehensive set of linear elastic, finite element fracture analyses were carried out on a TSSOP (Thin Shrink Small Outline Package) with outer dimensions 9.7 mm/spl times/4.4 mm/spl times/1 mm and die pad dimensions 5.5 mm/spl times/3 mm -0.125 mm. The virtual crack closure method was used to calculate the strain energy release rate (ERR) at the tip of a small crack at the edge of the pad-encapsulant interface. A parametric analysis was carried out. Among other things, it was found that the size of the border between the die and the die pad had the greatest influence on the ERR. If this border was greater than 0.8 mm the ERR became more or less independent of the length of the die. This finding should be very useful for packaging design.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928029
Yong-Ju Kim, Jo-Han Kim, Hyo-Seog Ryu, Young-Suk Suh, J. Wee, H. Chun, Joong-Sik Ki
In this paper, three s-parameter based techniques of meandering traces modeled on uniform transmission line model, optimized /spl Pi/-network model, and the Cauer network synthesis technique, are presented to obtain time-domain responses using time domain circuit simulators as like SPICE. And the results of simulation are compared at operating frequencies of 100 MHz, 250 MHz, and 500 MHz, respectively. Model-dependant delay difference between the uniform transmission line model and optimized /spl Pi/-network model at the frequency of 500 MHz is found to be about 32%. From these simulations, we can find that a selection of the proper model according to operating frequency on PWBs is important to obtain accurate signal integrity.
{"title":"Pico-second signal transient characterization technique of meanders through s-parameter measurement in high-speed PWB interconnects","authors":"Yong-Ju Kim, Jo-Han Kim, Hyo-Seog Ryu, Young-Suk Suh, J. Wee, H. Chun, Joong-Sik Ki","doi":"10.1109/ECTC.2001.928029","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928029","url":null,"abstract":"In this paper, three s-parameter based techniques of meandering traces modeled on uniform transmission line model, optimized /spl Pi/-network model, and the Cauer network synthesis technique, are presented to obtain time-domain responses using time domain circuit simulators as like SPICE. And the results of simulation are compared at operating frequencies of 100 MHz, 250 MHz, and 500 MHz, respectively. Model-dependant delay difference between the uniform transmission line model and optimized /spl Pi/-network model at the frequency of 500 MHz is found to be about 32%. From these simulations, we can find that a selection of the proper model according to operating frequency on PWBs is important to obtain accurate signal integrity.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125813995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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