Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927956
C. Chen, J. Zhao, Q. Chen
This paper describes a new methodology for simultaneous switching noise (SSN) simulations by using a system level signal integrity (SI) analysis software, which is combinations of a quick full wave electromagnetic field solver for multiple-layer structure based on FDTD (Finite Difference Time Domain) and a circuit solver. The solution is based on the geometry, material, stack-up structure, and basic circuit information. The simultaneous switching noise issue is studied for two types of chipset packages-OLGA (Organic Land Grid Array) and WBGA (Wirebond Ball Grid Array)-with 40 drivers switching simultaneously. Different simulation conditions, such as with or without on-die interconnection model, different on-die decoupling capacitor values, are imposed during the simulations. Simultaneous switching noise (SSN) effects such as skew, signal overshoot, ring back, and power-ground voltage fluctuations, are obtained and compared. These data can be used for a design guideline specification or for package performance improvement purposes. It is believed that all these studies are very informative to chip and package analysis and design for high-speed system applications.
本文介绍了一种利用系统级信号完整性分析软件进行同步开关噪声仿真的新方法，即基于时域有限差分(FDTD)的多层结构快速全波电磁场求解器和电路求解器的结合。该解决方案基于几何、材料、堆叠结构和基本电路信息。研究了两种类型的芯片组封装(olga (Organic Land Grid Array)和WBGA (Wirebond Ball Grid Array))在40个驱动器同时开关时的同时开关噪声问题。仿真过程中施加了不同的仿真条件，如有无片上互连模型、不同的片上去耦电容值等。同时开关噪声(SSN)的影响，如倾斜，信号超调，回环，和电源-地电压波动，得到和比较。这些数据可用于设计指南规范或用于包性能改进的目的。相信这些研究对高速系统的芯片和封装分析与设计具有重要的参考价值。
{"title":"A simulation study of simultaneous switching noise","authors":"C. Chen, J. Zhao, Q. Chen","doi":"10.1109/ECTC.2001.927956","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927956","url":null,"abstract":"This paper describes a new methodology for simultaneous switching noise (SSN) simulations by using a system level signal integrity (SI) analysis software, which is combinations of a quick full wave electromagnetic field solver for multiple-layer structure based on FDTD (Finite Difference Time Domain) and a circuit solver. The solution is based on the geometry, material, stack-up structure, and basic circuit information. The simultaneous switching noise issue is studied for two types of chipset packages-OLGA (Organic Land Grid Array) and WBGA (Wirebond Ball Grid Array)-with 40 drivers switching simultaneously. Different simulation conditions, such as with or without on-die interconnection model, different on-die decoupling capacitor values, are imposed during the simulations. Simultaneous switching noise (SSN) effects such as skew, signal overshoot, ring back, and power-ground voltage fluctuations, are obtained and compared. These data can be used for a design guideline specification or for package performance improvement purposes. It is believed that all these studies are very informative to chip and package analysis and design for high-speed system applications.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122226558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927939
W. Kroninger, F. Hecht, G. Lang, F. Mariani, S. Geyer, L. Schneider
One of the most challenging tasks in pre-assembly, coming up in recent years, is to produce thin chips. Lots of applications are standing on the horizon: Smart-cards (credit-card, telefon, security), tags and labels (tube-tickets, price-labels), memory applications (stacks of thin memory-chips). Power- and high-frequency devices are also getting thinner. Several procedures have been suggested and are in some cases already in production for manufacturing thin chips. Most promising are cluster-tools, combining several single processes in one equipment. We will look at the different process-flows and equipment-tools which are available or announced nowadays. Main aspect in judging these methods are compatibility between Front-End and Back-End, process-stability, quality and cost-effectiveness. According to product needs there will be different processes which are to be considered as best practice.
{"title":"Time for change in pre-assembly? The challenge of thin chips","authors":"W. Kroninger, F. Hecht, G. Lang, F. Mariani, S. Geyer, L. Schneider","doi":"10.1109/ECTC.2001.927939","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927939","url":null,"abstract":"One of the most challenging tasks in pre-assembly, coming up in recent years, is to produce thin chips. Lots of applications are standing on the horizon: Smart-cards (credit-card, telefon, security), tags and labels (tube-tickets, price-labels), memory applications (stacks of thin memory-chips). Power- and high-frequency devices are also getting thinner. Several procedures have been suggested and are in some cases already in production for manufacturing thin chips. Most promising are cluster-tools, combining several single processes in one equipment. We will look at the different process-flows and equipment-tools which are available or announced nowadays. Main aspect in judging these methods are compatibility between Front-End and Back-End, process-stability, quality and cost-effectiveness. According to product needs there will be different processes which are to be considered as best practice.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928031
Zhuqing Zhang, L. Fan, C. Wong
Most no-flow underfill materials are based on epoxy/anhydride chemistry. Due to the its sensitizing nature, the use of anhydride is limited and there is a need for a no-flow underfill using non-anhydride curing system. This paper presents the development of novel no-flow underfill materials based on epoxy/phenolic resin system. Epoxy and phenolic resins of different structures are evaluated in term of their curing behavior, thermo-mechanical properties and the reliability. Compared with anhydride cured epoxy resins, epoxy/phenolic resins show high adhesion, high fracture toughness, low crosslinking density and high viscosity. The assembly with non-anhydride underfill shows high reliability during the thermal shock test. Using proper fluxing agent, no-flow underfills based on epoxy/phenolic system have been developed.
{"title":"Study of non-anhydride curing system for no-flow underfill applications","authors":"Zhuqing Zhang, L. Fan, C. Wong","doi":"10.1109/ECTC.2001.928031","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928031","url":null,"abstract":"Most no-flow underfill materials are based on epoxy/anhydride chemistry. Due to the its sensitizing nature, the use of anhydride is limited and there is a need for a no-flow underfill using non-anhydride curing system. This paper presents the development of novel no-flow underfill materials based on epoxy/phenolic resin system. Epoxy and phenolic resins of different structures are evaluated in term of their curing behavior, thermo-mechanical properties and the reliability. Compared with anhydride cured epoxy resins, epoxy/phenolic resins show high adhesion, high fracture toughness, low crosslinking density and high viscosity. The assembly with non-anhydride underfill shows high reliability during the thermal shock test. Using proper fluxing agent, no-flow underfills based on epoxy/phenolic system have been developed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132556313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927875
Tie Wang, T. H. Chew, C. Lum, Y. Chew, P. Miao, L. Foo
This paper presents process concerns of flip-chip assembly via reflowable underfill in terms of substrate prebake, underfill dispensing, chip placement and overmolding that is required in certain applications. Test vehicles with various chip configurations and substrate design have been used in this study. The effects of substrate thickness, bond pad design and solder mask thickness on assembly defects, where void is the major contribution, were extensively elucidated. Meanwhile, approaches to solve the assembly failure have been successfully demonstrated by means of fine-tuning assembly parameters. It was found that voids were mainly from trapped air-bubbles during assembly, where underfill dispensing and chip placement are the major sources, rather than from reflowable underfill outgassing during reflow. The trapped voids could become aggravated after solder reflow process. In addition, pad design and solder mask thickness also significantly affect the void level. This study unveils that substrate bond pad with pre-solder on the surface traps less void than those only with nickel gold finish. For the latter case, substrate heating during underfill dispensing enables to enhance underfill flow and in turn reduces void. Furthermore, die heating that can be implemented via bonding head with heating element during chip placement will dramatically reduce void as well. Discussion will also be given on the impact of solder mask thickness and chip placement; speed (search speed) on void, in particularly for non pre-solder capped substrate.
{"title":"Assessment of flip chip assembly and reliability via reflowable underfill","authors":"Tie Wang, T. H. Chew, C. Lum, Y. Chew, P. Miao, L. Foo","doi":"10.1109/ECTC.2001.927875","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927875","url":null,"abstract":"This paper presents process concerns of flip-chip assembly via reflowable underfill in terms of substrate prebake, underfill dispensing, chip placement and overmolding that is required in certain applications. Test vehicles with various chip configurations and substrate design have been used in this study. The effects of substrate thickness, bond pad design and solder mask thickness on assembly defects, where void is the major contribution, were extensively elucidated. Meanwhile, approaches to solve the assembly failure have been successfully demonstrated by means of fine-tuning assembly parameters. It was found that voids were mainly from trapped air-bubbles during assembly, where underfill dispensing and chip placement are the major sources, rather than from reflowable underfill outgassing during reflow. The trapped voids could become aggravated after solder reflow process. In addition, pad design and solder mask thickness also significantly affect the void level. This study unveils that substrate bond pad with pre-solder on the surface traps less void than those only with nickel gold finish. For the latter case, substrate heating during underfill dispensing enables to enhance underfill flow and in turn reduces void. Furthermore, die heating that can be implemented via bonding head with heating element during chip placement will dramatically reduce void as well. Discussion will also be given on the impact of solder mask thickness and chip placement; speed (search speed) on void, in particularly for non pre-solder capped substrate.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"29 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134041163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927751
Jicun Lu, S. Busch, D. Baldwin
Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For in situ monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated.
{"title":"Solder wetting in a wafer-level flip chip assembly","authors":"Jicun Lu, S. Busch, D. Baldwin","doi":"10.1109/ECTC.2001.927751","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927751","url":null,"abstract":"Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For in situ monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127553429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927718
Y. T. Chin, C. K. Khor, H. P. Sow, S. J. Ooi, H. Tan
Present methods of attaching solder balls to ball grid array (BGA) package is through placing flux and pre-formed solder ball to substrate followed by reflow process. In the ever-moving electronic market, low cost and faster units per hour processing provides competitive edge in the manufacturing technology. Screen ball printing (BP) to form BGA balls provides an innovative processing solution to overcome the costly conventional processing method. The key challenges to this project are to fulfill specified ball dimension and yields with a comparable quality and reliability performance to the current ball attach process. The challenge associated with a print and reflow process is the requirement to print very high amount of solder paste volume on each pad to achieve specified ball height after reflow. Yield loss due to this process are related to solder ball bridging and monster ball formation. Defects will be aggravated on tight pitch printing application. This paper will discuss some of the challenges and solution for this technology.
{"title":"Breakthrough ball attach technology by introducing solder paste screen printing","authors":"Y. T. Chin, C. K. Khor, H. P. Sow, S. J. Ooi, H. Tan","doi":"10.1109/ECTC.2001.927718","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927718","url":null,"abstract":"Present methods of attaching solder balls to ball grid array (BGA) package is through placing flux and pre-formed solder ball to substrate followed by reflow process. In the ever-moving electronic market, low cost and faster units per hour processing provides competitive edge in the manufacturing technology. Screen ball printing (BP) to form BGA balls provides an innovative processing solution to overcome the costly conventional processing method. The key challenges to this project are to fulfill specified ball dimension and yields with a comparable quality and reliability performance to the current ball attach process. The challenge associated with a print and reflow process is the requirement to print very high amount of solder paste volume on each pad to achieve specified ball height after reflow. Yield loss due to this process are related to solder ball bridging and monster ball formation. Defects will be aggravated on tight pitch printing application. This paper will discuss some of the challenges and solution for this technology.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128816871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927756
P. Mccluskey
Many next generation electronic products will rely on programmable solid-state modules for controlling and distributing power. The use of solid-state electronic modules for power conversion and distribution has the potential to significantly improve the efficiency and performance of these power electronic products while reducing their cost. Critical to the success of power modules, however, is the development of mechanical packaging designs that will ensure reliable operation of the modules under harsh environmental and operational loading conditions. This paper proposes the development of a web-based graduate-level course on the Mechanical Design of High Temperature and High Power Electronics. Such a course would provide students with the necessary background to address the critical reliability and packaging issues needed to realize the promise of modular solid-state power electronics. The course will contain teaching modules on the fundamental operation of power electronic devices (MOSFETs, IGBTs, GTOs, SCRs, Thyristors, and MCTs), the power vs. frequency tradeoffs, the effects of high temperature on power and small signal control device operation and reliability, the incorporation of devices into soft and hard switches, methods of thermal analysis, the need for novel thermal management solutions, fatigue and failure of attach materials, stress analysis in multi-layer structures, wirebond reliability issues, and the use of pressure-based packaging structures. In addition, this course can be modified to produce a short course for practicing engineering professionals and extended for delivery on the web to a wide variety of audiences.
{"title":"A web-based graduate course on the Mechanical Design of High Temperature and High Power Electronics","authors":"P. Mccluskey","doi":"10.1109/ECTC.2001.927756","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927756","url":null,"abstract":"Many next generation electronic products will rely on programmable solid-state modules for controlling and distributing power. The use of solid-state electronic modules for power conversion and distribution has the potential to significantly improve the efficiency and performance of these power electronic products while reducing their cost. Critical to the success of power modules, however, is the development of mechanical packaging designs that will ensure reliable operation of the modules under harsh environmental and operational loading conditions. This paper proposes the development of a web-based graduate-level course on the Mechanical Design of High Temperature and High Power Electronics. Such a course would provide students with the necessary background to address the critical reliability and packaging issues needed to realize the promise of modular solid-state power electronics. The course will contain teaching modules on the fundamental operation of power electronic devices (MOSFETs, IGBTs, GTOs, SCRs, Thyristors, and MCTs), the power vs. frequency tradeoffs, the effects of high temperature on power and small signal control device operation and reliability, the incorporation of devices into soft and hard switches, methods of thermal analysis, the need for novel thermal management solutions, fatigue and failure of attach materials, stress analysis in multi-layer structures, wirebond reliability issues, and the use of pressure-based packaging structures. In addition, this course can be modified to produce a short course for practicing engineering professionals and extended for delivery on the web to a wide variety of audiences.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928001
A. T. Cheung, Yijin Xu
Encapsulants and underfills are polymeric materials containing some levels of low molecular mass chemicals which turn into volatiles during heat exposure. It is of interest to know what and when the volatiles undergo thermal desorption and are released during high temperature exposure such as solder reflow or environmental testing. Moisture turning to steam is not the only vapor present during solder reflow. With the push towards lead-free and higher reflow temperatures, this outgassing behavior is of particular significance to assist in the improvement of manufacturing yields. Using evolved gas analysis with gas chromatography and mass spectrometry, vapors found from epoxy mold compounds are carbon dioxide, moisture, methyl alcohol, benzene, isobutyl methyl ketone, triphenyl phosphine and occasionally, siloxanes from stress releasing agents. Gases reflecting curing byproducts or unreacted products are observed. For underfills, these gases are either absent or much reduced. Both underfills and encapsulants show some signs of polymer chain decomposition at higher temperatures for lead-free applications. Gas evolution rate increased directly with temperature for both encapsulants and underfills.
{"title":"Gases evolved during cure and solder reflow of encapsulants and underfills","authors":"A. T. Cheung, Yijin Xu","doi":"10.1109/ECTC.2001.928001","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928001","url":null,"abstract":"Encapsulants and underfills are polymeric materials containing some levels of low molecular mass chemicals which turn into volatiles during heat exposure. It is of interest to know what and when the volatiles undergo thermal desorption and are released during high temperature exposure such as solder reflow or environmental testing. Moisture turning to steam is not the only vapor present during solder reflow. With the push towards lead-free and higher reflow temperatures, this outgassing behavior is of particular significance to assist in the improvement of manufacturing yields. Using evolved gas analysis with gas chromatography and mass spectrometry, vapors found from epoxy mold compounds are carbon dioxide, moisture, methyl alcohol, benzene, isobutyl methyl ketone, triphenyl phosphine and occasionally, siloxanes from stress releasing agents. Gases reflecting curing byproducts or unreacted products are observed. For underfills, these gases are either absent or much reduced. Both underfills and encapsulants show some signs of polymer chain decomposition at higher temperatures for lead-free applications. Gas evolution rate increased directly with temperature for both encapsulants and underfills.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114482630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927858
A. Shigetou, N. Hosoda, T. Itoh, T. Suga
As the trend of microelectronic systems moves toward higher performance and speed, ultra-high density interconnection technology must be developed. To satisfy this requirement, a new concept called bumpless interconnection for next generation of packaging is proposed, which might bridge to global interconnection on chip. This technology will be most suitable and inevitable for ultra-high density interconnection when pad and pitch sizes are reduced to a few micrometers. Also the combination of a thin chip and a flexible substrate will be required for such interconnection since pads in the size of micrometers can not cope with the thermal stress in the bonding process. The surface activated bonding (SAB) method enables direct bonding at room-temperature. Thereby the SAB method is considered to be a most appropriate method for bumpless interconnection. Another requirement for bumpless interconnection is the bonding between Cu thin films because Cu is the most promising conductive material. Since SAB method requires no heat, large initial contact area must be maintained to obtain enough interconnection, For the purpose, the surface of Cu thin film must be highly flattened, for example, by Cu process. In this paper, a few fundamental experiments and preliminary results of investigations on the feasibility of CMP-Cu direct bonding at room temperature for bumpless interconnection are presented.
{"title":"Room-temperature direct bonding of CMP-Cu film for bumpless interconnection","authors":"A. Shigetou, N. Hosoda, T. Itoh, T. Suga","doi":"10.1109/ECTC.2001.927858","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927858","url":null,"abstract":"As the trend of microelectronic systems moves toward higher performance and speed, ultra-high density interconnection technology must be developed. To satisfy this requirement, a new concept called bumpless interconnection for next generation of packaging is proposed, which might bridge to global interconnection on chip. This technology will be most suitable and inevitable for ultra-high density interconnection when pad and pitch sizes are reduced to a few micrometers. Also the combination of a thin chip and a flexible substrate will be required for such interconnection since pads in the size of micrometers can not cope with the thermal stress in the bonding process. The surface activated bonding (SAB) method enables direct bonding at room-temperature. Thereby the SAB method is considered to be a most appropriate method for bumpless interconnection. Another requirement for bumpless interconnection is the bonding between Cu thin films because Cu is the most promising conductive material. Since SAB method requires no heat, large initial contact area must be maintained to obtain enough interconnection, For the purpose, the surface of Cu thin film must be highly flattened, for example, by Cu process. In this paper, a few fundamental experiments and preliminary results of investigations on the feasibility of CMP-Cu direct bonding at room temperature for bumpless interconnection are presented.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114926390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927744
N.A. Bushyager, M. Tentzeris
The modeling of MEMS structures using MRTD is presented. Many complex RF structures have been inadequately studied due to limitations in simulation methods. The space and time adaptive grid, as well as the ability to handle intracell feature variations, makes MRTD an ideal method for modeling these structures. MRTD is shown to be able to handle the complex structures found in modern wireless and microwave communication systems efficiently and accurately. Specifically, micromachined structures such as MEMS are treated.
{"title":"Modeling and design of RF MEMS structures using computationally efficient numerical techniques","authors":"N.A. Bushyager, M. Tentzeris","doi":"10.1109/ECTC.2001.927744","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927744","url":null,"abstract":"The modeling of MEMS structures using MRTD is presented. Many complex RF structures have been inadequately studied due to limitations in simulation methods. The space and time adaptive grid, as well as the ability to handle intracell feature variations, makes MRTD an ideal method for modeling these structures. MRTD is shown to be able to handle the complex structures found in modern wireless and microwave communication systems efficiently and accurately. Specifically, micromachined structures such as MEMS are treated.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116361854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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