Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927794
C. Liu, G.Q. Zhang, L. Ernst, M. Vervoort, G. Wisse
Interface delamination failure caused by thermomechanical loading and mismatch of thermal expansion coefficients is one of the important failure modes occurring in electronic packages, thus a threat for package reliability. To solve this problem, both academic institutions and industry have been spending tremendous research effort in order to understand the inherent failure mechanisms and to develop advanced and reliable experimental and simulation methodologies, thus to be able to predict and to avoid interface delamination before physical prototyping. Various damage mechanisms can be involved and can result into interface delamination phenomena. These are not all sufficiently addressed and/or reported so far, probably because of the complexities caused by the occurrence of strong geometric- and material nonlinearities. One of the phenomena being insufficiently understood so far is the so-called buckling driven delamination of thin metallic layers on ceramic substrates. This phenomena is discussed in the present paper.
{"title":"Buckling driven interface delamination between a thin metal layer and a ceramic substrate","authors":"C. Liu, G.Q. Zhang, L. Ernst, M. Vervoort, G. Wisse","doi":"10.1109/ECTC.2001.927794","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927794","url":null,"abstract":"Interface delamination failure caused by thermomechanical loading and mismatch of thermal expansion coefficients is one of the important failure modes occurring in electronic packages, thus a threat for package reliability. To solve this problem, both academic institutions and industry have been spending tremendous research effort in order to understand the inherent failure mechanisms and to develop advanced and reliable experimental and simulation methodologies, thus to be able to predict and to avoid interface delamination before physical prototyping. Various damage mechanisms can be involved and can result into interface delamination phenomena. These are not all sufficiently addressed and/or reported so far, probably because of the complexities caused by the occurrence of strong geometric- and material nonlinearities. One of the phenomena being insufficiently understood so far is the so-called buckling driven delamination of thin metallic layers on ceramic substrates. This phenomena is discussed in the present paper.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129605970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927707
Junwoo Lee, Baekkyu Choi, Seungyoung Ahn, Woonghwan Ryu, Jae Myun Kim, K. Choi, J. Hong, H. Chun, Joungho Kim
A wafer level package (WLP) has been developed as a cost effective packaging method compared to the /spl mu/BGA package, and especially applied to the Rambus DRAM (RDRAM) package. The maximum allowable thickness of the stress buffer layer on the WLP is limited to about 20 /spl mu/m, due to the limitation of the present spin coating process technology. Hence, the thickness of the stress buffer layer is much smaller than that of the elastomer (175 pm) used as a dielectric layer in the /spl mu/BGA package. Consequently, due to this extremely small distance between the metal traces on the WLP and the silicon substrate, the capacitive loading of the WLP on the RIMM (Rambus in-line memory module) is significantly increased. The increased capacitive loading by the WLP results in a decrease in the effective line impedance and an increase in the propagation delay on the RIMM, while the target line impedance on the RIMM is 28 /spl Omega//spl plusmn/10%. Therefore, careful design considerations are required at the package design level and at the module design level, to compensate for the increased capacitive loading by the WLP. In this paper, we firstly introduce the equivalent circuit model of the WLP interconnection lines using the S-parameter measurement in the microwave frequency region up to 5 GHz. Then, we suggest the electrical design methodology of the WLP and the module to compensate for the increased loading capacitance of the WLP.
{"title":"Microwave frequency model of wafer level package and increased loading effect on Rambus memory module","authors":"Junwoo Lee, Baekkyu Choi, Seungyoung Ahn, Woonghwan Ryu, Jae Myun Kim, K. Choi, J. Hong, H. Chun, Joungho Kim","doi":"10.1109/ECTC.2001.927707","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927707","url":null,"abstract":"A wafer level package (WLP) has been developed as a cost effective packaging method compared to the /spl mu/BGA package, and especially applied to the Rambus DRAM (RDRAM) package. The maximum allowable thickness of the stress buffer layer on the WLP is limited to about 20 /spl mu/m, due to the limitation of the present spin coating process technology. Hence, the thickness of the stress buffer layer is much smaller than that of the elastomer (175 pm) used as a dielectric layer in the /spl mu/BGA package. Consequently, due to this extremely small distance between the metal traces on the WLP and the silicon substrate, the capacitive loading of the WLP on the RIMM (Rambus in-line memory module) is significantly increased. The increased capacitive loading by the WLP results in a decrease in the effective line impedance and an increase in the propagation delay on the RIMM, while the target line impedance on the RIMM is 28 /spl Omega//spl plusmn/10%. Therefore, careful design considerations are required at the package design level and at the module design level, to compensate for the increased capacitive loading by the WLP. In this paper, we firstly introduce the equivalent circuit model of the WLP interconnection lines using the S-parameter measurement in the microwave frequency region up to 5 GHz. Then, we suggest the electrical design methodology of the WLP and the module to compensate for the increased loading capacitance of the WLP.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115008913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927740
Beth Keser, E. R. Prack, T. Fang
Commercially available, photosensitive dielectrics for use as a bump encapsulation or "stress compensation layer" (SCL) for wafer level chip-scale packaging (WL-CSP) were evaluated. Four materials were identified as potential SCL's. Filled and unfilled photosensitive materials were evaluated. To be successful as a SCL in WL-CSP, the commercially available material must be at least 125 /spl mu/m thick, be photosensitive, have 1:1 via and saw street resolution, have a total process time of less than 4 hours, have a cure process that does not effect the under-bump metallurgy, adhere to underlying passivation, and have a radius of curvature greater than 1.25 m. One commercially available unfilled photosensitive material had a glass transition temperature of 285/spl deg/C, a CTE of 55 ppm//spl deg/C, and a E of 2.5 Gpa. Since the company supplying this material had significant experience in thick, photosensitive film development and processing, they had excellent potential as a partner for evaluation. Another unfilled, photosensitive material supplied for this study had a glass transition temperature of 330/spl deg/C, a CTE of 80 ppm//spl deg/C, and an elastic modulus of 1.0 GPa. A filled, photosensitive material evaluated had a glass transition temperature of 130-150/spl deg/C, a CTE of 45 ppm//spl deg/C, and an elongation at break of 2.5%. Of the four materials evaluated, all types of materials showed potential.
{"title":"Evaluation of commercially available, thick, photosensitive films as a stress compensation layer for wafer level packaging","authors":"Beth Keser, E. R. Prack, T. Fang","doi":"10.1109/ECTC.2001.927740","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927740","url":null,"abstract":"Commercially available, photosensitive dielectrics for use as a bump encapsulation or \"stress compensation layer\" (SCL) for wafer level chip-scale packaging (WL-CSP) were evaluated. Four materials were identified as potential SCL's. Filled and unfilled photosensitive materials were evaluated. To be successful as a SCL in WL-CSP, the commercially available material must be at least 125 /spl mu/m thick, be photosensitive, have 1:1 via and saw street resolution, have a total process time of less than 4 hours, have a cure process that does not effect the under-bump metallurgy, adhere to underlying passivation, and have a radius of curvature greater than 1.25 m. One commercially available unfilled photosensitive material had a glass transition temperature of 285/spl deg/C, a CTE of 55 ppm//spl deg/C, and a E of 2.5 Gpa. Since the company supplying this material had significant experience in thick, photosensitive film development and processing, they had excellent potential as a partner for evaluation. Another unfilled, photosensitive material supplied for this study had a glass transition temperature of 330/spl deg/C, a CTE of 80 ppm//spl deg/C, and an elastic modulus of 1.0 GPa. A filled, photosensitive material evaluated had a glass transition temperature of 130-150/spl deg/C, a CTE of 45 ppm//spl deg/C, and an elongation at break of 2.5%. Of the four materials evaluated, all types of materials showed potential.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115146179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927712
P. Morganelli, B. Wheelock
There is much interest in understanding viscosity changes of a no-flow underfill during reflow. Viscosity changes that result from the onset of cure provide resistance to the formation of solder interconnections, and can result in a decrease in yield. The difficulty has been tracking viscosity changes during temperature profiles that vary as much as 4 degrees/second. We used microdielectrometry to make real-time ion viscosity measurements of various no-flow underfill formulations during a standard reflow temperature profile. The results clearly show the initial viscosity drop as temperature ramps up, and the point at which the effect of cure dominates and causes viscosity to rise. The data are related to DSC analysis and to solder joint yield. Overall, the results show how viscosity changes during the reflow process can potentially have a dramatic effect on assembly yield rates. The information gained is useful for developing a reflow process to form reliable solder joints.
{"title":"Viscosity of a no-flow underfill during reflow and its relationship to solder wetting","authors":"P. Morganelli, B. Wheelock","doi":"10.1109/ECTC.2001.927712","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927712","url":null,"abstract":"There is much interest in understanding viscosity changes of a no-flow underfill during reflow. Viscosity changes that result from the onset of cure provide resistance to the formation of solder interconnections, and can result in a decrease in yield. The difficulty has been tracking viscosity changes during temperature profiles that vary as much as 4 degrees/second. We used microdielectrometry to make real-time ion viscosity measurements of various no-flow underfill formulations during a standard reflow temperature profile. The results clearly show the initial viscosity drop as temperature ramps up, and the point at which the effect of cure dominates and causes viscosity to rise. The data are related to DSC analysis and to solder joint yield. Overall, the results show how viscosity changes during the reflow process can potentially have a dramatic effect on assembly yield rates. The information gained is useful for developing a reflow process to form reliable solder joints.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134054264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927713
K. Moon, L. Fan, C. Wong
Fillet cracking of no-flow underfill in flip-chip device during reliability test such as thermal shock or thermal cycling has been a serious reliability problem. The effect of toughening agents and modification of epoxy on fillet cracking of no-flow underfill was investigated. The base epoxy formulation and the appropriate loading level of toughening agent were found regarding the anti-fillet cracking performance. In case where the epoxy was modified with polysiloxanes, the 2nd phase with fine particle size was formed and the size of the particle depended on the toughening agent. The morphology was observed by scanning electron microscopy (SEM) and confirmed by dynamic mechanical measurement (DMA) measurement. The physical properties such as the fracture toughness, flexural modulus, coefficient of thermal expansion (CTE), and adhesion were measured and the liquid-liquid thermal shock (LLTS) test under -55-125/spl deg/C were performed with different formulations. One of the formulations toughened by amine/epoxy terminated polysiloxane, which has higher die shear strength, lower modulus, and higher toughness, passed 1000 cycles of the LLTS test. As such, in order to obtain high reliable no-flow underfill, the physical properties of the no-flow underfill should be well controlled and balanced. Finally correlation between physical properties of no-flow underfill and anti-fillet cracking capability for those approaches was discussed.
{"title":"Study on the effect of toughening of no-flow underfill on fillet cracking","authors":"K. Moon, L. Fan, C. Wong","doi":"10.1109/ECTC.2001.927713","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927713","url":null,"abstract":"Fillet cracking of no-flow underfill in flip-chip device during reliability test such as thermal shock or thermal cycling has been a serious reliability problem. The effect of toughening agents and modification of epoxy on fillet cracking of no-flow underfill was investigated. The base epoxy formulation and the appropriate loading level of toughening agent were found regarding the anti-fillet cracking performance. In case where the epoxy was modified with polysiloxanes, the 2nd phase with fine particle size was formed and the size of the particle depended on the toughening agent. The morphology was observed by scanning electron microscopy (SEM) and confirmed by dynamic mechanical measurement (DMA) measurement. The physical properties such as the fracture toughness, flexural modulus, coefficient of thermal expansion (CTE), and adhesion were measured and the liquid-liquid thermal shock (LLTS) test under -55-125/spl deg/C were performed with different formulations. One of the formulations toughened by amine/epoxy terminated polysiloxane, which has higher die shear strength, lower modulus, and higher toughness, passed 1000 cycles of the LLTS test. As such, in order to obtain high reliable no-flow underfill, the physical properties of the no-flow underfill should be well controlled and balanced. Finally correlation between physical properties of no-flow underfill and anti-fillet cracking capability for those approaches was discussed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132980467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927983
Chul-Won Ju, Seong-Su Park, S. Kim, Kyu-Ha Pack, H. Lee, Min-Kyu Song
In this paper, we present the effect of plasma descum by O/sub 2//C/sub 2/F/sub 6/ gas mixture on the via formation of photosensitive BCB layer and compare it with that of RF cleaning. Test vehicle was fabricated on Si wafer with Cu/photosensitive BCB layer structure and ECR-CVD system was used to descum the via. Residues at via bottom after the descum process were investigated by AES (auger electron microscope) and SEM (scanning electron microscope). It is shown in this work that O/sub 2//C/sub 2/F/sub 6/ plasma etching and the RF cleaning are effective for organic C, native C respectively, therefore the via descum by a combination of plasma etching with O/sub 2//C/sub 2/F/sub 6/ gas mixture and RF cleaning can efficiently remove the via residues.
{"title":"Effects of O/sub 2//C/sub 2/F/sub 6/ plasma descum with RF cleaning on via formation in MCM-D substrate using photosensitive BCB","authors":"Chul-Won Ju, Seong-Su Park, S. Kim, Kyu-Ha Pack, H. Lee, Min-Kyu Song","doi":"10.1109/ECTC.2001.927983","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927983","url":null,"abstract":"In this paper, we present the effect of plasma descum by O/sub 2//C/sub 2/F/sub 6/ gas mixture on the via formation of photosensitive BCB layer and compare it with that of RF cleaning. Test vehicle was fabricated on Si wafer with Cu/photosensitive BCB layer structure and ECR-CVD system was used to descum the via. Residues at via bottom after the descum process were investigated by AES (auger electron microscope) and SEM (scanning electron microscope). It is shown in this work that O/sub 2//C/sub 2/F/sub 6/ plasma etching and the RF cleaning are effective for organic C, native C respectively, therefore the via descum by a combination of plasma etching with O/sub 2//C/sub 2/F/sub 6/ gas mixture and RF cleaning can efficiently remove the via residues.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132440574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927743
L. R. Sloan, C. Sullivan, C. Tigges, C. Sandoval, D. Palmer, S. Hietala, T. Christenson, C. Dyck, T. A. Plut, G. R. Schuster
The application need for and specification of RF micro-electro-mechanical (MEM) switches are discussed. The design, low temperature processing, and RF characteristics of a coplanar waveguide MEMs switch are presented. This switch can be integrated onto previously fabricated MMICs or transistor chips. These switches demonstrate 0.2 dB loss while in the "on" state (closed), need approximately 10 volts to operate, and can carry more than 200 mW RF.
{"title":"RF micromechanical switches that can be post processed on commercial MMICs","authors":"L. R. Sloan, C. Sullivan, C. Tigges, C. Sandoval, D. Palmer, S. Hietala, T. Christenson, C. Dyck, T. A. Plut, G. R. Schuster","doi":"10.1109/ECTC.2001.927743","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927743","url":null,"abstract":"The application need for and specification of RF micro-electro-mechanical (MEM) switches are discussed. The design, low temperature processing, and RF characteristics of a coplanar waveguide MEMs switch are presented. This switch can be integrated onto previously fabricated MMICs or transistor chips. These switches demonstrate 0.2 dB loss while in the \"on\" state (closed), need approximately 10 volts to operate, and can carry more than 200 mW RF.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125162298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927911
T. Wang, F. Tung, L. Foo, V. Dutta
Pillar bump is a novel interconnect structure, including non-reflowable base and a reflowable cap like a pillar shape. In this study, pillar bump with copper base and Sn63/Pb37 eutectic solder cap is processed via electrolytic plating. Based on whether flat eutectic cap is reflowed prior to assembly, pillar bump is further split into two categories, namely pre-reflowed and non-reflowed, respectively. Assembly feasibility assessment as well as bump integrity evaluation are carried out. Bump shear test is conducted for both before and after reliability and failure mode is characterized via SEM and EDX. Furthermore, a 10 mm/spl times/10 mm test chip having 180 Cu/eutectic solder pillar bumps with 0.2 mm pitch is assembled onto BT substrate via no clean flux and subsequently underfilled. The results show that pillar shape is still maintained after assembly that can meet fine pitch requirement. No shear strength deterioration after moisture sensitivity preconditioning and 1000 thermal cycle test (TCT, -40/spl deg/C/spl sim/125/spl deg/C) has been observed. EDX spectra indicate fracture has occurred in the interfacial region between Al and silicon, not arising from bumping process. Furthermore, bump integrity is intact after package level reliability test under the same conditions as above. Stress simulation results lead to conclusion that maximum shear stress occurs in copper pillar portion with average range of 40/spl sim/50 MPa that is much below the shear strength of copper.
{"title":"Studies on a novel flip-chip interconnect structure. Pillar bump","authors":"T. Wang, F. Tung, L. Foo, V. Dutta","doi":"10.1109/ECTC.2001.927911","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927911","url":null,"abstract":"Pillar bump is a novel interconnect structure, including non-reflowable base and a reflowable cap like a pillar shape. In this study, pillar bump with copper base and Sn63/Pb37 eutectic solder cap is processed via electrolytic plating. Based on whether flat eutectic cap is reflowed prior to assembly, pillar bump is further split into two categories, namely pre-reflowed and non-reflowed, respectively. Assembly feasibility assessment as well as bump integrity evaluation are carried out. Bump shear test is conducted for both before and after reliability and failure mode is characterized via SEM and EDX. Furthermore, a 10 mm/spl times/10 mm test chip having 180 Cu/eutectic solder pillar bumps with 0.2 mm pitch is assembled onto BT substrate via no clean flux and subsequently underfilled. The results show that pillar shape is still maintained after assembly that can meet fine pitch requirement. No shear strength deterioration after moisture sensitivity preconditioning and 1000 thermal cycle test (TCT, -40/spl deg/C/spl sim/125/spl deg/C) has been observed. EDX spectra indicate fracture has occurred in the interfacial region between Al and silicon, not arising from bumping process. Furthermore, bump integrity is intact after package level reliability test under the same conditions as above. Stress simulation results lead to conclusion that maximum shear stress occurs in copper pillar portion with average range of 40/spl sim/50 MPa that is much below the shear strength of copper.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927708
Woonghwan Ryu, A. Wai, Fan Wei, Wai Lai Lai, Joungho Kim
Conventional digital clock distribution interconnection causes a severe power consumption problem for GHz clock distribution because of transmission line losses, and it exhibits difficult signal integrity problems due to clock skew, clock jitter and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, especially multi-processor systems using global clocking. In this paper, we firstly report signal integrity analysis including power, skew, jitter, crosstalk, reflection, and noise in the RF clock distribution system. Based on this analysis, we propose a novel signal integrity design methodology for the RF clock distribution. The system comprises an RF clock transmitter as a clock generator, an H clock tree with junction couplers as a clock distributing network and an RF receiver as a digital clock-recovering module. We assume solder-ball flip chip interconnects for the chip-to-substrate assembly and 0.35 /spl mu/m TSMC CMOS technology for the RF clock receiver. The clock skew and the clock jitter created by process parameter variations or modeled and predicted. Finally, we demonstrate the RCD as a low-power and high-performance clocking method using HP Advanced Design System (ADS) simulation considering the microwave frequency interconnection models and the process parameter variations.
{"title":"Over GHz low-power RF clock distribution for a multiprocessor digital system","authors":"Woonghwan Ryu, A. Wai, Fan Wei, Wai Lai Lai, Joungho Kim","doi":"10.1109/ECTC.2001.927708","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927708","url":null,"abstract":"Conventional digital clock distribution interconnection causes a severe power consumption problem for GHz clock distribution because of transmission line losses, and it exhibits difficult signal integrity problems due to clock skew, clock jitter and signal reflection. To overcome these conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, especially multi-processor systems using global clocking. In this paper, we firstly report signal integrity analysis including power, skew, jitter, crosstalk, reflection, and noise in the RF clock distribution system. Based on this analysis, we propose a novel signal integrity design methodology for the RF clock distribution. The system comprises an RF clock transmitter as a clock generator, an H clock tree with junction couplers as a clock distributing network and an RF receiver as a digital clock-recovering module. We assume solder-ball flip chip interconnects for the chip-to-substrate assembly and 0.35 /spl mu/m TSMC CMOS technology for the RF clock receiver. The clock skew and the clock jitter created by process parameter variations or modeled and predicted. Finally, we demonstrate the RCD as a low-power and high-performance clocking method using HP Advanced Design System (ADS) simulation considering the microwave frequency interconnection models and the process parameter variations.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128799816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927735
Yuan Li, J. Xie, T. Verma, V. Wang
A family of 1.0-mm pitch full-array flip-chip BGAs were developed. These packages vary from 27 to 45 mm in package size, 15 to 25 mm in die size, and 672 to 1020 in ball count. With dies and packages so large, solder joint fatigue failure and underfill delamination, induced by thermal expansion mismatch, are a major concern. Finite element analysis was set up for efficient reliability analysis. Two substrates, hi-CTE ceramic (12/spl times/10/sup -6///spl deg/C) and BT (17/spl times/10/sup -6///spl deg/C), are compared. Hi-CTE ceramic substrate has a better CTE match with die (2.6/spl times/10/sup -6///spl deg/C), therefore, it was surmised that hi-CTE ceramic would improve component-level reliability yet with satisfactory board-level reliability. To validate it, several die and package combinations were modeled using both substrates. Both component-level stresses and board-level solder joint fatigue life were compared. In addition, design of experiment (DOE) was used to study the effect of properties and dimensions of underfill and heat spreader on solder joint fatigue life. The effect of pad opening size was also quantified. Finally, the effect of underfill on interface stress between underfill and die was investigated.
{"title":"Reliability study of high-pin-count flip-chip BGA","authors":"Yuan Li, J. Xie, T. Verma, V. Wang","doi":"10.1109/ECTC.2001.927735","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927735","url":null,"abstract":"A family of 1.0-mm pitch full-array flip-chip BGAs were developed. These packages vary from 27 to 45 mm in package size, 15 to 25 mm in die size, and 672 to 1020 in ball count. With dies and packages so large, solder joint fatigue failure and underfill delamination, induced by thermal expansion mismatch, are a major concern. Finite element analysis was set up for efficient reliability analysis. Two substrates, hi-CTE ceramic (12/spl times/10/sup -6///spl deg/C) and BT (17/spl times/10/sup -6///spl deg/C), are compared. Hi-CTE ceramic substrate has a better CTE match with die (2.6/spl times/10/sup -6///spl deg/C), therefore, it was surmised that hi-CTE ceramic would improve component-level reliability yet with satisfactory board-level reliability. To validate it, several die and package combinations were modeled using both substrates. Both component-level stresses and board-level solder joint fatigue life were compared. In addition, design of experiment (DOE) was used to study the effect of properties and dimensions of underfill and heat spreader on solder joint fatigue life. The effect of pad opening size was also quantified. Finally, the effect of underfill on interface stress between underfill and die was investigated.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129177055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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