Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927770
Ka Yau Lee, Ming Li, D. Olsen, W.T. Chen, B.T.C. Tan, S. Mhaisalkar
The microstructure, joint strength and failure mechanisms of Sn-Ag and Sn-Ag-Cu versus Sn-Pb-Ag systems on Cu/Ni/Au BGA pad metallization have been investigated after multiple reflow and high temperature storage. Sn-Pb-Ag system gave rise to a two-layer structure, i.e. Ni/sub 3/Sn/sub 4/ and (Au,Ni)Sn/sub 4/, at the interface after aging at 150/spl deg/C. However, such a structure was not detected in both lead-free systems. Only a layer of Ni/sub 3/Sn/sub 4/ phase in the Sn-Ag system and a layer of Cu-Sn-Ni-Au intermetallic compound in Sn-Ag-Cu system were found at the interfaces, even after 1000 hours at the afore-mentioned temperature. The formation of the (Au,Ni)Sn/sub 4/ ternary compound was due to re-settlement of Au at the interface which led to severe brittle failure in the Sn-Pb-Ag system. In contrast, Sn-Ag and Sn-Ag-Cu systems failed exclusively inside the solder after aging at 150/spl deg/C up to 1000 hours. The solder ball joint strength of the three systems and failure modes were also evaluated. Both lead-free systems showed good resistance to thermal aging with a solder ball joint strength maintained at about 1.60 to 1.70 kgf. The Sn-Pb-Ag system, on the other hand, degraded in mechanical performance over aging time, reaching a strength as low as 1.20 kgf. The growth rates of intermetallic layers at 125, 150, and 175/spl deg/C, and the activation energy were also determined in this study.
{"title":"Microstructure, joint strength and failure mechanism of Sn-Ag, Sn-Ag-Cu versus Sn-Pb-Ag solders in BGA packages","authors":"Ka Yau Lee, Ming Li, D. Olsen, W.T. Chen, B.T.C. Tan, S. Mhaisalkar","doi":"10.1109/ECTC.2001.927770","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927770","url":null,"abstract":"The microstructure, joint strength and failure mechanisms of Sn-Ag and Sn-Ag-Cu versus Sn-Pb-Ag systems on Cu/Ni/Au BGA pad metallization have been investigated after multiple reflow and high temperature storage. Sn-Pb-Ag system gave rise to a two-layer structure, i.e. Ni/sub 3/Sn/sub 4/ and (Au,Ni)Sn/sub 4/, at the interface after aging at 150/spl deg/C. However, such a structure was not detected in both lead-free systems. Only a layer of Ni/sub 3/Sn/sub 4/ phase in the Sn-Ag system and a layer of Cu-Sn-Ni-Au intermetallic compound in Sn-Ag-Cu system were found at the interfaces, even after 1000 hours at the afore-mentioned temperature. The formation of the (Au,Ni)Sn/sub 4/ ternary compound was due to re-settlement of Au at the interface which led to severe brittle failure in the Sn-Pb-Ag system. In contrast, Sn-Ag and Sn-Ag-Cu systems failed exclusively inside the solder after aging at 150/spl deg/C up to 1000 hours. The solder ball joint strength of the three systems and failure modes were also evaluated. Both lead-free systems showed good resistance to thermal aging with a solder ball joint strength maintained at about 1.60 to 1.70 kgf. The Sn-Pb-Ag system, on the other hand, degraded in mechanical performance over aging time, reaching a strength as low as 1.20 kgf. The growth rates of intermetallic layers at 125, 150, and 175/spl deg/C, and the activation energy were also determined in this study.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927665
M. Vrazel, Jae J. Chang, In-Dal Song, K. Chung, M. Brooke, N. Jokerst, A. Brown, D. Wills
The increasing demand for high bandwidth, low latency I/O in gigascale systems is challenging current packaging technology. Optoelectronic I/O offers needed performance, but presents new challenges in mixed signal (digital, analog, optical, RF) design and test. In addition, the integration of OE interconnect must be suitable for high volume, low cost manufacturing of digital systems. This paper explores the heterogeneous integration of very large area, highly alignment tolerant photodetectors onto Si CMOS differential analog receiver circuits to realize noise-tolerant receiver interfaces for high-density interconnection electrical substrates with integrated optical links as well as for fiber optic links. The realization of an optically interconnected microprocessor that employs such a photodetector will also be discussed.
{"title":"Highly alignment tolerant InGaAs inverted MSM photodetector heterogeneously integrated on a differential Si CMOS receiver operating at 1 Gbps","authors":"M. Vrazel, Jae J. Chang, In-Dal Song, K. Chung, M. Brooke, N. Jokerst, A. Brown, D. Wills","doi":"10.1109/ECTC.2001.927665","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927665","url":null,"abstract":"The increasing demand for high bandwidth, low latency I/O in gigascale systems is challenging current packaging technology. Optoelectronic I/O offers needed performance, but presents new challenges in mixed signal (digital, analog, optical, RF) design and test. In addition, the integration of OE interconnect must be suitable for high volume, low cost manufacturing of digital systems. This paper explores the heterogeneous integration of very large area, highly alignment tolerant photodetectors onto Si CMOS differential analog receiver circuits to realize noise-tolerant receiver interfaces for high-density interconnection electrical substrates with integrated optical links as well as for fiber optic links. The realization of an optically interconnected microprocessor that employs such a photodetector will also be discussed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928015
Byung-Seon Kong, Hyo-Chang Yun, Jong-Chan Lim, Y. Jung, Dong-Young Kim, Kwan-Seek Chung
In this study, four kind of epoxy resins (biphenyl, naphthol, multi-functional, and OCN type) have applied to molding compound for CABGA packages. Basic, thermal, and mechanical properties of all molding compounds were measured and compared with moldability (coplanarity and wire sweep) and reliability (moisture sensitivity level) in the CABGA packages. From factor study, it was clear that molding compound which had high Tg and low shrinkage represents low coplanarity of CABGA packages. Coplanarity of MAP-type CABGA package decreased with increasing Tg and decreasing shrinkage of molding compound. Especially, coplanarity of the said package was found to be linearly proportional to the difference of shrinkage between PCB substrate and molding compound at room temperature. In case of reliability, the amount of absorbed moisture and flexural modulus of molding compounds affected on moisture sensitivity level. Low moisture absorption and flexural modulus are profitable for high reliability-JEDEC Level 3, 30/spl deg/C/60%RH/192 hours at reflow temperature 260/spl deg/C.
{"title":"High reliable and environmental friendly molding compound for CABGA(R) packages","authors":"Byung-Seon Kong, Hyo-Chang Yun, Jong-Chan Lim, Y. Jung, Dong-Young Kim, Kwan-Seek Chung","doi":"10.1109/ECTC.2001.928015","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928015","url":null,"abstract":"In this study, four kind of epoxy resins (biphenyl, naphthol, multi-functional, and OCN type) have applied to molding compound for CABGA packages. Basic, thermal, and mechanical properties of all molding compounds were measured and compared with moldability (coplanarity and wire sweep) and reliability (moisture sensitivity level) in the CABGA packages. From factor study, it was clear that molding compound which had high Tg and low shrinkage represents low coplanarity of CABGA packages. Coplanarity of MAP-type CABGA package decreased with increasing Tg and decreasing shrinkage of molding compound. Especially, coplanarity of the said package was found to be linearly proportional to the difference of shrinkage between PCB substrate and molding compound at room temperature. In case of reliability, the amount of absorbed moisture and flexural modulus of molding compounds affected on moisture sensitivity level. Low moisture absorption and flexural modulus are profitable for high reliability-JEDEC Level 3, 30/spl deg/C/60%RH/192 hours at reflow temperature 260/spl deg/C.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927950
R. Coyle, G. Wenger, D. E. Hodges, A. Mawer, D. Cullen, P. Solan
Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of four variations of the ENIG surface finish. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.
{"title":"The effect of variations in nickel/gold surface finish on the assembly quality and attachment reliability of a plastic ball grid array","authors":"R. Coyle, G. Wenger, D. E. Hodges, A. Mawer, D. Cullen, P. Solan","doi":"10.1109/ECTC.2001.927950","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927950","url":null,"abstract":"Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of four variations of the ENIG surface finish. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927935
T. Suga, M. Howlader, T. Itoh, C. Inaka, Y. Arai, A. Yamauchi
A robot-controlled wafer bonding machine was developed for the bonding of different sizes of wafers ranging up to 8 inches diameter. The features of this equipment are such that: (1) After the automatic parallel adjustment for 8-inch wafers to a margin of error within /spl plusmn/1 /spl mu/m, the X, Y, and /spl theta/ axis alignments are performed, allowing a margin of error within /spl plusmn/0.5 /spl mu/m in bonding accuracy; and (2) Room-temperature bonding is enabled using the surface activated (SAB) bonding concept. 8-inch diameter silicon wafers ware successfully bonded by the SAB process at room temperature for the first time. Preliminary investigations across the interface using an Infrared camera show that no bubbles are visibly present in the bonding region.
{"title":"A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept","authors":"T. Suga, M. Howlader, T. Itoh, C. Inaka, Y. Arai, A. Yamauchi","doi":"10.1109/ECTC.2001.927935","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927935","url":null,"abstract":"A robot-controlled wafer bonding machine was developed for the bonding of different sizes of wafers ranging up to 8 inches diameter. The features of this equipment are such that: (1) After the automatic parallel adjustment for 8-inch wafers to a margin of error within /spl plusmn/1 /spl mu/m, the X, Y, and /spl theta/ axis alignments are performed, allowing a margin of error within /spl plusmn/0.5 /spl mu/m in bonding accuracy; and (2) Room-temperature bonding is enabled using the surface activated (SAB) bonding concept. 8-inch diameter silicon wafers ware successfully bonded by the SAB process at room temperature for the first time. Preliminary investigations across the interface using an Infrared camera show that no bubbles are visibly present in the bonding region.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927933
T. Suga, K. Otsuka
A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.
{"title":"Bump-less interconnect for next generation system packaging","authors":"T. Suga, K. Otsuka","doi":"10.1109/ECTC.2001.927933","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927933","url":null,"abstract":"A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928010
L. Sweatlock, D. Lischner, J. Weiss
A methodology for performing characterization of Plastic Ball Grid Array (PBGA) packages via Infrared Thermography (IRT) was established. The thermal performance of various assemblies was characterized using IRT in conjunction with analytical methods to determine the individual contributions of the PBGA package and of the printed wiring board. Accuracy and repeatability of temperature measurements via IRT were found to be equal to those obtained by thermocouple techniques using standard IEDEC methods. Additionally, IRT was found to provide significant advantages relative to conventional measurement techniques including increased resolution, space and time domain profiling capability, ease of use, and reduced sample preparation and measurement time.
{"title":"Thermal characterization of plastic ball grid array packages via infrared thermography","authors":"L. Sweatlock, D. Lischner, J. Weiss","doi":"10.1109/ECTC.2001.928010","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928010","url":null,"abstract":"A methodology for performing characterization of Plastic Ball Grid Array (PBGA) packages via Infrared Thermography (IRT) was established. The thermal performance of various assemblies was characterized using IRT in conjunction with analytical methods to determine the individual contributions of the PBGA package and of the printed wiring board. Accuracy and repeatability of temperature measurements via IRT were found to be equal to those obtained by thermocouple techniques using standard IEDEC methods. Additionally, IRT was found to provide significant advantages relative to conventional measurement techniques including increased resolution, space and time domain profiling capability, ease of use, and reduced sample preparation and measurement time.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124402046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927750
Delin Li, D. Light, D. Castillo, M. Beroz, M. Nguyen, T. Wang
During the later 1990's, Tessera introduced a semiconductor packaging technology called WAVE (Wide Area Vertical Expansion) package to address the growing need for high pin count, high speed, high thermal dissipation, and high environmental reliability in advanced electronic packaging. The WAVE technology is an extension of Tessera's compliant packaging technologies that places a low modulus encapsulant between the silicon die and the package substrate to solve their CTE mismatch problem. The WAVE technology allows for compliant vertical interconnection links to be formed between the ICs and the substrate, with no need for a bond window. These interconnections are made simultaneously, in contrast to single point wire or lead bonding. The compliant interconnections and low modulus encapsulant enable the stress on BGA solder balls to be minimized. The WAVE package utilizes advanced materials and design to provide a unique combination of high electrical and thermal performance, high environmental reliability, and cost effective IC interconnection methodology. This paper presents one of the latest WAVE technology developments at Tessera.
{"title":"A Wide Area Vertical Expansion (WAVE/sup TM/) packaging process development","authors":"Delin Li, D. Light, D. Castillo, M. Beroz, M. Nguyen, T. Wang","doi":"10.1109/ECTC.2001.927750","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927750","url":null,"abstract":"During the later 1990's, Tessera introduced a semiconductor packaging technology called WAVE (Wide Area Vertical Expansion) package to address the growing need for high pin count, high speed, high thermal dissipation, and high environmental reliability in advanced electronic packaging. The WAVE technology is an extension of Tessera's compliant packaging technologies that places a low modulus encapsulant between the silicon die and the package substrate to solve their CTE mismatch problem. The WAVE technology allows for compliant vertical interconnection links to be formed between the ICs and the substrate, with no need for a bond window. These interconnections are made simultaneously, in contrast to single point wire or lead bonding. The compliant interconnections and low modulus encapsulant enable the stress on BGA solder balls to be minimized. The WAVE package utilizes advanced materials and design to provide a unique combination of high electrical and thermal performance, high environmental reliability, and cost effective IC interconnection methodology. This paper presents one of the latest WAVE technology developments at Tessera.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124289426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927938
J. Karasawa, M. Segawa, Y. Kishimoto, M. Aoki, T. Sasaki
Small cameras used as image storage devices have been rapidly applied to mobile information devices since the improvement of picture quality and the development of an easy picture processing method. The authors have developed a small camera module (3.6 cc, 30(W)/spl times/15(D)/spl times/8(H) mm/sup 3/; including lens unit) using two bare chip bonding methods. One is the CMOS image sensor packaging technique for fabrication on a flexible substrate by the ACP (anisotropic conductive paste) bonding method. The other is the flip chip bonding method which utilizes the advanced ACP method for a DSP (digital signal processor) chip. The new ACP enables a short resin curing time of less than six seconds. The ACP can also withstand the reflow soldering process, so that the bare chip IC and chip components can be mounted on the same substrate. By using these bare chip bonding techniques, the small camera module was realized. Regarding the ACP, its humidity absorption property was improved to obtain a high reliability. The filler content of the ACP was also controlled to obtain a high reliability. The flip chip bonding margin was confirmed to be applicable to mass production.
{"title":"Flip chip interconnection method applied to small camera module","authors":"J. Karasawa, M. Segawa, Y. Kishimoto, M. Aoki, T. Sasaki","doi":"10.1109/ECTC.2001.927938","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927938","url":null,"abstract":"Small cameras used as image storage devices have been rapidly applied to mobile information devices since the improvement of picture quality and the development of an easy picture processing method. The authors have developed a small camera module (3.6 cc, 30(W)/spl times/15(D)/spl times/8(H) mm/sup 3/; including lens unit) using two bare chip bonding methods. One is the CMOS image sensor packaging technique for fabrication on a flexible substrate by the ACP (anisotropic conductive paste) bonding method. The other is the flip chip bonding method which utilizes the advanced ACP method for a DSP (digital signal processor) chip. The new ACP enables a short resin curing time of less than six seconds. The ACP can also withstand the reflow soldering process, so that the bare chip IC and chip components can be mounted on the same substrate. By using these bare chip bonding techniques, the small camera module was realized. Regarding the ACP, its humidity absorption property was improved to obtain a high reliability. The filler content of the ACP was also controlled to obtain a high reliability. The flip chip bonding margin was confirmed to be applicable to mass production.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134230842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927766
S.K. Kang, D. Shih, K. Fogel, P. Lauro, M. Yim, G. Advocate, M. Griffin, C. Goldsmith, D. W. Henderson, T. Gosselin, D. King, J. Konrad, A. Sarkhel, K. Puttlitz
Recently, the research and development activities for replacing Pb-containing solders with Pb-free solders have been intensified due to both competitive market pressures and environmental issues. As a result of these activities, a few promising candidate solder alloys have been identified, mainly, Sn-based alloys. A key issue affecting the integrity and reliability of solder joints is the interfacial reactions between a molten solder and surface finishes in the solder joint structures. In this paper, a fundamental study of the interfacial reactions between several Pb-free candidate solders and surface finishes commonly used in printed-circuit cards is reported. The Pb-free solders investigated include Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and Sn-3.5Ag-3.0Bi. The surface finishes investigated include Cu, Au/Ni(P), Au/Pd/Ni(P), and Au/Ni (electroplated). The reaction kinetics of the dissolution of surface finishes and intermetallic compound growth have been measured as a function of reflow temperature and time. The intermetallic compounds formed during reflow reactions have been identified by SEM with Energy Dispersive X-ray Spectroscopy.
{"title":"Interfacial reaction studies on lead (Pb)-free solder alloys","authors":"S.K. Kang, D. Shih, K. Fogel, P. Lauro, M. Yim, G. Advocate, M. Griffin, C. Goldsmith, D. W. Henderson, T. Gosselin, D. King, J. Konrad, A. Sarkhel, K. Puttlitz","doi":"10.1109/ECTC.2001.927766","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927766","url":null,"abstract":"Recently, the research and development activities for replacing Pb-containing solders with Pb-free solders have been intensified due to both competitive market pressures and environmental issues. As a result of these activities, a few promising candidate solder alloys have been identified, mainly, Sn-based alloys. A key issue affecting the integrity and reliability of solder joints is the interfacial reactions between a molten solder and surface finishes in the solder joint structures. In this paper, a fundamental study of the interfacial reactions between several Pb-free candidate solders and surface finishes commonly used in printed-circuit cards is reported. The Pb-free solders investigated include Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and Sn-3.5Ag-3.0Bi. The surface finishes investigated include Cu, Au/Ni(P), Au/Pd/Ni(P), and Au/Ni (electroplated). The reaction kinetics of the dissolution of surface finishes and intermetallic compound growth have been measured as a function of reflow temperature and time. The intermetallic compounds formed during reflow reactions have been identified by SEM with Energy Dispersive X-ray Spectroscopy.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134595380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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