Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927770
Ka Yau Lee, Ming Li, D. Olsen, W.T. Chen, B.T.C. Tan, S. Mhaisalkar
The microstructure, joint strength and failure mechanisms of Sn-Ag and Sn-Ag-Cu versus Sn-Pb-Ag systems on Cu/Ni/Au BGA pad metallization have been investigated after multiple reflow and high temperature storage. Sn-Pb-Ag system gave rise to a two-layer structure, i.e. Ni/sub 3/Sn/sub 4/ and (Au,Ni)Sn/sub 4/, at the interface after aging at 150/spl deg/C. However, such a structure was not detected in both lead-free systems. Only a layer of Ni/sub 3/Sn/sub 4/ phase in the Sn-Ag system and a layer of Cu-Sn-Ni-Au intermetallic compound in Sn-Ag-Cu system were found at the interfaces, even after 1000 hours at the afore-mentioned temperature. The formation of the (Au,Ni)Sn/sub 4/ ternary compound was due to re-settlement of Au at the interface which led to severe brittle failure in the Sn-Pb-Ag system. In contrast, Sn-Ag and Sn-Ag-Cu systems failed exclusively inside the solder after aging at 150/spl deg/C up to 1000 hours. The solder ball joint strength of the three systems and failure modes were also evaluated. Both lead-free systems showed good resistance to thermal aging with a solder ball joint strength maintained at about 1.60 to 1.70 kgf. The Sn-Pb-Ag system, on the other hand, degraded in mechanical performance over aging time, reaching a strength as low as 1.20 kgf. The growth rates of intermetallic layers at 125, 150, and 175/spl deg/C, and the activation energy were also determined in this study.
{"title":"Microstructure, joint strength and failure mechanism of Sn-Ag, Sn-Ag-Cu versus Sn-Pb-Ag solders in BGA packages","authors":"Ka Yau Lee, Ming Li, D. Olsen, W.T. Chen, B.T.C. Tan, S. Mhaisalkar","doi":"10.1109/ECTC.2001.927770","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927770","url":null,"abstract":"The microstructure, joint strength and failure mechanisms of Sn-Ag and Sn-Ag-Cu versus Sn-Pb-Ag systems on Cu/Ni/Au BGA pad metallization have been investigated after multiple reflow and high temperature storage. Sn-Pb-Ag system gave rise to a two-layer structure, i.e. Ni/sub 3/Sn/sub 4/ and (Au,Ni)Sn/sub 4/, at the interface after aging at 150/spl deg/C. However, such a structure was not detected in both lead-free systems. Only a layer of Ni/sub 3/Sn/sub 4/ phase in the Sn-Ag system and a layer of Cu-Sn-Ni-Au intermetallic compound in Sn-Ag-Cu system were found at the interfaces, even after 1000 hours at the afore-mentioned temperature. The formation of the (Au,Ni)Sn/sub 4/ ternary compound was due to re-settlement of Au at the interface which led to severe brittle failure in the Sn-Pb-Ag system. In contrast, Sn-Ag and Sn-Ag-Cu systems failed exclusively inside the solder after aging at 150/spl deg/C up to 1000 hours. The solder ball joint strength of the three systems and failure modes were also evaluated. Both lead-free systems showed good resistance to thermal aging with a solder ball joint strength maintained at about 1.60 to 1.70 kgf. The Sn-Pb-Ag system, on the other hand, degraded in mechanical performance over aging time, reaching a strength as low as 1.20 kgf. The growth rates of intermetallic layers at 125, 150, and 175/spl deg/C, and the activation energy were also determined in this study.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927665
M. Vrazel, Jae J. Chang, In-Dal Song, K. Chung, M. Brooke, N. Jokerst, A. Brown, D. Wills
The increasing demand for high bandwidth, low latency I/O in gigascale systems is challenging current packaging technology. Optoelectronic I/O offers needed performance, but presents new challenges in mixed signal (digital, analog, optical, RF) design and test. In addition, the integration of OE interconnect must be suitable for high volume, low cost manufacturing of digital systems. This paper explores the heterogeneous integration of very large area, highly alignment tolerant photodetectors onto Si CMOS differential analog receiver circuits to realize noise-tolerant receiver interfaces for high-density interconnection electrical substrates with integrated optical links as well as for fiber optic links. The realization of an optically interconnected microprocessor that employs such a photodetector will also be discussed.
{"title":"Highly alignment tolerant InGaAs inverted MSM photodetector heterogeneously integrated on a differential Si CMOS receiver operating at 1 Gbps","authors":"M. Vrazel, Jae J. Chang, In-Dal Song, K. Chung, M. Brooke, N. Jokerst, A. Brown, D. Wills","doi":"10.1109/ECTC.2001.927665","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927665","url":null,"abstract":"The increasing demand for high bandwidth, low latency I/O in gigascale systems is challenging current packaging technology. Optoelectronic I/O offers needed performance, but presents new challenges in mixed signal (digital, analog, optical, RF) design and test. In addition, the integration of OE interconnect must be suitable for high volume, low cost manufacturing of digital systems. This paper explores the heterogeneous integration of very large area, highly alignment tolerant photodetectors onto Si CMOS differential analog receiver circuits to realize noise-tolerant receiver interfaces for high-density interconnection electrical substrates with integrated optical links as well as for fiber optic links. The realization of an optically interconnected microprocessor that employs such a photodetector will also be discussed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928015
Byung-Seon Kong, Hyo-Chang Yun, Jong-Chan Lim, Y. Jung, Dong-Young Kim, Kwan-Seek Chung
In this study, four kind of epoxy resins (biphenyl, naphthol, multi-functional, and OCN type) have applied to molding compound for CABGA packages. Basic, thermal, and mechanical properties of all molding compounds were measured and compared with moldability (coplanarity and wire sweep) and reliability (moisture sensitivity level) in the CABGA packages. From factor study, it was clear that molding compound which had high Tg and low shrinkage represents low coplanarity of CABGA packages. Coplanarity of MAP-type CABGA package decreased with increasing Tg and decreasing shrinkage of molding compound. Especially, coplanarity of the said package was found to be linearly proportional to the difference of shrinkage between PCB substrate and molding compound at room temperature. In case of reliability, the amount of absorbed moisture and flexural modulus of molding compounds affected on moisture sensitivity level. Low moisture absorption and flexural modulus are profitable for high reliability-JEDEC Level 3, 30/spl deg/C/60%RH/192 hours at reflow temperature 260/spl deg/C.
{"title":"High reliable and environmental friendly molding compound for CABGA(R) packages","authors":"Byung-Seon Kong, Hyo-Chang Yun, Jong-Chan Lim, Y. Jung, Dong-Young Kim, Kwan-Seek Chung","doi":"10.1109/ECTC.2001.928015","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928015","url":null,"abstract":"In this study, four kind of epoxy resins (biphenyl, naphthol, multi-functional, and OCN type) have applied to molding compound for CABGA packages. Basic, thermal, and mechanical properties of all molding compounds were measured and compared with moldability (coplanarity and wire sweep) and reliability (moisture sensitivity level) in the CABGA packages. From factor study, it was clear that molding compound which had high Tg and low shrinkage represents low coplanarity of CABGA packages. Coplanarity of MAP-type CABGA package decreased with increasing Tg and decreasing shrinkage of molding compound. Especially, coplanarity of the said package was found to be linearly proportional to the difference of shrinkage between PCB substrate and molding compound at room temperature. In case of reliability, the amount of absorbed moisture and flexural modulus of molding compounds affected on moisture sensitivity level. Low moisture absorption and flexural modulus are profitable for high reliability-JEDEC Level 3, 30/spl deg/C/60%RH/192 hours at reflow temperature 260/spl deg/C.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927950
R. Coyle, G. Wenger, D. E. Hodges, A. Mawer, D. Cullen, P. Solan
Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of four variations of the ENIG surface finish. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.
{"title":"The effect of variations in nickel/gold surface finish on the assembly quality and attachment reliability of a plastic ball grid array","authors":"R. Coyle, G. Wenger, D. E. Hodges, A. Mawer, D. Cullen, P. Solan","doi":"10.1109/ECTC.2001.927950","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927950","url":null,"abstract":"Electrolytic and electroless Ni/Au are common pad surface finishes on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process often is implemented when there is insufficient space to allow bussing for the more common electrolytic Ni/Au plating. The ENIG process continues to be used despite evidence that it may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. In this investigation a plastic ball grid array (PBGA) test vehicle is used to compare quality and reliability of four variations of the ENIG surface finish. The standard electrolytic Ni/Au surface finish is used as the control cell for the experiment. Ball shear tests and optical and scanning electron microscopy are performed on as-received and thermally preconditioned packages to evaluate package quality prior to assembly. Accelerated temperature cycling (0/+100/spl deg/C and -40/+125/spl deg/C) is used to evaluate solder joint attachment reliability. Detailed failure mode analysis is used to compare the fracture modes in the ball shear and thermal cycled samples in the electroless and electrolytic packages. The results are discussed in terms of the failure modes and the characteristics of the different Ni/Au surface finishes.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927935
T. Suga, M. Howlader, T. Itoh, C. Inaka, Y. Arai, A. Yamauchi
A robot-controlled wafer bonding machine was developed for the bonding of different sizes of wafers ranging up to 8 inches diameter. The features of this equipment are such that: (1) After the automatic parallel adjustment for 8-inch wafers to a margin of error within /spl plusmn/1 /spl mu/m, the X, Y, and /spl theta/ axis alignments are performed, allowing a margin of error within /spl plusmn/0.5 /spl mu/m in bonding accuracy; and (2) Room-temperature bonding is enabled using the surface activated (SAB) bonding concept. 8-inch diameter silicon wafers ware successfully bonded by the SAB process at room temperature for the first time. Preliminary investigations across the interface using an Infrared camera show that no bubbles are visibly present in the bonding region.
{"title":"A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept","authors":"T. Suga, M. Howlader, T. Itoh, C. Inaka, Y. Arai, A. Yamauchi","doi":"10.1109/ECTC.2001.927935","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927935","url":null,"abstract":"A robot-controlled wafer bonding machine was developed for the bonding of different sizes of wafers ranging up to 8 inches diameter. The features of this equipment are such that: (1) After the automatic parallel adjustment for 8-inch wafers to a margin of error within /spl plusmn/1 /spl mu/m, the X, Y, and /spl theta/ axis alignments are performed, allowing a margin of error within /spl plusmn/0.5 /spl mu/m in bonding accuracy; and (2) Room-temperature bonding is enabled using the surface activated (SAB) bonding concept. 8-inch diameter silicon wafers ware successfully bonded by the SAB process at room temperature for the first time. Preliminary investigations across the interface using an Infrared camera show that no bubbles are visibly present in the bonding region.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927933
T. Suga, K. Otsuka
A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.
{"title":"Bump-less interconnect for next generation system packaging","authors":"T. Suga, K. Otsuka","doi":"10.1109/ECTC.2001.927933","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927933","url":null,"abstract":"A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927749
S. Pienimaa, J. Valtanen, R. Heikkila, E. Ristolainen
This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.
{"title":"Stacked thin dice packaging","authors":"S. Pienimaa, J. Valtanen, R. Heikkila, E. Ristolainen","doi":"10.1109/ECTC.2001.927749","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927749","url":null,"abstract":"This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114441484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927791
A. Skipor, L. Leicht
The drive to finer pitch assemblies is in part due to smaller portable products. As these products reduce in size, the thickness of the printed circuit board must also reduce in thickness in proportion to the product size. These assemblies have become more flexible. Many of these products are assembled with area array packaging, which require numerous low-frequency mechanical deflections. The reliability emphasis has become more focused on isothermal bending fatigue. This paper will discuss a test method to evaluate bending fatigue reliability of 1.0 and 0.8 mm pitch area array packaging, the effect of printed circuit board (PCB) thickness, fatigue fracture morphology and its relation to solder joint location. Finite element results will also be presented to support and expand upon the findings in this study.
{"title":"Mechanical bending fatigue reliability and its application to area array packaging","authors":"A. Skipor, L. Leicht","doi":"10.1109/ECTC.2001.927791","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927791","url":null,"abstract":"The drive to finer pitch assemblies is in part due to smaller portable products. As these products reduce in size, the thickness of the printed circuit board must also reduce in thickness in proportion to the product size. These assemblies have become more flexible. Many of these products are assembled with area array packaging, which require numerous low-frequency mechanical deflections. The reliability emphasis has become more focused on isothermal bending fatigue. This paper will discuss a test method to evaluate bending fatigue reliability of 1.0 and 0.8 mm pitch area array packaging, the effect of printed circuit board (PCB) thickness, fatigue fracture morphology and its relation to solder joint location. Finite element results will also be presented to support and expand upon the findings in this study.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114753252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927724
N. Hirose, T. Yoshimura, O. Ibaragi
Easy, convenient and accurate optical component coupling methods have been proposed using self-written waveguides. The effect of this unique method is systematically studied here for two faced multi-mode optical fibers with various gaps. The optical fiber coupling is easily attained and the coupling loss significantly decreases after self-written waveguide formation even with a extended gap, more than 1000 /spl mu/m; the results clearly show that such self-written waveguide coupling is very effective; the waveguides act as "optical solder" in a gap between two optical components. All-solid type self-written waveguide formation and multichannel waveguide formation/connection are also successfully demonstrated; these results expand the application of self-written waveguides in future practical use. Unique, icicle shaped self-written waveguide formation is also described.
{"title":"Optical solder effects of self-written waveguides in optical circuit devices coupling","authors":"N. Hirose, T. Yoshimura, O. Ibaragi","doi":"10.1109/ECTC.2001.927724","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927724","url":null,"abstract":"Easy, convenient and accurate optical component coupling methods have been proposed using self-written waveguides. The effect of this unique method is systematically studied here for two faced multi-mode optical fibers with various gaps. The optical fiber coupling is easily attained and the coupling loss significantly decreases after self-written waveguide formation even with a extended gap, more than 1000 /spl mu/m; the results clearly show that such self-written waveguide coupling is very effective; the waveguides act as \"optical solder\" in a gap between two optical components. All-solid type self-written waveguide formation and multichannel waveguide formation/connection are also successfully demonstrated; these results expand the application of self-written waveguides in future practical use. Unique, icicle shaped self-written waveguide formation is also described.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116961024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927969
O. Yamada, Y. Sawada, M. Harada, T. Yokozuka, A. Yasukawa, H. Moriya, N. Saito, K. Kasai, T. Uda, T. Netsu, K. Koyano
In the HITACHI MP6000 (HDS Skyline Trinium TM), the bipolar-CMOS processor dissipates about 600 W, and the new direct solder-attached cooling (named DiSAC) method has been developed for use with it. In this cooling method, the HDM is supported by the 97Sn/Ag C4 (or CCB; controlled collapse bonding) bumps, which are affected by almost all the deformation that occurs in the power on/off cycle. Hence, the fatigue life of the C4 bumps is most important in the application of this cooling method. In this paper, the causes of C4 bump strain are analyzed by the finite element method, and several techniques for reducing strain are simulated. A new method of estimating the fatigue life of the C4 connections, pseudo-elastic plastic creep analysis (EPC), is developed in order to improve the accuracy of fatigue life calculations, and is used to evaluate the creep strain in a 3D model. Using EPC and experimental C4 power cycle damage data, a new strain-fatigue life curve is defined. Process defects in the direct solder attachment are found to markedly shorten the fatigue life of the C4 connections, and the effects are estimated. All the technological developments presented are implemented in the DiSAC model, and the improvement in reliability is verified by experiment.
{"title":"Improvement of the reliability of the C4 for ultrahigh thermal conduction module with the direct solder-attached cooling system (DiSAC)","authors":"O. Yamada, Y. Sawada, M. Harada, T. Yokozuka, A. Yasukawa, H. Moriya, N. Saito, K. Kasai, T. Uda, T. Netsu, K. Koyano","doi":"10.1109/ECTC.2001.927969","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927969","url":null,"abstract":"In the HITACHI MP6000 (HDS Skyline Trinium TM), the bipolar-CMOS processor dissipates about 600 W, and the new direct solder-attached cooling (named DiSAC) method has been developed for use with it. In this cooling method, the HDM is supported by the 97Sn/Ag C4 (or CCB; controlled collapse bonding) bumps, which are affected by almost all the deformation that occurs in the power on/off cycle. Hence, the fatigue life of the C4 bumps is most important in the application of this cooling method. In this paper, the causes of C4 bump strain are analyzed by the finite element method, and several techniques for reducing strain are simulated. A new method of estimating the fatigue life of the C4 connections, pseudo-elastic plastic creep analysis (EPC), is developed in order to improve the accuracy of fatigue life calculations, and is used to evaluate the creep strain in a 3D model. Using EPC and experimental C4 power cycle damage data, a new strain-fatigue life curve is defined. Process defects in the direct solder attachment are found to markedly shorten the fatigue life of the C4 connections, and the effects are estimated. All the technological developments presented are implemented in the DiSAC model, and the improvement in reliability is verified by experiment.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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