Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298137
Pablo Ilha Vaz, G. Wirth
In this work, the Radiation Hardened by Design (RHBD) of an inverter cell is proposed. The design considers the use of standard CMOS processes with commercial PDK, focusing on fully incorporating the design into CAD tools allowing the automatic place & route. Corners and Monte Carlo simulations were performed in order to analyze and compare the performances between the standard cells and proposed devices in terms of power, delay, and area consumption. The simulated results indicate that by trading of area and circuit density it is possible to synthesize an automated RHBD with an equivalent performance. Moreover, employing enclosed gate technique in both NMOS and PMOS networks improved propagation delay, energy consumption and lead to reduced variability if compared to standard cells.
{"title":"Design and comparative performance simulation of RHBD inverter cells in 180nm CMOS","authors":"Pablo Ilha Vaz, G. Wirth","doi":"10.1109/SBMICRO.2015.7298137","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298137","url":null,"abstract":"In this work, the Radiation Hardened by Design (RHBD) of an inverter cell is proposed. The design considers the use of standard CMOS processes with commercial PDK, focusing on fully incorporating the design into CAD tools allowing the automatic place & route. Corners and Monte Carlo simulations were performed in order to analyze and compare the performances between the standard cells and proposed devices in terms of power, delay, and area consumption. The simulated results indicate that by trading of area and circuit density it is possible to synthesize an automated RHBD with an equivalent performance. Moreover, employing enclosed gate technique in both NMOS and PMOS networks improved propagation delay, energy consumption and lead to reduced variability if compared to standard cells.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298120
R. Assalti, M. Pavanello, D. Flandre, M. de Souza
This paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.
{"title":"Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications","authors":"R. Assalti, M. Pavanello, D. Flandre, M. de Souza","doi":"10.1109/SBMICRO.2015.7298120","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298120","url":null,"abstract":"This paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124328104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298155
L. Barea, A. V. Von Zuben, T. M. Brahim, A. Montagnoli, Michel Hospital, N. Frateschi, G. Cirino
This work reports the fabrication of Fresnel Zone Plates (FZP) by employing a maskless lithography tool based on direct laser writing. The target application areas in this work are to use a micro lens array (MLA) in a wavefront sensor, for optical aberrations quantification in human eye diagnostics or adaptive optical system. This last one is essential in astronomy applications in order to correct the aberrations introduced by earth atmosphere. The fabricated FZP generates illumination points with high-contrast intensity in the focal plane, which is the purpose of the wavefront sensor. This high-contrast image suggests that the employed fabrication process is well controlled and it matches the design parameters.
{"title":"Fresnel Zone Plate array fabricated by maskless lithography","authors":"L. Barea, A. V. Von Zuben, T. M. Brahim, A. Montagnoli, Michel Hospital, N. Frateschi, G. Cirino","doi":"10.1109/SBMICRO.2015.7298155","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298155","url":null,"abstract":"This work reports the fabrication of Fresnel Zone Plates (FZP) by employing a maskless lithography tool based on direct laser writing. The target application areas in this work are to use a micro lens array (MLA) in a wavefront sensor, for optical aberrations quantification in human eye diagnostics or adaptive optical system. This last one is essential in astronomy applications in order to correct the aberrations introduced by earth atmosphere. The fabricated FZP generates illumination points with high-contrast intensity in the focal plane, which is the purpose of the wavefront sensor. This high-contrast image suggests that the employed fabrication process is well controlled and it matches the design parameters.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127092725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298142
J. Herrera-Celis, C. Reyes-Betanzo, A. Orduña-Díaz
This work proposes an interdigitated microelectrode biosensor (IMB), which includes hydrogenated amorphous silicon carbide (a-SiC:H) as surface to be functionalized. Accordingly, two a-SiC:H films are included, one on top of SiO2, and another on top of microelectrodes. The design along with the medium were simulated on CoventorWare® software, taking into account that the IMB proposed will be for the detection of Escherichia coli. The influence of both the a-SiC:H thin film and the capture of bacteria on electrodes on the impedance spectroscopy of the biosensor in the range of 10 kHz to 100 MHz was studied. The results show that the higher the conductivity of the thin film on microelectrodes, the lower is the increase of the magnitude of the impedance spectrum measured in presence of the sterile blank solution, and that the capture of bacteria on microelectrodes increases the sensitivity. The maximum percentage change in the magnitude of impedance of the PIMB is about 45 times greater than that of the conventional interdigitated microelectrode biosensor (CIMB).
{"title":"Design of an interdigitated microelectrode biosensor using a-SiC:H surface to capture E. coli","authors":"J. Herrera-Celis, C. Reyes-Betanzo, A. Orduña-Díaz","doi":"10.1109/SBMICRO.2015.7298142","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298142","url":null,"abstract":"This work proposes an interdigitated microelectrode biosensor (IMB), which includes hydrogenated amorphous silicon carbide (a-SiC:H) as surface to be functionalized. Accordingly, two a-SiC:H films are included, one on top of SiO2, and another on top of microelectrodes. The design along with the medium were simulated on CoventorWare® software, taking into account that the IMB proposed will be for the detection of Escherichia coli. The influence of both the a-SiC:H thin film and the capture of bacteria on electrodes on the impedance spectroscopy of the biosensor in the range of 10 kHz to 100 MHz was studied. The results show that the higher the conductivity of the thin film on microelectrodes, the lower is the increase of the magnitude of the impedance spectrum measured in presence of the sterile blank solution, and that the capture of bacteria on microelectrodes increases the sensitivity. The maximum percentage change in the magnitude of impedance of the PIMB is about 45 times greater than that of the conventional interdigitated microelectrode biosensor (CIMB).","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131967948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298152
G. Sombrio, Frâncio Rodrigues, P. Franzen, P. A. Soave, H. Boudinov
Non-stoichiometric silicon nitride layers were sandwiched between indium thin oxide (transparent contact) and n type silicon substrate. These films were deposited by reactive sputtering from silicon target. The composition and thickness were extracted by Rutherford backscattering spectroscopy measurement. Photo and electroluminescence spectra have been compared and there is a considerable difference between emitted wavelengths. Exponential conduction models (Pool-Frenkel and Fowler-Nordheim) were used to fit the experimental data. A linear correlation between electroluminescence intensity and current density has been observed. Electroluminescence spectra at several temperatures (50 to 300 K) were reported.
{"title":"Photo and electroluminescence from SiNx layers deposited by reactive sputtering","authors":"G. Sombrio, Frâncio Rodrigues, P. Franzen, P. A. Soave, H. Boudinov","doi":"10.1109/SBMICRO.2015.7298152","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298152","url":null,"abstract":"Non-stoichiometric silicon nitride layers were sandwiched between indium thin oxide (transparent contact) and n type silicon substrate. These films were deposited by reactive sputtering from silicon target. The composition and thickness were extracted by Rutherford backscattering spectroscopy measurement. Photo and electroluminescence spectra have been compared and there is a considerable difference between emitted wavelengths. Exponential conduction models (Pool-Frenkel and Fowler-Nordheim) were used to fit the experimental data. A linear correlation between electroluminescence intensity and current density has been observed. Electroluminescence spectra at several temperatures (50 to 300 K) were reported.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121000153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298105
S. Deleonibus
In the future, drastic power consumption reduction will request less energy greedy device, interconnect, computing technologies and architectures. Challenging tomorrow's exponentially growing electronic market, towards Autonomous and Mobile systems for new societal needs, request a drastic reduction towards Zero Intrinsic Variability, Heterogeneous and 3D integration at the device, functional and system levels. Maximizing Energy Efficiency of combined Low Power, High Performance CMOS and Memories to contribute to the energy saving balance at system level, become realistic goals.
{"title":"More moore and more than moore meeting for 3D","authors":"S. Deleonibus","doi":"10.1109/SBMICRO.2015.7298105","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298105","url":null,"abstract":"In the future, drastic power consumption reduction will request less energy greedy device, interconnect, computing technologies and architectures. Challenging tomorrow's exponentially growing electronic market, towards Autonomous and Mobile systems for new societal needs, request a drastic reduction towards Zero Intrinsic Variability, Heterogeneous and 3D integration at the device, functional and system levels. Maximizing Energy Efficiency of combined Low Power, High Performance CMOS and Memories to contribute to the energy saving balance at system level, become realistic goals.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298123
K. Sasaki, C. Navarro, M. Bawedin, F. Andrieu, J. Martino, S. Cristoloveanu
This work aims to study the reliability of the Si film thickness extraction method based on the capacitance derivative analysis in p-i-n gated diodes. Results provided by the derivative procedure are compared to the basic capacitance method (without the derivative). The basic method yields accurate Si-film thicknesses, but it can only be applied to relatively thick body devices where the supercoupling effect does not occur. On the other hand, the use of the derivative analysis is feasible and effective in ultrathin devices. This makes the derivative procedure more suitable for the characterization of the body thickness in advanced FDSOI MOS-like devices.
{"title":"Reliability of film thickness extraction through CV curves of SOI p-i-n gated diodes","authors":"K. Sasaki, C. Navarro, M. Bawedin, F. Andrieu, J. Martino, S. Cristoloveanu","doi":"10.1109/SBMICRO.2015.7298123","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298123","url":null,"abstract":"This work aims to study the reliability of the Si film thickness extraction method based on the capacitance derivative analysis in p-i-n gated diodes. Results provided by the derivative procedure are compared to the basic capacitance method (without the derivative). The basic method yields accurate Si-film thicknesses, but it can only be applied to relatively thick body devices where the supercoupling effect does not occur. On the other hand, the use of the derivative analysis is feasible and effective in ultrathin devices. This makes the derivative procedure more suitable for the characterization of the body thickness in advanced FDSOI MOS-like devices.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114848858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298133
G. Torelly, R. Jakomin, M. Pires, L. Dornelas, R. Prioli, P. G. Caldas, H. Xie, F. Ponce, P. L. Souza
The formation of self-assembled InAs quantum dots is investigated as the growth time increases from 3.6 to 12 seconds at a low growth rate. The morphological evolution from a rough surface at a short length scale to an extended 2D InAs flat area, and finally to the 3D InAs islands is followed using atomic force microscopy, photoluminescence and transmission electron microscopy. We show that micrometer long terraces with 2 and 3 monolayers thicknesses can co-exist even though 3 monolayers is beyond the critical thickness. As the quantum dots are nucleated the 3 monolayers thick terrace is depleted by the 3D islands.
{"title":"From InAs extended monolayer flat 2D terraces to 3D islands grown on GaAs substrates","authors":"G. Torelly, R. Jakomin, M. Pires, L. Dornelas, R. Prioli, P. G. Caldas, H. Xie, F. Ponce, P. L. Souza","doi":"10.1109/SBMICRO.2015.7298133","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298133","url":null,"abstract":"The formation of self-assembled InAs quantum dots is investigated as the growth time increases from 3.6 to 12 seconds at a low growth rate. The morphological evolution from a rough surface at a short length scale to an extended 2D InAs flat area, and finally to the 3D InAs islands is followed using atomic force microscopy, photoluminescence and transmission electron microscopy. We show that micrometer long terraces with 2 and 3 monolayers thicknesses can co-exist even though 3 monolayers is beyond the critical thickness. As the quantum dots are nucleated the 3 monolayers thick terrace is depleted by the 3D islands.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123065422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298144
R. Trevisoli, R. Doria, M. de Souza, M. Pavanello
The aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.
{"title":"Effective channel length in Junctionless Nanowire Transistors","authors":"R. Trevisoli, R. Doria, M. de Souza, M. Pavanello","doi":"10.1109/SBMICRO.2015.7298144","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298144","url":null,"abstract":"The aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/SBMICRO.2015.7298108
A. Cerdeira, F. Avila Herrera, B. Cardoso Paz, M. Estrada, M. Pavanello
This work studies the effect of doping level applied to the extensions on the electrical characteristics of short channel double gate junctionless transistor. Structures with homogeneous doping profile between source and drain contacts and structures with additional doping in the extensions are studied. 2D simulations were performed for structures with doping concentration of 5×1018 and 1019 cm-3, silicon layer thickness of 10 and 15 nm and with/without extensions of 30 nm. Above flat band voltage, the drain current in saturation presents an important decrease for homogeneously doped structures with extensions attributed to the reduction of potentials at high gate voltage. Lower short channel effects, as less threshold voltage roll off and less subthreshold slope take place in this type of structures due to the shift of minimum potential in the extension regions.
{"title":"Role of the extensions in Double-Gate Junctionless MOSFETs in the drain current at high gate voltage","authors":"A. Cerdeira, F. Avila Herrera, B. Cardoso Paz, M. Estrada, M. Pavanello","doi":"10.1109/SBMICRO.2015.7298108","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298108","url":null,"abstract":"This work studies the effect of doping level applied to the extensions on the electrical characteristics of short channel double gate junctionless transistor. Structures with homogeneous doping profile between source and drain contacts and structures with additional doping in the extensions are studied. 2D simulations were performed for structures with doping concentration of 5×1018 and 1019 cm-3, silicon layer thickness of 10 and 15 nm and with/without extensions of 30 nm. Above flat band voltage, the drain current in saturation presents an important decrease for homogeneously doped structures with extensions attributed to the reduction of potentials at high gate voltage. Lower short channel effects, as less threshold voltage roll off and less subthreshold slope take place in this type of structures due to the shift of minimum potential in the extension regions.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133081325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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